Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210114
G. Han, Yue Yang, P. Guo, Chunlei Zhan, Kain Lu Low, K. Goh, B. Liu, E. Toh, Y. Yeo
We report the first comparison study of BTI characteristics of nTFET and nMOSFET with the same high-k/metal gate stack fabricated on the same wafer. NTFETs demonstrate smaller ΔVTH and Gm loss in comparison with the nMOSFET under the same PBTI stress. We speculate that the trapped electrons density in HfO2 gate dielectric above the tunnel junction (TJ) is lower than that above the channel, which leads to the superior PBTI characteristics in nTFET.
{"title":"PBTI characteristics of N-channel tunneling field effect transistor with HfO2 gate dielectric: New insights and physical model","authors":"G. Han, Yue Yang, P. Guo, Chunlei Zhan, Kain Lu Low, K. Goh, B. Liu, E. Toh, Y. Yeo","doi":"10.1109/VLSI-TSA.2012.6210114","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210114","url":null,"abstract":"We report the first comparison study of BTI characteristics of nTFET and nMOSFET with the same high-k/metal gate stack fabricated on the same wafer. NTFETs demonstrate smaller ΔVTH and Gm loss in comparison with the nMOSFET under the same PBTI stress. We speculate that the trapped electrons density in HfO2 gate dielectric above the tunnel junction (TJ) is lower than that above the channel, which leads to the superior PBTI characteristics in nTFET.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115924309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210144
Y. Yeo
Technology options for reducing channel and contact resistances in advanced transistors will be reviewed. Strain engineering techniques for enhancing electron and hole mobilities will be discussed, e.g. novel source/drain (S/D) stressors, buried stressors, novel high stress liners, etc. Also, external series resistance Rext has become a more dominant component of the total resistance between S/D in recent years. Solutions for reducing RC will be discussed. Approaches to reduce electron and hole barrier heights between the metallic contact and S/D region will be discussed.
{"title":"Advanced channel and contact technologies for future CMOS devices","authors":"Y. Yeo","doi":"10.1109/VLSI-TSA.2012.6210144","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210144","url":null,"abstract":"Technology options for reducing channel and contact resistances in advanced transistors will be reviewed. Strain engineering techniques for enhancing electron and hole mobilities will be discussed, e.g. novel source/drain (S/D) stressors, buried stressors, novel high stress liners, etc. Also, external series resistance Rext has become a more dominant component of the total resistance between S/D in recent years. Solutions for reducing RC will be discussed. Approaches to reduce electron and hole barrier heights between the metallic contact and S/D region will be discussed.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131663143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210160
P. Kirsch, R. Hill, J. Huang, W. Loh, T. Kim, M. Wong, B. Min, C. Huffman, D. Veksler, C. Young, K. Ang, I. Ali, R. T. Lee, T. Ngai, A. Wang, W. Wang, T. Cunningham, Y. T. Chen, P. Hung, E. Bersch, B. Sassman, M. Cruz, S. Trammell, R. Droopad, S. Oktybrysky, J. Lee, G. Bersuker, C. Hobbs, R. Jammy
The superior transport properties of III-V materials are promising candidates to achieve improved performance at low power. This paper examines the module challenges of III-V materials in advanced CMOS at or beyond the 10 nm technology node, and reports VLSI compatible epi, junction, contact and gate stack process modules with Xj<;60;10nm, ND=5×1019 cm-3, ρc= 6Ω.μm2 and Dit = 4×1012 eV-1 cm-2. Si VLSI fab and ESH protocols have been developed to enable advanced process flows.
III-V材料优越的输运特性有望在低功率下实现更好的性能。本文研究了III-V材料在10纳米或以上技术节点的先进CMOS中的模块挑战，并报道了XjD=5×1019 cm-3， ρc= 6Ω的VLSI兼容epi，结，触点和栅极堆栈工艺模块。μm2, Dit = 4×1012 eV-1 cm-2。Si VLSI晶圆厂和ESH协议已经开发，以实现先进的工艺流程。
{"title":"Challenges of III–V materials in advanced CMOS logic","authors":"P. Kirsch, R. Hill, J. Huang, W. Loh, T. Kim, M. Wong, B. Min, C. Huffman, D. Veksler, C. Young, K. Ang, I. Ali, R. T. Lee, T. Ngai, A. Wang, W. Wang, T. Cunningham, Y. T. Chen, P. Hung, E. Bersch, B. Sassman, M. Cruz, S. Trammell, R. Droopad, S. Oktybrysky, J. Lee, G. Bersuker, C. Hobbs, R. Jammy","doi":"10.1109/VLSI-TSA.2012.6210160","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210160","url":null,"abstract":"The superior transport properties of III-V materials are promising candidates to achieve improved performance at low power. This paper examines the module challenges of III-V materials in advanced CMOS at or beyond the 10 nm technology node, and reports VLSI compatible epi, junction, contact and gate stack process modules with Xj<;60;10nm, N<sub>D</sub>=5×10<sup>19</sup> cm<sup>-3</sup>, ρ<sub>c</sub>= 6Ω.μm<sup>2</sup> and Dit = 4×10<sup>12</sup> eV<sup>-1</sup> cm<sup>-2</sup>. Si VLSI fab and ESH protocols have been developed to enable advanced process flows.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127004169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210165
G. Roll, S. Jakschik, M. Goldbach, A. Wachowiak, T. Mikolajick, L. Frey
The gate leakage (IGate, table 1) is reduced compared to the conventional 65nm process with SiON dielectric (Fig. 2). The leakage current due to direct tunneling is simulated using the CET as fitting parameter. High-k PFETs with an oxide extension spacer show a decrease in leakage density with reducing channel length, due to an average CET increase of 1Å (Fig. 3). Most likely unintended oxidation of the interlayer at the gate edge by oxygen supply through the spacer causes the CET increase (Fig. 1). The phenomenon is avoided using a nitride extension spacer. But nitride spacers at the inner gate edge are known to lead to increased gate induced drain leakage (GIDL) [8]. A dual oxide nitride extension spacer is sufficient to prevent unintended gate edge oxidation (Fig. 3).
{"title":"Intrinsic MOSFET leakage of high-k peripheral DRAM devices: Measurement and simulation","authors":"G. Roll, S. Jakschik, M. Goldbach, A. Wachowiak, T. Mikolajick, L. Frey","doi":"10.1109/VLSI-TSA.2012.6210165","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210165","url":null,"abstract":"The gate leakage (IGate, table 1) is reduced compared to the conventional 65nm process with SiON dielectric (Fig. 2). The leakage current due to direct tunneling is simulated using the CET as fitting parameter. High-k PFETs with an oxide extension spacer show a decrease in leakage density with reducing channel length, due to an average CET increase of 1Å (Fig. 3). Most likely unintended oxidation of the interlayer at the gate edge by oxygen supply through the spacer causes the CET increase (Fig. 1). The phenomenon is avoided using a nitride extension spacer. But nitride spacers at the inner gate edge are known to lead to increased gate induced drain leakage (GIDL) [8]. A dual oxide nitride extension spacer is sufficient to prevent unintended gate edge oxidation (Fig. 3).","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115656214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210174
L. Peng, J. Fan, H. Li, S. Gao, C. Tan
Wafer-on-wafer stacking is demonstrated successfully using bump-less Cu-Cu bonding for simultaneous formation of electrical connection, mechanical support and hermetic seal. The mechanical strength of the bonded Cu-Cu layer sustains grinding and chemical etching. Daisy chain of at least 44,000 contacts at 15μm pitch is connected successfully. Cu-Cu hermetic seal ring shows helium leak rate >;10X lower than the reject limit without under-fill. This provides robust IC-to-IC connection density of 4.4 × 105 cm-2 suitable for future wafer level 3D integration.
{"title":"Simultaneous formation of electrical connection, mechanical support and hermetic seal with bump-less cu-cu bonding for 3D wafer stacking","authors":"L. Peng, J. Fan, H. Li, S. Gao, C. Tan","doi":"10.1109/VLSI-TSA.2012.6210174","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210174","url":null,"abstract":"Wafer-on-wafer stacking is demonstrated successfully using bump-less Cu-Cu bonding for simultaneous formation of electrical connection, mechanical support and hermetic seal. The mechanical strength of the bonded Cu-Cu layer sustains grinding and chemical etching. Daisy chain of at least 44,000 contacts at 15μm pitch is connected successfully. Cu-Cu hermetic seal ring shows helium leak rate >;10X lower than the reject limit without under-fill. This provides robust IC-to-IC connection density of 4.4 × 105 cm-2 suitable for future wafer level 3D integration.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124829786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210155
C. Ni, X. Fu, N. Yoshida, O. Chan, M. Jin, H. Chen, S. Hung, R. Jakkaraju, S. Kesapragada, C. Lazik, R. Hung, S. Gandikota, C. Chang, A. Brand
Gate-first (GF) high-k metal gate (HKMG) for LSTP/LOP logic and DRAM periphery applications requires an efficient and low-cost effective work function (eWF) solution. We demonstrated TiAlN for pFET eWF tuning without appreciable EOT, Jg, and interface degradation. Hence TiAlN is shown to be a key enabler to realize process-friendly and cost-effective GF HKMG implementation.
{"title":"Gate-first TiAlN P-gate electrode for cost effective high-k metal gate implementation","authors":"C. Ni, X. Fu, N. Yoshida, O. Chan, M. Jin, H. Chen, S. Hung, R. Jakkaraju, S. Kesapragada, C. Lazik, R. Hung, S. Gandikota, C. Chang, A. Brand","doi":"10.1109/VLSI-TSA.2012.6210155","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210155","url":null,"abstract":"Gate-first (GF) high-k metal gate (HKMG) for LSTP/LOP logic and DRAM periphery applications requires an efficient and low-cost effective work function (eWF) solution. We demonstrated TiAlN for pFET eWF tuning without appreciable EOT, Jg, and interface degradation. Hence TiAlN is shown to be a key enabler to realize process-friendly and cost-effective GF HKMG implementation.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"410 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124371493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210150
S. Subramanian, I. Ivana, Y. Yeo
We report a novel n-channel Ultra-Thin Body Field-Effect Transistor (UTB-FET) comprising an embedded Metal Source/Drain (eMSD) formed in a quasi-insulating InAlAs region. The InAlAs barrier layer reduces off-state leakage current IOFF significantly. The eMSD consists of conductive Ni-InGaAs and Ni-InAlAs layers, and has a low sheet resistance Rsh of ~20 Ω/square. This achieves a significant reduction in the parasitic S/D resistance Rsd, as compared with a conventional UTB-FET with thin S/D.
{"title":"Embedded Metal Source/Drain (eMSD) for series resistance reduction in In0.53Ga0.47As n-channel Ultra-Thin Body Field-Effect Transistor (UTB-FET)","authors":"S. Subramanian, I. Ivana, Y. Yeo","doi":"10.1109/VLSI-TSA.2012.6210150","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210150","url":null,"abstract":"We report a novel n-channel Ultra-Thin Body Field-Effect Transistor (UTB-FET) comprising an embedded Metal Source/Drain (eMSD) formed in a quasi-insulating InAlAs region. The InAlAs barrier layer reduces off-state leakage current IOFF significantly. The eMSD consists of conductive Ni-InGaAs and Ni-InAlAs layers, and has a low sheet resistance Rsh of ~20 Ω/square. This achieves a significant reduction in the parasitic S/D resistance Rsd, as compared with a conventional UTB-FET with thin S/D.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133686754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210122
SangBum Kim, P. Du, Jing Li, M. Breitwisch, Y. Zhu, S. Mittal, R. Cheek, T. Hsu, Ming-Hsiu Lee, A. Schrott, Simone Raoux, Huai-Yu Cheng, S. Lai, Jau-Yi Wu, Tien-Yen Wang, Eric A. Joseph, Erh-Kun Lai, A. Ray, H. Lung, C. Lam
We study the effect of programming current on the endurance failure of phase change memory and propose a general scheme of optimizing programming currents for the most endurance cycles. We consider two major endurance failure modes, stuck-SET and open failure. We show that higher current does not necessarily cause, and even prevents the earlier open failure and attribute it to phase-dependent open-failure mechanisms. As for the stuck-SET failure, RESET current is optimized to balance material segregation effect and RESET current margin. The overall programming conditions are optimized by combining open and stuck-SET failure characteristic curves.
{"title":"Optimization of programming current on endurance of phase change memory","authors":"SangBum Kim, P. Du, Jing Li, M. Breitwisch, Y. Zhu, S. Mittal, R. Cheek, T. Hsu, Ming-Hsiu Lee, A. Schrott, Simone Raoux, Huai-Yu Cheng, S. Lai, Jau-Yi Wu, Tien-Yen Wang, Eric A. Joseph, Erh-Kun Lai, A. Ray, H. Lung, C. Lam","doi":"10.1109/VLSI-TSA.2012.6210122","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210122","url":null,"abstract":"We study the effect of programming current on the endurance failure of phase change memory and propose a general scheme of optimizing programming currents for the most endurance cycles. We consider two major endurance failure modes, stuck-SET and open failure. We show that higher current does not necessarily cause, and even prevents the earlier open failure and attribute it to phase-dependent open-failure mechanisms. As for the stuck-SET failure, RESET current is optimized to balance material segregation effect and RESET current margin. The overall programming conditions are optimized by combining open and stuck-SET failure characteristic curves.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"47 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132677080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210113
J. Wan, C. Le Royer, A. Zaslavsky, S. Cristoloveanu
We present a novel switching device named Z2-FET that features zero subthreshold swing and zero impact ionization. The device is built in fully-depleted silicon-on-insulator (FD-SOI) technology and is demonstrated to switch sharply with the subthreshold slope (SS) <; 1 mV/dec and an ION/IOFF current ratio >; 1010. The device further shows large hysteresis in drain current-drain voltage (ID-VD) domain with the turn-on voltage (VON) linearly controlled by gate voltage (VG). Simulation confirms that the operation of the device is determined by the positive feedback between the flow of carriers and their injection barriers.
{"title":"Z2-FET: A zero-slope switching device with gate-controlled hysteresis","authors":"J. Wan, C. Le Royer, A. Zaslavsky, S. Cristoloveanu","doi":"10.1109/VLSI-TSA.2012.6210113","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210113","url":null,"abstract":"We present a novel switching device named Z<sup>2</sup>-FET that features zero subthreshold swing and zero impact ionization. The device is built in fully-depleted silicon-on-insulator (FD-SOI) technology and is demonstrated to switch sharply with the subthreshold slope (SS) <; 1 mV/dec and an I<sub>ON</sub>/I<sub>OFF</sub> current ratio >; 10<sup>10</sup>. The device further shows large hysteresis in drain current-drain voltage (I<sub>D</sub>-V<sub>D</sub>) domain with the turn-on voltage (V<sub>ON</sub>) linearly controlled by gate voltage (V<sub>G</sub>). Simulation confirms that the operation of the device is determined by the positive feedback between the flow of carriers and their injection barriers.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132724569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210104
We Chang, C. Shih, Wen-Fa Wu, C. Lien
An ultralow voltage p-channel Schottky barrier nanowire SONOS memory is reported experimentally with excellent reliability. By applying pure metallic Schottky barrier S/D, the nanowire SONOS memory can operate at a gate voltage of -7V to -11V for hole programming, and 5V to 7V for electron erasing. This Schottky barrier cell exhibits superior 10K cycling and 125°C retention for practical applications.
{"title":"P-channel Schottky barrier nanowire SONOS memory with low-voltage operations and excellent reliability","authors":"We Chang, C. Shih, Wen-Fa Wu, C. Lien","doi":"10.1109/VLSI-TSA.2012.6210104","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210104","url":null,"abstract":"An ultralow voltage p-channel Schottky barrier nanowire SONOS memory is reported experimentally with excellent reliability. By applying pure metallic Schottky barrier S/D, the nanowire SONOS memory can operate at a gate voltage of -7V to -11V for hole programming, and 5V to 7V for electron erasing. This Schottky barrier cell exhibits superior 10K cycling and 125°C retention for practical applications.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"27 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132394534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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