Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210109
M. Vinet
Summary form only given. Recent device developments and achievements have demonstrated that undoped channel Fully depleted SOI devices are becoming a serious alternative to Bulk technologies for 20nm node and below. These architectures have proven that they can provide high drive current together with ensuring low static and dynamic power. This paper gives an overview of the main advantages provided by Fully Depleted technologies, as well as the key challenges that need to be addressed. Electrostatic integrity, drivability, variability and scalability are addressed through silicon data and TCAD analyses. Unique features of planar architectures such as solutions to the Multiple VT challenges and non logic devices (ESD, I/Os) are also reported.
{"title":"MOSFETs transitions towards fully depleted architectures","authors":"M. Vinet","doi":"10.1109/VLSI-TSA.2012.6210109","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210109","url":null,"abstract":"Summary form only given. Recent device developments and achievements have demonstrated that undoped channel Fully depleted SOI devices are becoming a serious alternative to Bulk technologies for 20nm node and below. These architectures have proven that they can provide high drive current together with ensuring low static and dynamic power. This paper gives an overview of the main advantages provided by Fully Depleted technologies, as well as the key challenges that need to be addressed. Electrostatic integrity, drivability, variability and scalability are addressed through silicon data and TCAD analyses. Unique features of planar architectures such as solutions to the Multiple VT challenges and non logic devices (ESD, I/Os) are also reported.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"762 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114001930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210167
C. L. Yang, C. I. Li, G. Lin, W. Chen, C. Tsai, Y. S. Huang, C. Fu, T. Y. Lu, H. Y. Wang, B. Hsu, C. T. Huang, M. Chan, J. Y. Wu, Y. C. Cheng, O. Cheng, B. Guo, S. Lu, H. Gossmann, B. Colombeau, I. Chen
In this paper, we have demonstrated that cryogenic implantation applied to source and drain (SD) extension, pocket/halo and SD formation offers advantages for higher core and SRAM driving current and one order lower Ioff bulk (Ioffb) leakage in NMOS with reduced SRAM defectivity. Atomistic Kinetic Monte Carlo (KMC) modeling confirms that the cryo-implantation has enabled a unique control of active Boron and point defect distribution in the channel/halo region of NMOS.
{"title":"Optimizing state-of-the-art 28nm core/SRAM device performance by cryo-implantation technology","authors":"C. L. Yang, C. I. Li, G. Lin, W. Chen, C. Tsai, Y. S. Huang, C. Fu, T. Y. Lu, H. Y. Wang, B. Hsu, C. T. Huang, M. Chan, J. Y. Wu, Y. C. Cheng, O. Cheng, B. Guo, S. Lu, H. Gossmann, B. Colombeau, I. Chen","doi":"10.1109/VLSI-TSA.2012.6210167","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210167","url":null,"abstract":"In this paper, we have demonstrated that cryogenic implantation applied to source and drain (SD) extension, pocket/halo and SD formation offers advantages for higher core and SRAM driving current and one order lower Ioff bulk (Ioffb) leakage in NMOS with reduced SRAM defectivity. Atomistic Kinetic Monte Carlo (KMC) modeling confirms that the cryo-implantation has enabled a unique control of active Boron and point defect distribution in the channel/halo region of NMOS.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128731045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210124
S. Z. Rahaman, S. Maikap, W. Chen, T. Tien, H. Y. Lee, F. Chen, M. Kao, M. Tsai
Influence of GeOx layer on resistive switching memory performance in a simple and CMOS compatible W/WOx/GeOx:WOx mixture/W structure has been investigated for the first time. All layers are confirmed by both HRTEM and XPS. This memory device has enhanced performance in terms of the resistance ratio, uniformity, and program/erase cycles as compared to W/WOx/W structure. An excellent read endurance and program/erase cycles of >;106 at large Vread of ±1V are obtained. Furthermore, the memory device exhibits robust data retention at 85°C. This device can be operated as low current as 0.1 μA.
{"title":"Excellent resistive switching memory: Influence of GeOx in WOx mixture","authors":"S. Z. Rahaman, S. Maikap, W. Chen, T. Tien, H. Y. Lee, F. Chen, M. Kao, M. Tsai","doi":"10.1109/VLSI-TSA.2012.6210124","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210124","url":null,"abstract":"Influence of GeO<sub>x</sub> layer on resistive switching memory performance in a simple and CMOS compatible W/WO<sub>x</sub>/GeO<sub>x</sub>:WO<sub>x</sub> mixture/W structure has been investigated for the first time. All layers are confirmed by both HRTEM and XPS. This memory device has enhanced performance in terms of the resistance ratio, uniformity, and program/erase cycles as compared to W/WO<sub>x</sub>/W structure. An excellent read endurance and program/erase cycles of >;10<sup>6</sup> at large V<sub>read</sub> of ±1V are obtained. Furthermore, the memory device exhibits robust data retention at 85°C. This device can be operated as low current as 0.1 μA.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125406661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210128
L. Pantisano, G. Zschaetzsch, G. Hellings, R. Krom, S.H. Lee, R. Ritzenthaler, J. Mitard, G. Eneman, P. Roussel, T. Chiarella, L. Ragnarsson, M. Togo, W. Vandervorst, G. Groeseneken, A. Thean, N. Horiguchi
Introduction: Series resistance (Rseries) is a crucial factor for technology optimization and benchmarking [1-3]. Rseries is typically extracted in the bias conditions where Rseries dominates, i.e., linear regime and high Vgs by comparing multiple gate lengths. However this simple extraction is very challenging for sub22nm CMOS devices as changing a device length / width may change mobility or Rseries. For instance, this is the case for SiGe where the built-in stress effect [5,6] increases the channel mobility thus making the standard extraction difficult. The case is even more compelling for the bulk finfet case where the length width and height may not be known with the necessary precision and the gate stack itself may introduce (un)wanted stress components. As any Rseries extraction do rely critically on assumptions, in this paper we will first test the applicability and limits of several Rseries extraction techniques [1-3] and then use the best of both to gain new insights on the finfet and SiGe technology.
{"title":"On the rseries extraction techniques for sub-22nm CMOS finfet and SiGe technologies","authors":"L. Pantisano, G. Zschaetzsch, G. Hellings, R. Krom, S.H. Lee, R. Ritzenthaler, J. Mitard, G. Eneman, P. Roussel, T. Chiarella, L. Ragnarsson, M. Togo, W. Vandervorst, G. Groeseneken, A. Thean, N. Horiguchi","doi":"10.1109/VLSI-TSA.2012.6210128","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210128","url":null,"abstract":"Introduction: Series resistance (Rseries) is a crucial factor for technology optimization and benchmarking [1-3]. Rseries is typically extracted in the bias conditions where Rseries dominates, i.e., linear regime and high Vgs by comparing multiple gate lengths. However this simple extraction is very challenging for sub22nm CMOS devices as changing a device length / width may change mobility or Rseries. For instance, this is the case for SiGe where the built-in stress effect [5,6] increases the channel mobility thus making the standard extraction difficult. The case is even more compelling for the bulk finfet case where the length width and height may not be known with the necessary precision and the gate stack itself may introduce (un)wanted stress components. As any Rseries extraction do rely critically on assumptions, in this paper we will first test the applicability and limits of several Rseries extraction techniques [1-3] and then use the best of both to gain new insights on the finfet and SiGe technology.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129216809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210173
P. Tzeng, Y. Hsin, Jui-Chin Chen, Shang-Chun Chen, Chien-Ying Wu, W. Tsai, Chung-Chih Wang, C. Ho, Chien-Chou Chen, Y. Hsu, S. Shen, S. Liao, C. Chien, Hsiang-Hung Chang, Cha-Hsin Lin, T. Ku, M. Kao
Process issues and challenges of three-dimensional integrated circuit (3DIC) using through-silicon-via (TSV) are extensively investigated. Key enabling process technologies in the TSV formation and thin wafer handling are discussed with a viewpoint of TSV process integration. Test element groups (TEG) are designed to characterize the process performance and optimizations of some key process modules are also provided as process guidelines.
{"title":"Key enabling technologies of 300mm 3DIC process integration","authors":"P. Tzeng, Y. Hsin, Jui-Chin Chen, Shang-Chun Chen, Chien-Ying Wu, W. Tsai, Chung-Chih Wang, C. Ho, Chien-Chou Chen, Y. Hsu, S. Shen, S. Liao, C. Chien, Hsiang-Hung Chang, Cha-Hsin Lin, T. Ku, M. Kao","doi":"10.1109/VLSI-TSA.2012.6210173","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210173","url":null,"abstract":"Process issues and challenges of three-dimensional integrated circuit (3DIC) using through-silicon-via (TSV) are extensively investigated. Key enabling process technologies in the TSV formation and thin wafer handling are discussed with a viewpoint of TSV process integration. Test element groups (TEG) are designed to characterize the process performance and optimizations of some key process modules are also provided as process guidelines.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130422093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The random telegraph noise (RTN) is becoming a critical issue for variability and reliability in nanoscale MOSFETs. Since devices actually operate under AC signals in digital circuits, it is essential to investigate the AC RTN at dynamic voltage, instead of traditional DC RTN at fixed gate bias. In this paper, the AC RTN in nano-MOSFETs is experimentally studied in detail, with the focus on the time domain. Various RTN parameters are investigated, in terms of frequency dependence and bias dependence, which are important for robust circuit design against RTN.
{"title":"New observations on the AC random telegraph noise (AC RTN) in nano-MOSFETs","authors":"Runsheng Wang, Jibin Zou, Xiaoqing Xu, Changze Liu, Jinhua Liu, Hanming Wu, Yangyuan Wang, Ru Huang","doi":"10.1109/VLSI-TSA.2012.6210146","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210146","url":null,"abstract":"The random telegraph noise (RTN) is becoming a critical issue for variability and reliability in nanoscale MOSFETs. Since devices actually operate under AC signals in digital circuits, it is essential to investigate the AC RTN at dynamic voltage, instead of traditional DC RTN at fixed gate bias. In this paper, the AC RTN in nano-MOSFETs is experimentally studied in detail, with the focus on the time domain. Various RTN parameters are investigated, in terms of frequency dependence and bias dependence, which are important for robust circuit design against RTN.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123647713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210154
M. Jo, C. Kang, K. Ang, J. Huang, P. Kirsch, R. Jammy
Stress-induced leakage current (SILC) behavior in full gate-last (FGL) high-k/metal gate devices was evaluated and compared to gate-first (GF) devices. To improve SILC characteristics, Zr was introduced into the high-k bulk region. Incorporating Zr can reduce SILC in both FGL and GF devices by suppressing trap generation in the high-k bulk region under time-dependent dielectric breakdown (TDDB) stress. However, the interfacial layer quality can be a critical SILC issue in FGL devices.
{"title":"Understanding and improving SILC behavior under TDDB stress in full gate-last high-k/metal gate nMOSFETs","authors":"M. Jo, C. Kang, K. Ang, J. Huang, P. Kirsch, R. Jammy","doi":"10.1109/VLSI-TSA.2012.6210154","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210154","url":null,"abstract":"Stress-induced leakage current (SILC) behavior in full gate-last (FGL) high-k/metal gate devices was evaluated and compared to gate-first (GF) devices. To improve SILC characteristics, Zr was introduced into the high-k bulk region. Incorporating Zr can reduce SILC in both FGL and GF devices by suppressing trap generation in the high-k bulk region under time-dependent dielectric breakdown (TDDB) stress. However, the interfacial layer quality can be a critical SILC issue in FGL devices.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123670802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210118
H. Na, T. Endoh
A new charge pump with the multi-pillar VMOS has been proposed and its performances for different ratio of the pillar diameter and the pillar space in the multi-pillar have been evaluated. As the results, it is clarified that the proposed charge pump realizes the best performances when the ratio is 1. The proposed charge pump realizes a 24% increased output current with 2.88% improved efficiency and a 0.7V higher VPP with 19% shorter VPP generation time than the conventional charge pump with the single-pillar VMOS.
{"title":"A high efficient and compact charge pump with multi-pillar vertical MOSFET","authors":"H. Na, T. Endoh","doi":"10.1109/VLSI-TSA.2012.6210118","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210118","url":null,"abstract":"A new charge pump with the multi-pillar VMOS has been proposed and its performances for different ratio of the pillar diameter and the pillar space in the multi-pillar have been evaluated. As the results, it is clarified that the proposed charge pump realizes the best performances when the ratio is 1. The proposed charge pump realizes a 24% increased output current with 2.88% improved efficiency and a 0.7V higher VPP with 19% shorter VPP generation time than the conventional charge pump with the single-pillar VMOS.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115447043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210115
R. Nathanael, J. Jeon, I. Chen, Yenhao Chen, Fred F. Chen, H. Kam, T. Liu
Multi-functional digital logic circuits, each utilizing only two relays, are demonstrated for the first time. This work can be extended to relay designs comprising greater than two input electrodes and/or greater than two sets of source/drain electrodes, for more compact realization of zero-leakage digital ICs in the future.
{"title":"Multi-input/multi-output relay design for more compact and versatile implementation of digital logic with zero leakage","authors":"R. Nathanael, J. Jeon, I. Chen, Yenhao Chen, Fred F. Chen, H. Kam, T. Liu","doi":"10.1109/VLSI-TSA.2012.6210115","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210115","url":null,"abstract":"Multi-functional digital logic circuits, each utilizing only two relays, are demonstrated for the first time. This work can be extended to relay designs comprising greater than two input electrodes and/or greater than two sets of source/drain electrodes, for more compact realization of zero-leakage digital ICs in the future.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121843019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210112
Sangbum Kim, C. Lam
Historically, transition of memory technologies has been enabled by not only disruptive new features of the memory technology but also new applications which proved the core value of those new features. As improvement of prevalent memory technologies is becoming more challenging, many resources have been devoted to development of emerging memory technologies. In this regard, characteristics of emerging memory technologies such as PCM, STT-MRAM, and RRAM will be reviewed to evaluate its potential of becoming transformational memory technology.
{"title":"Transition of memory technologies","authors":"Sangbum Kim, C. Lam","doi":"10.1109/VLSI-TSA.2012.6210112","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210112","url":null,"abstract":"Historically, transition of memory technologies has been enabled by not only disruptive new features of the memory technology but also new applications which proved the core value of those new features. As improvement of prevalent memory technologies is becoming more challenging, many resources have been devoted to development of emerging memory technologies. In this regard, characteristics of emerging memory technologies such as PCM, STT-MRAM, and RRAM will be reviewed to evaluate its potential of becoming transformational memory technology.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123957381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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