Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210148
E. Hsieh, S. Chung, J.C. Wang, C. S. Lai, C. Tsai, R. Huang, C. Tsai, C. Liang
In this paper, we have studied the Id variation in linear and saturation region by considering the strain-induced effect and the carrier transport of strained CMOS devices. It was found that the origin of linear Id variation comes from the mobility scattering; while in saturation region, the Id variation is dominated by the injection velocity. The higher the injection velocity is, the smaller the saturation Id variation becomes. These results provide us a guideline for achieving good variability control of strain-based CMOS technologies.
{"title":"New criteria for the RDF induced drain current variation considering strain and transport effects in strain-silicon CMOS devices","authors":"E. Hsieh, S. Chung, J.C. Wang, C. S. Lai, C. Tsai, R. Huang, C. Tsai, C. Liang","doi":"10.1109/VLSI-TSA.2012.6210148","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210148","url":null,"abstract":"In this paper, we have studied the Id variation in linear and saturation region by considering the strain-induced effect and the carrier transport of strained CMOS devices. It was found that the origin of linear Id variation comes from the mobility scattering; while in saturation region, the Id variation is dominated by the injection velocity. The higher the injection velocity is, the smaller the saturation Id variation becomes. These results provide us a guideline for achieving good variability control of strain-based CMOS technologies.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"418 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124254133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210129
C. Sohn, C. Kang, R. Baek, D. Choi, H. Sagong, E. Jeong, Jeong-Soo Lee, P. Kirsch, R. Jammy, J. Lee, Y. Jeong
We quantitatively compared the parasitic capacitance of the planar FETs and the DG FinFETs. Optimization with a fixed Sfin-to-Hfin ratio significantly reduces Cpara/W, which renders DG FinFETs comparable to planar FETs. Process variation on Wfin and Hfin should be controlled, otherwise, the Cpara uniformity will be worse for DG FinFETs than it is planar FETs.
{"title":"Comparative study of geometry-dependent capacitances of planar FETs and double-gate FinFETs: Optimization and process variation","authors":"C. Sohn, C. Kang, R. Baek, D. Choi, H. Sagong, E. Jeong, Jeong-Soo Lee, P. Kirsch, R. Jammy, J. Lee, Y. Jeong","doi":"10.1109/VLSI-TSA.2012.6210129","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210129","url":null,"abstract":"We quantitatively compared the parasitic capacitance of the planar FETs and the DG FinFETs. Optimization with a fixed Sfin-to-H<sub>fin</sub> ratio significantly reduces C<sub>para</sub>/W, which renders DG FinFETs comparable to planar FETs. Process variation on W<sub>fin</sub> and H<sub>fin</sub> should be controlled, otherwise, the C<sub>para</sub> uniformity will be worse for DG FinFETs than it is planar FETs.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133270308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210162
C. Tsai, C. Yang, C. Hsu, C. M. Lai, K. Y. Lo, C. G. Chen, R. Huang, C. T. Tsai, L. Hung, J. You, W. Hung, T. F. Chen, O. Cheng, J. Y. Wu, S. F. Tzou, C. Liang, I. Chen
High-K/Metal-Gate (HK/MG) reliability TDDB and BTI are investigated systematically for the first time through HfZrOx gate stack engineering. To meet reliability requirements, it is shown that the HK film thickness, the position and concentration of a Zr dopant, utilizing post deposition anneal (PDA), and decoupled plasma nitridation (DPN) are important factors.
{"title":"Characteristics of HfZrOx gate stack engineering for reliability improvement on 28nm HK/MG CMOS technology","authors":"C. Tsai, C. Yang, C. Hsu, C. M. Lai, K. Y. Lo, C. G. Chen, R. Huang, C. T. Tsai, L. Hung, J. You, W. Hung, T. F. Chen, O. Cheng, J. Y. Wu, S. F. Tzou, C. Liang, I. Chen","doi":"10.1109/VLSI-TSA.2012.6210162","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210162","url":null,"abstract":"High-K/Metal-Gate (HK/MG) reliability TDDB and BTI are investigated systematically for the first time through HfZrOx gate stack engineering. To meet reliability requirements, it is shown that the HK film thickness, the position and concentration of a Zr dopant, utilizing post deposition anneal (PDA), and decoupled plasma nitridation (DPN) are important factors.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130532449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210126
W. Banerjee, S. Maikap
The improvement in resistive switching memory parameters by embedding IrOx nanodots in IrOx/AlOx/IrOx NDs/AlOx/W cross-point structure is reported. The fabricated memory devices exhibit MLC operation of both LRS and HRS, excellent read endurance of >;106 times, program/erase endurance of >;105 cycles, robust data retention of >;104s at 125°C with a small operation voltage of ±2V and a low CC of <;200 μA.
{"title":"Improvement of resistive switching memory parameters using IrOx Nanodots in high-κ AlOx Cross-Point","authors":"W. Banerjee, S. Maikap","doi":"10.1109/VLSI-TSA.2012.6210126","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210126","url":null,"abstract":"The improvement in resistive switching memory parameters by embedding IrO<sub>x</sub> nanodots in IrO<sub>x</sub>/AlO<sub>x</sub>/IrO<sub>x</sub> NDs/AlO<sub>x</sub>/W cross-point structure is reported. The fabricated memory devices exhibit MLC operation of both LRS and HRS, excellent read endurance of >;10<sup>6</sup> times, program/erase endurance of >;10<sup>5</sup> cycles, robust data retention of >;10<sup>4</sup>s at 125°C with a small operation voltage of ±2V and a low CC of <;200 μA.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120943423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210102
D. Gilmer, S. Koveshnikov, B. Butcher, G. Bersuker, A. Kalantarian, M. Sung, R. Geer, Y. Nishi, P. Kirsch, R. Jammy
Low operation current and voltage range are required for scaled low power RRAM devices in high density memory cell arrays. In this work, for the first time we demonstrate 1 uA, +/- 1V bipolar switching of TiN/HfOx/Zr/W RRAM devices. High switching performance up to 108 cycles at low power and a 100× reduction of the high-resistance-state current was achieved by identification and utilization of key parameters for establishing superior control of the conductive filament formation.
{"title":"Superior filament formation control in HfO2 based RRAM for high-performance low-power operation of 1 µA to 20 µA at +/− 1V","authors":"D. Gilmer, S. Koveshnikov, B. Butcher, G. Bersuker, A. Kalantarian, M. Sung, R. Geer, Y. Nishi, P. Kirsch, R. Jammy","doi":"10.1109/VLSI-TSA.2012.6210102","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210102","url":null,"abstract":"Low operation current and voltage range are required for scaled low power RRAM devices in high density memory cell arrays. In this work, for the first time we demonstrate 1 uA, +/- 1V bipolar switching of TiN/HfOx/Zr/W RRAM devices. High switching performance up to 108 cycles at low power and a 100× reduction of the high-resistance-state current was achieved by identification and utilization of key parameters for establishing superior control of the conductive filament formation.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123435156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210151
Lanxiang Wang, G. Han, S. Su, Qian Zhou, Yue Yang, P. Guo, Wei Wang, Y. Tong, P. S. Lim, C. Xue, Qiming Wang, B. Cheng, Y. Yeo
We report a novel metal stanogermanide contact metallization process for high-mobility germanium-tin (Ge0.947Sn0.053 or GeSn) channel p-MOSFETs. Nickel-Platinum (NiPt) alloy was used to react with GeSn to form a multi-phase Ni and Pt stanogermanide [NiGeSn+Ptx(GeSn)y] contact on epitaxial Ge0.947Sn0.053. Rapid thermal annealing of co-sputtered Ni and Pt on GeSn/Ge (100) at temperatures from 350 °C to 550 °C in N2 was used for the stanogermanide formation. Compared with nickel stanogermanide (NiGeSn) contact, the Pt-incorporated contact, i.e. NiGeSn+Ptx(GeSn)y, exhibits enhanced thermal stability in a wide range of formation temperatures.
{"title":"Metal stanogermanide contacts with enhanced thermal stability for high mobility germanium-tin field-effect transistor","authors":"Lanxiang Wang, G. Han, S. Su, Qian Zhou, Yue Yang, P. Guo, Wei Wang, Y. Tong, P. S. Lim, C. Xue, Qiming Wang, B. Cheng, Y. Yeo","doi":"10.1109/VLSI-TSA.2012.6210151","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210151","url":null,"abstract":"We report a novel metal stanogermanide contact metallization process for high-mobility germanium-tin (Ge<sub>0.947</sub>Sn<sub>0.053</sub> or GeSn) channel p-MOSFETs. Nickel-Platinum (NiPt) alloy was used to react with GeSn to form a multi-phase Ni and Pt stanogermanide [NiGeSn+Pt<sub>x</sub>(GeSn)<sub>y</sub>] contact on epitaxial Ge<sub>0.947</sub>Sn<sub>0.053</sub>. Rapid thermal annealing of co-sputtered Ni and Pt on GeSn/Ge (100) at temperatures from 350 °C to 550 °C in N<sub>2</sub> was used for the stanogermanide formation. Compared with nickel stanogermanide (NiGeSn) contact, the Pt-incorporated contact, i.e. NiGeSn+Pt<sub>x</sub>(GeSn)<sub>y</sub>, exhibits enhanced thermal stability in a wide range of formation temperatures.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"15 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123699376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210110
S. Wurm
Today's materials and tool infrastructure is supporting EUVL for pilot line applications with industry efforts focused on addressing the remaining challenges to introduce EUV into HVM at the 22 nm half-pitch in 2014/15. Ensuring EUV extendibility to the sub-16 nm half-pitch will require additional efforts, such as enabling the research and development tools to support the materials development for next generation EUV resist and EUV mask technology. SEMATECH is leading this industry effort. With the introduction of EUVL, SEMATECH's lithography focus is shifting towards addressing the challenges for patterning at the ≤ 10 nm half-pitch.
{"title":"Transition to EUV lithography","authors":"S. Wurm","doi":"10.1109/VLSI-TSA.2012.6210110","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210110","url":null,"abstract":"Today's materials and tool infrastructure is supporting EUVL for pilot line applications with industry efforts focused on addressing the remaining challenges to introduce EUV into HVM at the 22 nm half-pitch in 2014/15. Ensuring EUV extendibility to the sub-16 nm half-pitch will require additional efforts, such as enabling the research and development tools to support the materials development for next generation EUV resist and EUV mask technology. SEMATECH is leading this industry effort. With the introduction of EUVL, SEMATECH's lithography focus is shifting towards addressing the challenges for patterning at the ≤ 10 nm half-pitch.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130015290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210153
J. Yum, G. Bersuker, T. Hudnall, C. Bielawski, P. Kirsch, S. Banerjee
To overcome the issues of mobility degradation and charge trapping between the Si channel and high-k gate dielectric in metal-oxide-semiconductor field effect transistors (MOSFETs), thin BeO layers are deposited by atomic layer deposition (ALD) between (100) p-Si substrates and HfO2 high-k gate dielectric as an alternative interface passivation layer (IPL) to SiO2. We discuss the electrical properties of BeO/HfO2 gate stacks in MOSFETs. Compared to SiO2/HfO2 and Al2O3/HfO2 reference gate stacks, the novel dielectric, BeO, exhibits high drive current, slightly elevated transconductance (Gm), low subthreshold swing (SS), and high mobility at a high electric field.
{"title":"A study of novel ALD beryllium oxide as an interface passivation layer for Si MOS devices","authors":"J. Yum, G. Bersuker, T. Hudnall, C. Bielawski, P. Kirsch, S. Banerjee","doi":"10.1109/VLSI-TSA.2012.6210153","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210153","url":null,"abstract":"To overcome the issues of mobility degradation and charge trapping between the Si channel and high-k gate dielectric in metal-oxide-semiconductor field effect transistors (MOSFETs), thin BeO layers are deposited by atomic layer deposition (ALD) between (100) p-Si substrates and HfO<sub>2</sub> high-k gate dielectric as an alternative interface passivation layer (IPL) to SiO<sub>2</sub>. We discuss the electrical properties of BeO/HfO<sub>2</sub> gate stacks in MOSFETs. Compared to SiO<sub>2</sub>/HfO<sub>2</sub> and Al<sub>2</sub>O<sub>3</sub>/HfO<sub>2</sub> reference gate stacks, the novel dielectric, BeO, exhibits high drive current, slightly elevated transconductance (G<sub>m</sub>), low subthreshold swing (SS), and high mobility at a high electric field.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133764459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210161
S. Deora, G. Bersuker, C. Young, J. Huang, K. Matthews, K. Ang, T. Nagi, C. Hobbs, P. Kirsch, R. Jammy
PBTI in the HfxZryO gate dielectric low temperature full gate last process flow nMOSFETs was demonstrated to be reduced compared to the HfO2 gate dielectric devices of a similar EOT. PBTI degradation in both stacks was successfully modeled within a common framework of fast and slow electron trapping components in the gate dielectrics. The fast component was assigned to the resonance electron trapping in the pre-existing high-κ dielectric defects while a slow, temperature dependent component could be attributed to the migration of the trapped electrons to unoccupied defect sites. Lower PBTI degradation in the Zr:HfO2 stack was shown to be caused by a smaller fast electron trapping component.
{"title":"PBTI improvement in gate last HfO2 gate dielectric nMOSFET due to Zr incorporation","authors":"S. Deora, G. Bersuker, C. Young, J. Huang, K. Matthews, K. Ang, T. Nagi, C. Hobbs, P. Kirsch, R. Jammy","doi":"10.1109/VLSI-TSA.2012.6210161","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210161","url":null,"abstract":"PBTI in the HfxZryO gate dielectric low temperature full gate last process flow nMOSFETs was demonstrated to be reduced compared to the HfO2 gate dielectric devices of a similar EOT. PBTI degradation in both stacks was successfully modeled within a common framework of fast and slow electron trapping components in the gate dielectrics. The fast component was assigned to the resonance electron trapping in the pre-existing high-κ dielectric defects while a slow, temperature dependent component could be attributed to the migration of the trapped electrons to unoccupied defect sites. Lower PBTI degradation in the Zr:HfO2 stack was shown to be caused by a smaller fast electron trapping component.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126516657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210164
K. Tu, C. Wang, Y. Hsieh, Y. Ting, C. Chang, C. Pai, K. Tzeng, H. Chu, H. L. Lin, Y. Chang, C. Pen, K. W. Chen, T. Hsieh, C. Tsai, K. C. Huang, W. Chiang, M. Wang, C. Wang, C. Tsai, S. Wuu, H. Hwang, L. Tran
A cylinder-type Metal-Insulator-Metal (MIM) capacitor integrated with advanced 28nm logic High-K/Metal-Gate (HKMG) process for embedded DRAM has been developed. The stacked cell capacitor is formed using low temperature high-K dielectrics to achieve sufficient storage capacitance without significantly impacting logic transistors. This paper describes techniques to achieve cylinder-type MIM capacitor's capacitance >;10fF/cell and keep the low leakage (<;0.1fA/cell) requirements. The MIM dielectric reliability test passes Time Dependent Dielectric Breakdown (TDDB) lifetime (>;10 years). The test vehicle is composed of 72 macros of 4.5Mb each. We successfully demonstrate fully functional good yield of 28nm eDRAM 324Mb test vehicle with access speed >;330MHz.
{"title":"A high density cylinder-type MIM capacitor integrated with advanced 28nm logic High-K/Metal-Gate process for embedded DRAM","authors":"K. Tu, C. Wang, Y. Hsieh, Y. Ting, C. Chang, C. Pai, K. Tzeng, H. Chu, H. L. Lin, Y. Chang, C. Pen, K. W. Chen, T. Hsieh, C. Tsai, K. C. Huang, W. Chiang, M. Wang, C. Wang, C. Tsai, S. Wuu, H. Hwang, L. Tran","doi":"10.1109/VLSI-TSA.2012.6210164","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210164","url":null,"abstract":"A cylinder-type Metal-Insulator-Metal (MIM) capacitor integrated with advanced 28nm logic High-K/Metal-Gate (HKMG) process for embedded DRAM has been developed. The stacked cell capacitor is formed using low temperature high-K dielectrics to achieve sufficient storage capacitance without significantly impacting logic transistors. This paper describes techniques to achieve cylinder-type MIM capacitor's capacitance >;10fF/cell and keep the low leakage (<;0.1fA/cell) requirements. The MIM dielectric reliability test passes Time Dependent Dielectric Breakdown (TDDB) lifetime (>;10 years). The test vehicle is composed of 72 macros of 4.5Mb each. We successfully demonstrate fully functional good yield of 28nm eDRAM 324Mb test vehicle with access speed >;330MHz.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131141408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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