Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210120
Haesoo Kim, Kangbin Lee, K. Han, Seokwon Cho, Se Kyoung Choi, S. Seo, J. Chung, K. Lee, Sungjae Chung, K. Noh, Tae-Un Youn, Ju Yeab Lee, Min Kyu Lee, B. Han, S. M. Yi, H. Lee, Sung Soon Kim, W. S. Shin, K. Yun, M. Ko, J. Choi, Sang Wan Lee, Sang Deok Kim, Myung Kyu Ahn, Ki Seog Kim, Y. Jeon, Sung Kye Park, S. Aritome, Jin Woong Kim, Sang Sun Lee, S. Lee, K. Ahn, Sung-Joo Hong, G. Bae, S. Park
We developed the new control gate (CG) material and structure in order to overcome scaling limitation beyond 20nm NAND flash cell. New CG material can achieve excellent gap-fill without void and improvement of the Gate CD Gap (GCG). And also, by using new CG material, CG depletion between floating gate (FG) can be improved. As a result, gate coupling ratio, bit-line (BL) interference and tail-cell Vt distribution are drastically improved. These technologies play an important role in the characteristic of scaled NAND flash memory cell and reliability.
{"title":"Optimization of control gate material and structure for enhancing 20nm 64Gb NAND flash reliability","authors":"Haesoo Kim, Kangbin Lee, K. Han, Seokwon Cho, Se Kyoung Choi, S. Seo, J. Chung, K. Lee, Sungjae Chung, K. Noh, Tae-Un Youn, Ju Yeab Lee, Min Kyu Lee, B. Han, S. M. Yi, H. Lee, Sung Soon Kim, W. S. Shin, K. Yun, M. Ko, J. Choi, Sang Wan Lee, Sang Deok Kim, Myung Kyu Ahn, Ki Seog Kim, Y. Jeon, Sung Kye Park, S. Aritome, Jin Woong Kim, Sang Sun Lee, S. Lee, K. Ahn, Sung-Joo Hong, G. Bae, S. Park","doi":"10.1109/VLSI-TSA.2012.6210120","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210120","url":null,"abstract":"We developed the new control gate (CG) material and structure in order to overcome scaling limitation beyond 20nm NAND flash cell. New CG material can achieve excellent gap-fill without void and improvement of the Gate CD Gap (GCG). And also, by using new CG material, CG depletion between floating gate (FG) can be improved. As a result, gate coupling ratio, bit-line (BL) interference and tail-cell Vt distribution are drastically improved. These technologies play an important role in the characteristic of scaled NAND flash memory cell and reliability.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116698801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210130
Chun-Hsien Chiang, M. Fan, J. Kuo, P. Su
We investigate and report the body-effect induced variability in Bulk tri-gate MOSFETs. Through 3-D atomistic simulation, the random dopant fluctuations in the Punch-Through-Stopper (PTS) region of Bulk tri-gate devices are examined. Our study indicates that to achieve an efficient threshold-voltage modulation through substrate bias, the high-doping PTS region may introduce excess variation in Bulk tri-gate devices. This effect has to be considered when one-to-one comparisons between Bulk tri-gate and SOI tri-gate regarding device variability are made.
{"title":"Body effect induced variability in Bulk tri-gate MOSFETs","authors":"Chun-Hsien Chiang, M. Fan, J. Kuo, P. Su","doi":"10.1109/VLSI-TSA.2012.6210130","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210130","url":null,"abstract":"We investigate and report the body-effect induced variability in Bulk tri-gate MOSFETs. Through 3-D atomistic simulation, the random dopant fluctuations in the Punch-Through-Stopper (PTS) region of Bulk tri-gate devices are examined. Our study indicates that to achieve an efficient threshold-voltage modulation through substrate bias, the high-doping PTS region may introduce excess variation in Bulk tri-gate devices. This effect has to be considered when one-to-one comparisons between Bulk tri-gate and SOI tri-gate regarding device variability are made.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131766068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210127
K. Akarvardar, C. Young, D. Veksler, K. Ang, I. Ok, M. Rodgers, V. Kaushik, S. Novak, J. Nadeau, M. Baykan, H. Madan, P. Hung, T. Ngai, H. Stamper, S. Bennett, D. Franca, M. Rao, S. Gausepohl, P. Majhi, C. Hobbs, P. Kirsch, R. Jammy
The impact of fin doping (B, P, As) on FinFET device parameters is studied for high-K/midgap metal gate SOI FinFETs. For a fin width of ~25 nm, >;1 V VT modulation is demonstrated from accumulation mode (AM) to inversion mode (IM). IM FinFETs improve short channel FinFET electrostatics, on-off ratio, and VT variability compared to their undoped counterparts. The same parameters degrade in accumulation mode FinFETs. A VT modulation of ±0.25 V using fin B and P doping comes at the expense of 24% and 14% high field mobility penalty for NFET and PFET, respectively. For the same dose, Arsenic is found to modulate the VT more effectively than does Phosphorus. Basic modeling results show that for aggressively scaled (5 nm-wide) fins, the impact of single dopant atom on VT can be as high as 25 mV, severely challenging the viability of the technique towards the end of roadmap.
{"title":"Performance and variability in multi-VT FinFETs using fin doping","authors":"K. Akarvardar, C. Young, D. Veksler, K. Ang, I. Ok, M. Rodgers, V. Kaushik, S. Novak, J. Nadeau, M. Baykan, H. Madan, P. Hung, T. Ngai, H. Stamper, S. Bennett, D. Franca, M. Rao, S. Gausepohl, P. Majhi, C. Hobbs, P. Kirsch, R. Jammy","doi":"10.1109/VLSI-TSA.2012.6210127","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210127","url":null,"abstract":"The impact of fin doping (B, P, As) on FinFET device parameters is studied for high-K/midgap metal gate SOI FinFETs. For a fin width of ~25 nm, >;1 V VT modulation is demonstrated from accumulation mode (AM) to inversion mode (IM). IM FinFETs improve short channel FinFET electrostatics, on-off ratio, and VT variability compared to their undoped counterparts. The same parameters degrade in accumulation mode FinFETs. A VT modulation of ±0.25 V using fin B and P doping comes at the expense of 24% and 14% high field mobility penalty for NFET and PFET, respectively. For the same dose, Arsenic is found to modulate the VT more effectively than does Phosphorus. Basic modeling results show that for aggressively scaled (5 nm-wide) fins, the impact of single dopant atom on VT can be as high as 25 mV, severely challenging the viability of the technique towards the end of roadmap.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"29 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114119813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210111
S. Arkalgud
Summary form only given. Envisioning greater functionality, higher performance and lower power consumption, the semiconductor industry is introducing the first products with 3D interconnects into volume manufacturing. This presentation will trace the transition from planar to 3D interconnects by beginning with the key issues which confronted the scaling of 2D interconnects. The second part of the talk will cover the current status and the enablement of the supply chain, The final part of this presentation will discuss the potential trends for 3D IC in the future years.
{"title":"Planar interconnects to 3D interconnects","authors":"S. Arkalgud","doi":"10.1109/VLSI-TSA.2012.6210111","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210111","url":null,"abstract":"Summary form only given. Envisioning greater functionality, higher performance and lower power consumption, the semiconductor industry is introducing the first products with 3D interconnects into volume manufacturing. This presentation will trace the transition from planar to 3D interconnects by beginning with the key issues which confronted the scaling of 2D interconnects. The second part of the talk will cover the current status and the enablement of the supply chain, The final part of this presentation will discuss the potential trends for 3D IC in the future years.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129967683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210119
Xinke Liu, Chunlei Zhan, K. W. Chan, Wei Liu, L. Tan, K. Teo, K. J. Chen, Y. Yeo
AlGaN/GaN MOS-HEMTs on a silicon platform were realized using a CMOS-compatible gold-free process. Process modules commonly used in CMOS were used, including gate stack formation, etching modules, etc. Ron of 3 mΩ.cm2 was obtained. Breakdown voltage VBR of 800 V was achieved, the highest for LGD below 10 μm for AlGaN/GaN/Si MOS-HEMTs fabricated using a gold-free process. The devices could be generally useful for cost-competitive power switching circuits with supply voltage in the range of several hundred volts.
采用与cmos兼容的无金工艺，在硅平台上实现了AlGaN/GaN mos - hemt。采用了CMOS中常用的工艺模块，包括栅极堆叠形成、蚀刻模块等。Ron (3) mΩ。得到Cm2。采用无金工艺制备的AlGaN/GaN/Si mos - hemt的击穿电压VBR为800 V，在LGD小于10 μm时达到最高。该器件通常可用于具有成本竞争力的电源电压在几百伏范围内的电源开关电路。
{"title":"AlGaN/GaN-on-Silicon MOS-HEMTs with breakdown voltage of 800 V and on-state resistance of 3 mΩ.cm2 using a CMOS-compatible gold-free process","authors":"Xinke Liu, Chunlei Zhan, K. W. Chan, Wei Liu, L. Tan, K. Teo, K. J. Chen, Y. Yeo","doi":"10.1109/VLSI-TSA.2012.6210119","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210119","url":null,"abstract":"AlGaN/GaN MOS-HEMTs on a silicon platform were realized using a CMOS-compatible gold-free process. Process modules commonly used in CMOS were used, including gate stack formation, etching modules, etc. R<sub>on</sub> of 3 mΩ.cm<sup>2</sup> was obtained. Breakdown voltage V<sub>BR</sub> of 800 V was achieved, the highest for L<sub>GD</sub> below 10 μm for AlGaN/GaN/Si MOS-HEMTs fabricated using a gold-free process. The devices could be generally useful for cost-competitive power switching circuits with supply voltage in the range of several hundred volts.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128830586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210156
T. Ngai, C. Hobbs, D. Veksler, K. Matthews, I. Ok, K. Akarvardar, K. Ang, J. Huang, M. Rodgers, S. Vivekanand, H. Li, C. Young, P. Majhi, S. Gausepohl, P. Kirsch, R. Jammy
In this paper, we report a Vt tuning technique by dipole-engineering dopant incorporation in the FinFET metal gate stack. Remote interfacial layer scavenging induced by the metal gate dopants has an added advantage of improving the CET, without impacting short channel behavior. Using Al as the dipole-inducing dopant in a FinFET gate stack, a 170mV of positive Vt shift with 0.8Å CETinv reduction was demonstrated. Dopant profiles can be tailored to simply render a CET reduction alone without any Vt tuning, if needed. These results demonstrate key progress towards realizing multi Vt FinFET device architectures for 20nm node and beyond.
{"title":"Simple FinFET gate doping technique for dipole-engineered Vt tuning and CET scaling","authors":"T. Ngai, C. Hobbs, D. Veksler, K. Matthews, I. Ok, K. Akarvardar, K. Ang, J. Huang, M. Rodgers, S. Vivekanand, H. Li, C. Young, P. Majhi, S. Gausepohl, P. Kirsch, R. Jammy","doi":"10.1109/VLSI-TSA.2012.6210156","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210156","url":null,"abstract":"In this paper, we report a Vt tuning technique by dipole-engineering dopant incorporation in the FinFET metal gate stack. Remote interfacial layer scavenging induced by the metal gate dopants has an added advantage of improving the CET, without impacting short channel behavior. Using Al as the dipole-inducing dopant in a FinFET gate stack, a 170mV of positive Vt shift with 0.8Å CETinv reduction was demonstrated. Dopant profiles can be tailored to simply render a CET reduction alone without any Vt tuning, if needed. These results demonstrate key progress towards realizing multi Vt FinFET device architectures for 20nm node and beyond.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128438148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210103
Shih-Chieh Wu, Chieh-Ting Lo, T. Hou
Various bias schemes in the RS-TFT have been comprehensively investigated. As shown in Table I, the VD-biased bipolar RS is superior for the logic/RS hybrid operation with the ability of two-bit-per-cell storage because of its large program margin, localized filament location, negligible VTH shift, and suppressed gate leakage current. In comparison with other embedded memory technologies, the proposed RS-TFT in this work not only is compatible with logic CMOS technology, but also provides comparable memory performance with a very competitive cell size.
{"title":"Logic/resistive-switching hybrid transistor for two-bit-per-cell storage","authors":"Shih-Chieh Wu, Chieh-Ting Lo, T. Hou","doi":"10.1109/VLSI-TSA.2012.6210103","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210103","url":null,"abstract":"Various bias schemes in the RS-TFT have been comprehensively investigated. As shown in Table I, the VD-biased bipolar RS is superior for the logic/RS hybrid operation with the ability of two-bit-per-cell storage because of its large program margin, localized filament location, negligible VTH shift, and suppressed gate leakage current. In comparison with other embedded memory technologies, the proposed RS-TFT in this work not only is compatible with logic CMOS technology, but also provides comparable memory performance with a very competitive cell size.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133332525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210147
W. Shen, Chia-En Huang, H. OuYang, Y. King, C. Lin
A 32nm MTP cell with a nitride-based storage node using 32nm strained Si process are demonstrated with an ultra small cell size of 0.0528μm2 by a 32nm strained-CMOS fully logic compatible process. A self-aligned tiny nitride storage node is placed in the narrow spacing of two 32nm transistors by a merged transistor spacer mingled with a strained nitride of 32nm strained Si process. The twin-gate cell uses the source side injection (SSI) to obtain 100 times of on/off window by a low program voltage of 3.5V within 1msec. A good reliability in retention and disturb is exhibited due to the inherently decoupling of storage node and transistor gate oxide in this cell, even when gate oxide is thinner than 16Å with 32nm gate length only.
{"title":"32nm strained nitride MTP cell by fully CMOS logic compatible process","authors":"W. Shen, Chia-En Huang, H. OuYang, Y. King, C. Lin","doi":"10.1109/VLSI-TSA.2012.6210147","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210147","url":null,"abstract":"A 32nm MTP cell with a nitride-based storage node using 32nm strained Si process are demonstrated with an ultra small cell size of 0.0528μm2 by a 32nm strained-CMOS fully logic compatible process. A self-aligned tiny nitride storage node is placed in the narrow spacing of two 32nm transistors by a merged transistor spacer mingled with a strained nitride of 32nm strained Si process. The twin-gate cell uses the source side injection (SSI) to obtain 100 times of on/off window by a low program voltage of 3.5V within 1msec. A good reliability in retention and disturb is exhibited due to the inherently decoupling of storage node and transistor gate oxide in this cell, even when gate oxide is thinner than 16Å with 32nm gate length only.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127649599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-DAT.2012.6212612
G. Loh
Three-dimensional die-stacking technologies are rapidly maturing, with intense research and development happening in the areas of manufacturing, EDA/CAD, test, and yield improvement. When die-stacking technology has reached the point of economic viability for high-volume manufacturing, chip and system designers must have complete architectures ready to take advantage of this exciting new technology. Computer architecture researchers are showing great interest in 3D technology. This paper summarizes some of the major directions that academic researchers are currently exploring, highlights some of these efforts, and discusses future opportunities in these and other areas of computer and system architectures. In particular, this paper covers 3D opportunities for compute (including processor- and application-specific accelerators), memory, and the integration of other technologies from a computer architecture perspective. This paper also explores how collaboration between computer architecture and other fields may provide further value for the entire die-stacking ecosystem.
{"title":"Computer architecture for die stacking","authors":"G. Loh","doi":"10.1109/VLSI-DAT.2012.6212612","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2012.6212612","url":null,"abstract":"Three-dimensional die-stacking technologies are rapidly maturing, with intense research and development happening in the areas of manufacturing, EDA/CAD, test, and yield improvement. When die-stacking technology has reached the point of economic viability for high-volume manufacturing, chip and system designers must have complete architectures ready to take advantage of this exciting new technology. Computer architecture researchers are showing great interest in 3D technology. This paper summarizes some of the major directions that academic researchers are currently exploring, highlights some of these efforts, and discusses future opportunities in these and other areas of computer and system architectures. In particular, this paper covers 3D opportunities for compute (including processor- and application-specific accelerators), memory, and the integration of other technologies from a computer architecture perspective. This paper also explores how collaboration between computer architecture and other fields may provide further value for the entire die-stacking ecosystem.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117069448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210132
Yu-Sheng Wu, Chun-Hsien Chiang, P. Su
Using a physical and predictive 2-D confinement model considering the impact of source/drain coupling on the potential well, this work investigates the scalability of Ge and InGaAs multi-gate NMOSFETs by exploring a wide design space with various aspect ratio (AR). Our study indicates that, for a given subthreshold swing, multi-gate devices with InGaAs channel are more scalable than the Ge counterpart because of the larger fin-width allowed. Since the quantum-confinement effect can improve the Vth roll-off, Tri-gate (AR=1) with significant 2-D confinement effect exhibits better Vth roll-off than FinFET (AR>;1). In addition, the InGaAs devices exhibit better Vth roll-off than the Ge devices.
{"title":"Investigation of scalability for Ge and InGaAs channel multi-gate NMOSFETs","authors":"Yu-Sheng Wu, Chun-Hsien Chiang, P. Su","doi":"10.1109/VLSI-TSA.2012.6210132","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210132","url":null,"abstract":"Using a physical and predictive 2-D confinement model considering the impact of source/drain coupling on the potential well, this work investigates the scalability of Ge and InGaAs multi-gate NMOSFETs by exploring a wide design space with various aspect ratio (AR). Our study indicates that, for a given subthreshold swing, multi-gate devices with InGaAs channel are more scalable than the Ge counterpart because of the larger fin-width allowed. Since the quantum-confinement effect can improve the Vth roll-off, Tri-gate (AR=1) with significant 2-D confinement effect exhibits better Vth roll-off than FinFET (AR>;1). In addition, the InGaAs devices exhibit better Vth roll-off than the Ge devices.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125319599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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