Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551863
Sheng Liu, Yang Liu, R. Montazami, V. Jain, J. Heflin, Qiming Zhang
In ionomeric polymers, the accumulation or depletion of excess charges (ions) at the electrodes under an applied voltage will generate strain in these regions. This can be made use of for electromechanical transduction devices such as actuators and sensors[1]. Figure 1 illustrates schematically an ionomeric polymer bending actuator in which the accumulation and depletion of cations at the cathode and anode, respectively, create bending of the ionomeric polymer sheet under an applied voltage. In order to increase the charge density and population at the electrodes so that a large strain and high force output can be realized, various ionomeric polymer/conductive network composites (CNC) electrodes (analogous to the porous electrodes in the supercapacitors) have been developed to form ionomeric polymer/CNC actuators (IPCNC) in the past 15 years[2–3]. A schematic of a typical bending actuator thus developed is shown in Figure 2, which in general has a three layer structure, i.e., two porous electrode layers in the form of the conductive network/ionomer composite separated by a neat ionomer layer. IPCNC actuators are attractive because it can be operated under a few volts. On the other hand, IPCNC actuators suffer a low actuation speed which is often in tens of seconds range, low efficiency (<3 %), and low elastic energy density, all of which should be improved in order to meet the demands of a broad range of polymer electromechanical applications.
{"title":"Fast response of actuators with self assembly nanoparticle electrodes and ionic liquids","authors":"Sheng Liu, Yang Liu, R. Montazami, V. Jain, J. Heflin, Qiming Zhang","doi":"10.1109/DRC.2010.5551863","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551863","url":null,"abstract":"In ionomeric polymers, the accumulation or depletion of excess charges (ions) at the electrodes under an applied voltage will generate strain in these regions. This can be made use of for electromechanical transduction devices such as actuators and sensors[1]. Figure 1 illustrates schematically an ionomeric polymer bending actuator in which the accumulation and depletion of cations at the cathode and anode, respectively, create bending of the ionomeric polymer sheet under an applied voltage. In order to increase the charge density and population at the electrodes so that a large strain and high force output can be realized, various ionomeric polymer/conductive network composites (CNC) electrodes (analogous to the porous electrodes in the supercapacitors) have been developed to form ionomeric polymer/CNC actuators (IPCNC) in the past 15 years[2–3]. A schematic of a typical bending actuator thus developed is shown in Figure 2, which in general has a three layer structure, i.e., two porous electrode layers in the form of the conductive network/ionomer composite separated by a neat ionomer layer. IPCNC actuators are attractive because it can be operated under a few volts. On the other hand, IPCNC actuators suffer a low actuation speed which is often in tens of seconds range, low efficiency (<3 %), and low elastic energy density, all of which should be improved in order to meet the demands of a broad range of polymer electromechanical applications.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124671747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551865
Lin Yu, Sunkook Kim, S. Mohammadi
DC and intrinsic low frequency noise properties of p-channel depletion-mode single-walled carbon nanotube field effect transistors (SWCNT-FETs) are investigated. To characterize the intrinsic noise properties a thin atomic layer deposited (ALD) HfO2 gate dielectric which also works as a passivation layer is used to isolate SWCNT-FETs from environmental factors. The SWCNT-FET devices (a prototypical device with 1 CNT is shown in Fig. 1) are fabricated on Si substrate with a 300nm SiO2 thermal oxide. Iron catalyst patterns are defined by UV photolithography with a 10µm spacing and subsequent iron deposition and lift-off. Single-walled carbon nanotubes (SWCNTs) are then synthesized by chemical vapor deposition (CVD) of methane on the substrate coated with patterned Iron catalyst. Source and drain contacts separated by 3µm are formed by electron beam deposition of Pd metal. A 20nm high-k HfO2 film is deposited using ASM Micro-chemistry F-120 ALCVD™ Reactor at 300°C by using precursor of HfCl4 and H2O. Top Gate metal is defined by UV photolithography followed by the deposition of Cr/Au (10/50nm) with a minimum gate length of 1.5 µm. Cr/Au (20/450nm) metal interconnects are finally deposited on top of the source and drain Pd contacts. Fig. 2 shows transfer characteristics (Id-Vsg) of a SWCNT-FET with 1.5µm gate-length and 3µm source-drain separation measured in the ambient environment when Vsg is swept from −1.5V to 1V and back to −1.5V. Virtually no hysteresis is observed in the IV characteristics of this device. Figure 3 shows Id-Vsd characteristics of the same device with a maximum on current of 14µA and a maximum transconductance of 6µS at a drain bias of Vsd = 1.5V and gate bias of Vsg = −0.75V. A drain resistance (R) of 120kΩ due to schottky barrier at the drain contact was extracted from IV curves. Drain current in the linear region was modeled according to Id = μeffCg(Vsg+Vt)Vsd/ (L+RμeffCg(Vsg+Vt where Cg = 2πε0ε / cosh−1(1+h/ r) ∼ 28af / nm presuming a cylindrical tube model is the gate capacitance per unit length per number of CNTs in the device structure, L is the gate length, εr = 15 is the effective dielectric constant of HfO2, r = 0.5∼2nm is the radius of CNT, h = 20nm is the gate oxide thickness and μeff is the effective field-effect mobility of holes in SWCNT channel. In the current saturation regime where Vsd ≥ Vsg+Vt+RId, SWCNT-FET has a semi-ballistic transport with a drain current modeled as Id = K(Vsg+Vt)3/2(1+λVsd, with effective transconductance K = 1.7×10−6 [A/V1.5] and channel length modulation
{"title":"DC and flicker noise models for passivated single-walled carbon nanotube transistors","authors":"Lin Yu, Sunkook Kim, S. Mohammadi","doi":"10.1109/DRC.2010.5551865","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551865","url":null,"abstract":"DC and intrinsic low frequency noise properties of p-channel depletion-mode single-walled carbon nanotube field effect transistors (SWCNT-FETs) are investigated. To characterize the intrinsic noise properties a thin atomic layer deposited (ALD) HfO<inf>2</inf> gate dielectric which also works as a passivation layer is used to isolate SWCNT-FETs from environmental factors. The SWCNT-FET devices (a prototypical device with 1 CNT is shown in Fig. 1) are fabricated on Si substrate with a 300nm SiO<inf>2</inf> thermal oxide. Iron catalyst patterns are defined by UV photolithography with a 10µm spacing and subsequent iron deposition and lift-off. Single-walled carbon nanotubes (SWCNTs) are then synthesized by chemical vapor deposition (CVD) of methane on the substrate coated with patterned Iron catalyst. Source and drain contacts separated by 3µm are formed by electron beam deposition of Pd metal. A 20nm high-k HfO<inf>2</inf> film is deposited using ASM Micro-chemistry F-120 ALCVD<sup>™</sup> Reactor at 300°C by using precursor of HfCl<inf>4</inf> and H<inf>2</inf>O. Top Gate metal is defined by UV photolithography followed by the deposition of Cr/Au (10/50nm) with a minimum gate length of 1.5 µm. Cr/Au (20/450nm) metal interconnects are finally deposited on top of the source and drain Pd contacts. Fig. 2 shows transfer characteristics (I<inf>d</inf>-V<inf>sg</inf>) of a SWCNT-FET with 1.5µm gate-length and 3µm source-drain separation measured in the ambient environment when V<inf>sg</inf> is swept from −1.5V to 1V and back to −1.5V. Virtually no hysteresis is observed in the IV characteristics of this device. Figure 3 shows I<inf>d</inf>-V<inf>sd</inf> characteristics of the same device with a maximum on current of 14µA and a maximum transconductance of 6µS at a drain bias of V<inf>sd</inf> = 1.5V and gate bias of V<inf>sg</inf> = −0.75V. A drain resistance (R) of 120kΩ due to schottky barrier at the drain contact was extracted from IV curves. Drain current in the linear region was modeled according to I<inf>d</inf> = μ<inf>eff</inf>C<inf>g</inf>(V<inf>sg</inf>+V<inf>t</inf>)V<inf>sd</inf>/ (L+Rμ<inf>eff</inf>C<inf>g</inf>(V<inf>sg</inf>+V<inf>t</inf> where C<inf>g</inf> = 2πε<inf>0</inf>ε / cosh<sup>−1</sup>(1+h/ r) ∼ 28af / nm presuming a cylindrical tube model is the gate capacitance per unit length per number of CNTs in the device structure, L is the gate length, ε<inf>r</inf> = 15 is the effective dielectric constant of HfO<inf>2</inf>, r = 0.5∼2nm is the radius of CNT, h = 20nm is the gate oxide thickness and μ<inf>eff</inf> is the effective field-effect mobility of holes in SWCNT channel. In the current saturation regime where V<inf>sd</inf> ≥ V<inf>sg</inf>+V<inf>t</inf>+RI<inf>d</inf>, SWCNT-FET has a semi-ballistic transport with a drain current modeled as I<inf>d</inf> = K(V<inf>sg</inf>+V<inf>t</inf>)<sup>3/2</sup>(1+λV<inf>sd</inf>, with effective transconductance K = 1.7×10<sup>−6</sup> [A/V<sup>1.5</sup>] and channel length modulation ","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128859582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551891
M. Egard, M. Arlelid, E. Lind, L. Wernersson
We report on a gated tunnel diode (GTD) and its operation in a 60 GHz pulsed oscillator, also known as a wavelet generator. The wavelet generator operates with the aid of a reactive bias stabilizing network, which minimizes the DC power consumption. This allows for 60 GHz wavelets as short as 56 ps to be produced, with a corresponding energy consumption of 1.0 pJ, which is a factor of 3.6 lower as compared to earlier results [1]. The operation of the GTD is described by a small signal equivalent model deduced from S-parameter measurements.
{"title":"Gated tunnel diode with a reactive bias stabilizing network for 60 GHz impulse radio implementations","authors":"M. Egard, M. Arlelid, E. Lind, L. Wernersson","doi":"10.1109/DRC.2010.5551891","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551891","url":null,"abstract":"We report on a gated tunnel diode (GTD) and its operation in a 60 GHz pulsed oscillator, also known as a wavelet generator. The wavelet generator operates with the aid of a reactive bias stabilizing network, which minimizes the DC power consumption. This allows for 60 GHz wavelets as short as 56 ps to be produced, with a corresponding energy consumption of 1.0 pJ, which is a factor of 3.6 lower as compared to earlier results [1]. The operation of the GTD is described by a small signal equivalent model deduced from S-parameter measurements.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125548528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551900
H. Miyamoto, H. Shimawaki
A GaN based field effect transistor (FET) on a silicon substrate is a promising candidate for next generation switching and RF power devices due to its high breakdown electric fields, high drift velocity and low substrate cost. A normally-off operation with a low on-resistance is important to utilize the GaN FETs as switching devices used for power supplies for computer systems and power modules for hybrid vehicles. A recessed gate structure has been reported to realize the normally-off GaN FETs with low on-resistance [1–3]. However, there still exists an issue of the insufficient uniformity in threshold voltage (Vth) due to lack of an available etch stop layer under the gate. RF power GaN FETs on Si substrates have been mainly developed for power amplifiers used for Cellular and WiMax base stations at an operating frequency of 2–5 GHz [4]. The maximum operating frequency of the reported GaN FETs on a Si substrate was up to 10 GHz [5, 6]. There is no report of a GaN FET on a Si substrate for millimeter- wave range applications such as automotive radar systems. In this paper, we describe a GaN switching device with high Vth uniformity and low on-resistance using novel piezo neutralization (PNT) technique and a 76 GHz GaN power amplifier(PA) on a Si substrate using 0.15-µm-gate GaN FETs and low-loss Coplanar Waveguide (CPW) lines.
{"title":"Recent progress in GaN FETs on silicon substrate for switching and RF power applications","authors":"H. Miyamoto, H. Shimawaki","doi":"10.1109/DRC.2010.5551900","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551900","url":null,"abstract":"A GaN based field effect transistor (FET) on a silicon substrate is a promising candidate for next generation switching and RF power devices due to its high breakdown electric fields, high drift velocity and low substrate cost. A normally-off operation with a low on-resistance is important to utilize the GaN FETs as switching devices used for power supplies for computer systems and power modules for hybrid vehicles. A recessed gate structure has been reported to realize the normally-off GaN FETs with low on-resistance [1–3]. However, there still exists an issue of the insufficient uniformity in threshold voltage (Vth) due to lack of an available etch stop layer under the gate. RF power GaN FETs on Si substrates have been mainly developed for power amplifiers used for Cellular and WiMax base stations at an operating frequency of 2–5 GHz [4]. The maximum operating frequency of the reported GaN FETs on a Si substrate was up to 10 GHz [5, 6]. There is no report of a GaN FET on a Si substrate for millimeter- wave range applications such as automotive radar systems. In this paper, we describe a GaN switching device with high Vth uniformity and low on-resistance using novel piezo neutralization (PNT) technique and a 76 GHz GaN power amplifier(PA) on a Si substrate using 0.15-µm-gate GaN FETs and low-loss Coplanar Waveguide (CPW) lines.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"176 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114080814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551867
V. Kaushal, I. Íñiguez-de-la-Torre, M. Margala
Ballistic transport appears when the size of electronic devices is reduced below the electron mean free path. By using latest fabrication techniques and proper material system, the ballistic behavior can be achieved in nano-scale devices even at room temperature (RT). In [1], Song has presented a ballistic rectifier which demonstrates the nonlinear transport at RT. However, the functionality of this device was constraint to rectification only. Using this well established theory, and to extend the functionality beyond rectification, our group proposed a novel device in which we added two in-plane strategically placed gates as shown in SEM image in Fig. 1. This led to formation of ballistic deflector transistor (BDT) [2]. In BDT, without biasing the lateral gates, we replicated the rectifying behavior shown in Fig. 2, certifying the presence of non-linear effect at RT.
{"title":"Room temperature nonlinear ballistic nanodevices for logic applications","authors":"V. Kaushal, I. Íñiguez-de-la-Torre, M. Margala","doi":"10.1109/DRC.2010.5551867","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551867","url":null,"abstract":"Ballistic transport appears when the size of electronic devices is reduced below the electron mean free path. By using latest fabrication techniques and proper material system, the ballistic behavior can be achieved in nano-scale devices even at room temperature (RT). In [1], Song has presented a ballistic rectifier which demonstrates the nonlinear transport at RT. However, the functionality of this device was constraint to rectification only. Using this well established theory, and to extend the functionality beyond rectification, our group proposed a novel device in which we added two in-plane strategically placed gates as shown in SEM image in Fig. 1. This led to formation of ballistic deflector transistor (BDT) [2]. In BDT, without biasing the lateral gates, we replicated the rectifying behavior shown in Fig. 2, certifying the presence of non-linear effect at RT.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"1 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114122359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551946
A. Raychowdhury, D. Somasekhar, T. Karnik, V. De
The paper presents a RD disturb model study of STT-MTJ memory bits. It shows that high-current short-pulsed RD may cause failure under hammer conditions. Analytical models for such have been developed and validated against numerical simulations.
{"title":"Modeling and analysis of read (RD) disturb in 1T-1STT MTJ memory bits","authors":"A. Raychowdhury, D. Somasekhar, T. Karnik, V. De","doi":"10.1109/DRC.2010.5551946","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551946","url":null,"abstract":"The paper presents a RD disturb model study of STT-MTJ memory bits. It shows that high-current short-pulsed RD may cause failure under hammer conditions. Analytical models for such have been developed and validated against numerical simulations.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120981182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551866
Haojun Luo, P. Wellenius, L. Lunardi, J. Muth
InGaZnO is an amorphous oxide semiconductor with electron mobility an order of magnitude higher than that of amorphous silicon or organic semiconductors. The ability to control carrier concentration, the wide band gap and deposition at room temperature make it an excellent candidate for transparent electronic systems on glass or plastics. Thus far, most reports have focused on the performance of the performance of single discrete devices [1],[2] or simple ring oscillator circuits operating at 2 MHz [3]. While a OR gate has recently been published [4] operating at10 Hz, in general the basic building blocks for transparent digital logic has not been investigated. In this paper we present, transparent logic showing good performance from inverters, NAND and NOR gates, all deposited at room temperature. The significance of these results is that construction of these basic digital logic building blocks with high gain and fast response demonstrate the viability for amorphous oxide digital logic to be utilized in transparent, and flexible electronic systems.
{"title":"Amorphous InGaZnO logic gates for transparent electronics","authors":"Haojun Luo, P. Wellenius, L. Lunardi, J. Muth","doi":"10.1109/DRC.2010.5551866","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551866","url":null,"abstract":"InGaZnO is an amorphous oxide semiconductor with electron mobility an order of magnitude higher than that of amorphous silicon or organic semiconductors. The ability to control carrier concentration, the wide band gap and deposition at room temperature make it an excellent candidate for transparent electronic systems on glass or plastics. Thus far, most reports have focused on the performance of the performance of single discrete devices [1],[2] or simple ring oscillator circuits operating at 2 MHz [3]. While a OR gate has recently been published [4] operating at10 Hz, in general the basic building blocks for transparent digital logic has not been investigated. In this paper we present, transparent logic showing good performance from inverters, NAND and NOR gates, all deposited at room temperature. The significance of these results is that construction of these basic digital logic building blocks with high gain and fast response demonstrate the viability for amorphous oxide digital logic to be utilized in transparent, and flexible electronic systems.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121579111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551874
S. L. Selvaraj, Kazuhiro Nagai, T. Egawa
Enhancement mode AlGaN/GaN HEMT devices with a positive threshold voltage and higher gate voltage operation still remains a major issue and challenges the integration of simplified circuit design. The demonstration of normally-OFF operation is difficult because of large amount of polarization charges in AlGaN/GaN hetero-structures. However today it is imperative to demonstrate normally-OFF type transistors in order to simplify the driving circuits for power applications. The already reported devices for enhancement mode have smaller gate bias (VG) swing and quasi-normally-OFF operation. Further, most of the reports on enhancement mode AlGaN/GaN HEMTs were demonstrated on expensive SiC or sapphire substrates. To this day, only one report [1] is available demonstrating the normally-OFF type AlGaN/GaN HEMTs on Si substrate with a maximum possible gate bias of 1 V, threshold voltage (Vth) at 0 V and drain current maximum (IDmax) of 30 mA/mm. The normally-OFF AlGaN/GaN HEMTs grown on Si needs to be improved to give a large VG swing and high IDmax. Therefore here in this report, we are reporting a p-InGaN cap layered AlGaN/GaN normally-OFF type HEMTs on silicon substrate with VG applicable as high as +3.5V without gate leakage. Further we achieved a high breakdown for relatively a small gate-drain length (Lgd) of 3 µm. Demonstrating a normally-OFF type AlGaN/GaN HEMTs on low cost Si substrate, coupled with high breakdown is an important step forward to integrate enhancement and depletion mode devices on Si.
{"title":"MOCVD grown normally-OFF type AlGaN/GaN HEMTs on 4 inch Si using p-InGaN cap layer with high breakdown","authors":"S. L. Selvaraj, Kazuhiro Nagai, T. Egawa","doi":"10.1109/DRC.2010.5551874","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551874","url":null,"abstract":"Enhancement mode AlGaN/GaN HEMT devices with a positive threshold voltage and higher gate voltage operation still remains a major issue and challenges the integration of simplified circuit design. The demonstration of normally-OFF operation is difficult because of large amount of polarization charges in AlGaN/GaN hetero-structures. However today it is imperative to demonstrate normally-OFF type transistors in order to simplify the driving circuits for power applications. The already reported devices for enhancement mode have smaller gate bias (VG) swing and quasi-normally-OFF operation. Further, most of the reports on enhancement mode AlGaN/GaN HEMTs were demonstrated on expensive SiC or sapphire substrates. To this day, only one report [1] is available demonstrating the normally-OFF type AlGaN/GaN HEMTs on Si substrate with a maximum possible gate bias of 1 V, threshold voltage (Vth) at 0 V and drain current maximum (IDmax) of 30 mA/mm. The normally-OFF AlGaN/GaN HEMTs grown on Si needs to be improved to give a large VG swing and high IDmax. Therefore here in this report, we are reporting a p-InGaN cap layered AlGaN/GaN normally-OFF type HEMTs on silicon substrate with VG applicable as high as +3.5V without gate leakage. Further we achieved a high breakdown for relatively a small gate-drain length (Lgd) of 3 µm. Demonstrating a normally-OFF type AlGaN/GaN HEMTs on low cost Si substrate, coupled with high breakdown is an important step forward to integrate enhancement and depletion mode devices on Si.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122506410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551944
Y. Chang, C. Merckling, J. Penaud, C. Y. Lu, G. Brammertz, W. Wang, M. Hong, J. Kwo, J. Dekoster, M. Caymax, M. Meuris, M. Heyns
The quest for technologies beyond the 15 nm node complementary metal-oxide-semiconductor (CMOS) devices has now called for research on alternative channel materials such as Ge and III–V compound semiconductors with inherently higher carrier mobility than those of Si. Intensive effort has been made on GaAs nMOS devices owing to GaAs's superior electron mobility and its lattice parameter close to that of Ge. Dielectric/GaAs (100) interfaces, in general, have very high interfacial trap density (Dit) at the mid-gap energy,1−3 resulting in serious Fermi-level pinning issues, and thus preventing the proper inversion response required for the inversion-channel GaAs MOS devices. To solve this problem, a number of approaches for passivating GaAs have been reported in the past decades,4−10 with one report showing good drain current in an inversion-channel GaAs MOSFET.10 Evaluation of Dit was usually obtained using capacitance-voltage (C-V) and conductance-voltage (G-V) characteristics measured at room temperatures. However, due to the larger energy band-gap of GaAs as compared to that of Si, interfacial traps near the mid-gap of the dielectric/GaAs interfaces may be too slow to respond to the usual C-V and G-V characterization frequencies at room temperatures and only a small region of the whole GaAs band-gap away from the mid-gap can be measured.2,3,11 In this work, this inadequacy is remedied by performing additional C-V and G-V measurements at a high temperature of 150°C to probe Dit spectrums near the critical mid-gap region. Furthermore, the influence on the Dit around the mid-gap region of the dielectric/GaAs interfaces by the GaAs surface reconstructions and systematic annealing conditions has been studied.
{"title":"Great reduction of interfacial traps in Al2O3/GaAs (100) starting with Ga-rich surface and through systematic thermal annealing","authors":"Y. Chang, C. Merckling, J. Penaud, C. Y. Lu, G. Brammertz, W. Wang, M. Hong, J. Kwo, J. Dekoster, M. Caymax, M. Meuris, M. Heyns","doi":"10.1109/DRC.2010.5551944","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551944","url":null,"abstract":"The quest for technologies beyond the 15 nm node complementary metal-oxide-semiconductor (CMOS) devices has now called for research on alternative channel materials such as Ge and III–V compound semiconductors with inherently higher carrier mobility than those of Si. Intensive effort has been made on GaAs nMOS devices owing to GaAs's superior electron mobility and its lattice parameter close to that of Ge. Dielectric/GaAs (100) interfaces, in general, have very high interfacial trap density (Dit) at the mid-gap energy,1−3 resulting in serious Fermi-level pinning issues, and thus preventing the proper inversion response required for the inversion-channel GaAs MOS devices. To solve this problem, a number of approaches for passivating GaAs have been reported in the past decades,4−10 with one report showing good drain current in an inversion-channel GaAs MOSFET.10 Evaluation of Dit was usually obtained using capacitance-voltage (C-V) and conductance-voltage (G-V) characteristics measured at room temperatures. However, due to the larger energy band-gap of GaAs as compared to that of Si, interfacial traps near the mid-gap of the dielectric/GaAs interfaces may be too slow to respond to the usual C-V and G-V characterization frequencies at room temperatures and only a small region of the whole GaAs band-gap away from the mid-gap can be measured.2,3,11 In this work, this inadequacy is remedied by performing additional C-V and G-V measurements at a high temperature of 150°C to probe Dit spectrums near the critical mid-gap region. Furthermore, the influence on the Dit around the mid-gap region of the dielectric/GaAs interfaces by the GaAs surface reconstructions and systematic annealing conditions has been studied.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133436954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551980
Hau-Yuan Huang, Yen-Chieh Huang, Je-Yi Su, N. Su, C. Chiang, Chien-Hung Wu, Shui-Jinn Wang
Thin-film transistors were fabricated using amorphous indium gallium zinc oxide (α-IGZO) as channels and high-к material HfSiO as gate dielectric by RF sputtering. The influence of high-к PDA temperature variation on device characteristics was investigated. The bottom-gate low voltage driven (≤ 2 V) TFTs operated in n-type enhancement mode with a field-effect mobility of 12.7cm2/V-s, on-off current ratio of 3×105, threshold voltage of 0.005V, and subthreshold voltage swing of 0.11V/dec.
{"title":"High performance and low driving voltage amorphous InGaZnO thin-film transistors using high-к HfSiO dielectrics","authors":"Hau-Yuan Huang, Yen-Chieh Huang, Je-Yi Su, N. Su, C. Chiang, Chien-Hung Wu, Shui-Jinn Wang","doi":"10.1109/DRC.2010.5551980","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551980","url":null,"abstract":"Thin-film transistors were fabricated using amorphous indium gallium zinc oxide (α-IGZO) as channels and high-к material HfSiO as gate dielectric by RF sputtering. The influence of high-к PDA temperature variation on device characteristics was investigated. The bottom-gate low voltage driven (≤ 2 V) TFTs operated in n-type enhancement mode with a field-effect mobility of 12.7cm<sup>2</sup>/V-s, on-off current ratio of 3×10<sup>5</sup>, threshold voltage of 0.005V, and subthreshold voltage swing of 0.11V/dec.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131852391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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