Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387146
J. Shin, K. Aygun
Multi-gigabit input/output (I/O) links on printed circuit boards (PCBs) suffer from high-frequency signal attenuation, necessitating equalization to restore the transmitted waveforms. Whereas active transmitter or receiver equalization circuits consume significant power, equalizers composed exclusively of passive devices can achieve good signal integrity with no active power dissipation. Recent advances in packaging technology allow passive devices to be integrated directly into the substrate, thereby freeing area in the die or on the motherboard that would otherwise have been needed for the equalizer. In this paper, we are reporting the first, experimental demonstration of continuous-time linear equalizers (CTLEs) using embedded passive components up to 10 gigabit per second (Gbps). We have designed, optimized and fabricated three different equalizers using embedded passives technology. These devices were employed to a equalize board-level interconnect suffering from frequency-dependent loss. We have then validated the performance of the CTLEs in the frequency and time domains.
{"title":"On-Package Continuous-Time Linear Equalizer using Embedded Passive Components","authors":"J. Shin, K. Aygun","doi":"10.1109/EPEP.2007.4387146","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387146","url":null,"abstract":"Multi-gigabit input/output (I/O) links on printed circuit boards (PCBs) suffer from high-frequency signal attenuation, necessitating equalization to restore the transmitted waveforms. Whereas active transmitter or receiver equalization circuits consume significant power, equalizers composed exclusively of passive devices can achieve good signal integrity with no active power dissipation. Recent advances in packaging technology allow passive devices to be integrated directly into the substrate, thereby freeing area in the die or on the motherboard that would otherwise have been needed for the equalizer. In this paper, we are reporting the first, experimental demonstration of continuous-time linear equalizers (CTLEs) using embedded passive components up to 10 gigabit per second (Gbps). We have designed, optimized and fabricated three different equalizers using embedded passives technology. These devices were employed to a equalize board-level interconnect suffering from frequency-dependent loss. We have then validated the performance of the CTLEs in the frequency and time domains.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125116771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387202
Lijun Jiang, B. Rubin, Yuan-Fu Liu, J. Morsey, A. Deustch
The paper contains a novel mechanism for full wave electromagnetic simulation of complicated inhomogeneous structures, such as on-chip interconnects, IC packaging, antennas, and scattering objects. It uses only equivalent principle based EFIE instead of both EFIE and MFIE to establish the surface integral equations for practical inhomogeneous structure so that a much more simplified formulation process is needed in the EM simulation procedure. To overcome the numerical error of K operator in the formulation, a new analytical solution to the K operator for general full-wave integral equations is provided. Numerical results are demonstrated to verify the proposed algorithm.
{"title":"Electromagnetic Simulation for Inhomogeneous Interconnect and Packaging Structures","authors":"Lijun Jiang, B. Rubin, Yuan-Fu Liu, J. Morsey, A. Deustch","doi":"10.1109/EPEP.2007.4387202","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387202","url":null,"abstract":"The paper contains a novel mechanism for full wave electromagnetic simulation of complicated inhomogeneous structures, such as on-chip interconnects, IC packaging, antennas, and scattering objects. It uses only equivalent principle based EFIE instead of both EFIE and MFIE to establish the surface integral equations for practical inhomogeneous structure so that a much more simplified formulation process is needed in the EM simulation procedure. To overcome the numerical error of K operator in the formulation, a new analytical solution to the K operator for general full-wave integral equations is provided. Numerical results are demonstrated to verify the proposed algorithm.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134546964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387152
T. Thorolfsson, P. Franzon
3D stacking and integration can provide tremendous advantages to electronic systems. This paper explores the system-level considerations such as layout, routing and IO in the design of 3D multi-FPGA packaging, along with their architectural implications.
{"title":"System Design for 3D Multi-FPGA Packaging","authors":"T. Thorolfsson, P. Franzon","doi":"10.1109/EPEP.2007.4387152","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387152","url":null,"abstract":"3D stacking and integration can provide tremendous advantages to electronic systems. This paper explores the system-level considerations such as layout, routing and IO in the design of 3D multi-FPGA packaging, along with their architectural implications.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133299759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387187
Mengmeng Ding, D. Smart
This paper presents an efficient model order determination and accurate model generation algorithm from measured or simulated s-parameters. Based on the vector fitting algorithm for rational approximation, the proposed algorithm efficiently determines the model order and provides good initial poles to the vector fitting algorithm, resulting in faster generation of more accurate rational approximations. Consequently, the passivity of the rational approximations are improved.
{"title":"Efficient, Automatic Model Order Determination and Model Generation for Tabulated S-parameters","authors":"Mengmeng Ding, D. Smart","doi":"10.1109/EPEP.2007.4387187","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387187","url":null,"abstract":"This paper presents an efficient model order determination and accurate model generation algorithm from measured or simulated s-parameters. Based on the vector fitting algorithm for rational approximation, the proposed algorithm efficiently determines the model order and provides good initial poles to the vector fitting algorithm, resulting in faster generation of more accurate rational approximations. Consequently, the passivity of the rational approximations are improved.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"35 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114118582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387191
H. Since, B.Y.A. Jalaluddin, O.A.Y. Yeong
Traditionally, power integrity engineer uses simulated transient current profile, icc(t) from the Circuit Designer as input to power delivery network, PDN to simulate worst case transient power noise. However, it is extremely difficult to simulate the maximum current profile from large circuit or logic block. It increases the difficulties when the circuit/ logic run at random application. The paper discusses the reverse engineering method to regenerate high speed stimulus current from the given PDN and measured voltage waveform. The paper firstly verified that the reverse engineering method proven to be accurate in HSPICE simulation. Then measurement technique is applied to an Intelreg Core 2 Duo Processor running stress test under various random applications. The paper also discusses the precision and reproducibility of high speed current profile, icc(t) by using this reverse engineering technique. The finding enables the transient power simulation of a PDN can be done without depending on the simulated CKT/ Logic block icc(t) data. The method also improves the correlation work to be done between the pre-silicon simulated icc(t) with the measurement data from the lab.
{"title":"Study of High Speed Current Excitation Reverse Engineering Methodology Using Measured Voltage and PDN Impedance Profile from a Running Microprocessor","authors":"H. Since, B.Y.A. Jalaluddin, O.A.Y. Yeong","doi":"10.1109/EPEP.2007.4387191","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387191","url":null,"abstract":"Traditionally, power integrity engineer uses simulated transient current profile, icc(t) from the Circuit Designer as input to power delivery network, PDN to simulate worst case transient power noise. However, it is extremely difficult to simulate the maximum current profile from large circuit or logic block. It increases the difficulties when the circuit/ logic run at random application. The paper discusses the reverse engineering method to regenerate high speed stimulus current from the given PDN and measured voltage waveform. The paper firstly verified that the reverse engineering method proven to be accurate in HSPICE simulation. Then measurement technique is applied to an Intelreg Core 2 Duo Processor running stress test under various random applications. The paper also discusses the precision and reproducibility of high speed current profile, icc(t) by using this reverse engineering technique. The finding enables the transient power simulation of a PDN can be done without depending on the simulated CKT/ Logic block icc(t) data. The method also improves the correlation work to be done between the pre-silicon simulated icc(t) with the measurement data from the lab.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117121914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387133
H. Kwak, H. Ke, B. Lee, T. Hubing
Various multi-layer ceramic capacitor (MLCC) geometries with horizontally and vertically oriented plates are modeled to determine the equivalent series inductance. It shows that the plate stack location and dimensions (independent of plate orientation) are the most significant factors affecting the inductance.
{"title":"Plate Orientation Effect on the Inductance of Multi-Layer Ceramic Capacitors","authors":"H. Kwak, H. Ke, B. Lee, T. Hubing","doi":"10.1109/EPEP.2007.4387133","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387133","url":null,"abstract":"Various multi-layer ceramic capacitor (MLCC) geometries with horizontally and vertically oriented plates are modeled to determine the equivalent series inductance. It shows that the plate stack location and dimensions (independent of plate orientation) are the most significant factors affecting the inductance.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127152601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387136
S. Min, C.-S. Seo, S. Lapushin, L. Carastro, S. Dalmia, G. White, M. Swaminathan
This paper presents a parasitic-aware design method using parameterization of embedded passive devices on multilayer organic substrates. The parameterization enables designers to map electrical circuits into high quality physical layouts and to use parasitics of embedded inductors and capacitors for high quality RF design. The proposed method was demonstrated through design of compact, high performance bandpass filter on multilayer organic substrates.
{"title":"Parasitic-Aware RF Design via Parameterization of Embedded Passives on Multilayer Organic Substrates","authors":"S. Min, C.-S. Seo, S. Lapushin, L. Carastro, S. Dalmia, G. White, M. Swaminathan","doi":"10.1109/EPEP.2007.4387136","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387136","url":null,"abstract":"This paper presents a parasitic-aware design method using parameterization of embedded passive devices on multilayer organic substrates. The parameterization enables designers to map electrical circuits into high quality physical layouts and to use parasitics of embedded inductors and capacitors for high quality RF design. The proposed method was demonstrated through design of compact, high performance bandpass filter on multilayer organic substrates.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117338543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387119
Hao Shi
The relations between the sampled sequences of the real and imaginary parts of a causal function are found based on sampling theorem and causality. An iterative procedure is devised to update any frequency-domain causal sequence, which can be applied to refine any DC extrapolation of S-parameters.
{"title":"A Refinement Procedure for S-Parameter DC Extrapolation based on Sampling Theorem and Causality","authors":"Hao Shi","doi":"10.1109/EPEP.2007.4387119","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387119","url":null,"abstract":"The relations between the sampled sequences of the real and imaginary parts of a causal function are found based on sampling theorem and causality. An iterative procedure is devised to update any frequency-domain causal sequence, which can be applied to refine any DC extrapolation of S-parameters.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"69 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121015975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387138
M. Pathak, S. Vadlamudi, J. Beaver, S. Lim
In this paper we propose a methodology for automatic layout generation of embedded passive RF circuits. Physical layout generation of such designs is challenging since the response of a given layout is tightly coupled with the response of the individual components and the effect of interconnect parasitics. Our approach is to make use of circuit models to represent and optimize a given layout and use non-linear optimization at various stages to obtain the desired goals. Full-wave EM simulations is completely out of the design loop, so our methodology significantly reduces the design time for RF embedded passive circuits.
{"title":"Automatic Layout Generation of RF Embedded Passive Designs","authors":"M. Pathak, S. Vadlamudi, J. Beaver, S. Lim","doi":"10.1109/EPEP.2007.4387138","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387138","url":null,"abstract":"In this paper we propose a methodology for automatic layout generation of embedded passive RF circuits. Physical layout generation of such designs is challenging since the response of a given layout is tightly coupled with the response of the individual components and the effect of interconnect parasitics. Our approach is to make use of circuit models to represent and optimize a given layout and use non-linear optimization at various stages to obtain the desired goals. Full-wave EM simulations is completely out of the design loop, so our methodology significantly reduces the design time for RF embedded passive circuits.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123647770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387159
Joong-Ho Kim, Woopoung Kim, D. Oh, R. Schmitt, J. Feng, C. Yuan, L. Luo, J. Wilson
Simultaneous switching output noise (SSO) in single-ended signaling systems is one of the major performance limiters as data rate scales higher. This paper studies the impact of SSO on high performance graphic memory systems (GDDR3/4) using a systematic approach considering both signal and power integrity simultaneously. Specifically, power distribution network (PDN) and channel models are co-simulated in order to study the impact of SSO noise on channel voltage and timing margin. The reference voltage (VREF) noise is also considered as SSO noise couples to both signal and VREF. A methodology for characterizing the system performance by separating high and medium frequency analysis is demonstrated. The worst case system performance is simulated by varying data patterns to excite either medium (100-300 MHz) or high (GHz) frequency noise. A data bus inversion (DBI) coding has recently introduced in GDDR4 to remedy SSO noise and its effectiveness is also investigated in this paper. Finally, the system performance is compared between 4-layer flip-chip and 2-layer chip-scaled packages.
{"title":"Performance Impact of Simultaneous Switching Output Noise on Graphic Memory Systems","authors":"Joong-Ho Kim, Woopoung Kim, D. Oh, R. Schmitt, J. Feng, C. Yuan, L. Luo, J. Wilson","doi":"10.1109/EPEP.2007.4387159","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387159","url":null,"abstract":"Simultaneous switching output noise (SSO) in single-ended signaling systems is one of the major performance limiters as data rate scales higher. This paper studies the impact of SSO on high performance graphic memory systems (GDDR3/4) using a systematic approach considering both signal and power integrity simultaneously. Specifically, power distribution network (PDN) and channel models are co-simulated in order to study the impact of SSO noise on channel voltage and timing margin. The reference voltage (VREF) noise is also considered as SSO noise couples to both signal and VREF. A methodology for characterizing the system performance by separating high and medium frequency analysis is demonstrated. The worst case system performance is simulated by varying data patterns to excite either medium (100-300 MHz) or high (GHz) frequency noise. A data bus inversion (DBI) coding has recently introduced in GDDR4 to remedy SSO noise and its effectiveness is also investigated in this paper. Finally, the system performance is compared between 4-layer flip-chip and 2-layer chip-scaled packages.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128442311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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