Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387169
J. Schutt-Ainé
An overview of the latency insertion method (LIM) is presented in this paper. Extensions and improvements of the LIM formulation are discussed and techniques that exploit the versatility of the algorithm are compared. It is shown that the algorithm can be extended to simulate frequency-dependent networks. In addition, block partitioning and parallelization methods can further enhance the speed of the algorithm.
{"title":"LIM-Based Algorithms for the Transient Simulation of Large Networks","authors":"J. Schutt-Ainé","doi":"10.1109/EPEP.2007.4387169","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387169","url":null,"abstract":"An overview of the latency insertion method (LIM) is presented in this paper. Extensions and improvements of the LIM formulation are discussed and techniques that exploit the versatility of the algorithm are compared. It is shown that the algorithm can be extended to simulate frequency-dependent networks. In addition, block partitioning and parallelization methods can further enhance the speed of the algorithm.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117239107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387177
E. Liu, Xingchang Wei, Z. Oo, E. Li
We developed a two-dimensional full wave method for efficient power integrity and EMI Analysis of general power/ground planes in high-speed electronic packages. The resultant equivalent magnetic source from the 2D simulation is used for EMI analysis via the free-space Green's function. Both analytical and experimental validation shows that the method is accurate and efficient.
{"title":"An Efficient Method for Power integrity and EMI Analysis of Irregular-Shaped Power/Ground Planes in Packages","authors":"E. Liu, Xingchang Wei, Z. Oo, E. Li","doi":"10.1109/EPEP.2007.4387177","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387177","url":null,"abstract":"We developed a two-dimensional full wave method for efficient power integrity and EMI Analysis of general power/ground planes in high-speed electronic packages. The resultant equivalent magnetic source from the 2D simulation is used for EMI analysis via the free-space Green's function. Both analytical and experimental validation shows that the method is accurate and efficient.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121660685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387181
Kaiyu Mao, Jilin Tan, Jianming Jin
A domain decomposition method (DDM) is developed to improve the efficiency of the finite element simulation of interconnects on multilayered printed circuit boards, which helps reduce memory requirements and CPU time without sacrificing the final accuracy. It takes advantage of the multilayered structure and decomposes the board into several single layers separated by power or ground planes. The simulation of each layer can be carried out independently. Connections between neighboring layers are realized by small holes ("vias"), whose computation is accomplished in a trivial final combination procedure. The total memory requirement is only related to the largest single layer. The CPU time is also found to be less than that of the full board simulation. This domain decomposition method further permits a convenient and practical way for parallel computation.
{"title":"A Domain Decomposition Method for the Finite Element Simulation of Circuit Board Interconnects","authors":"Kaiyu Mao, Jilin Tan, Jianming Jin","doi":"10.1109/EPEP.2007.4387181","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387181","url":null,"abstract":"A domain decomposition method (DDM) is developed to improve the efficiency of the finite element simulation of interconnects on multilayered printed circuit boards, which helps reduce memory requirements and CPU time without sacrificing the final accuracy. It takes advantage of the multilayered structure and decomposes the board into several single layers separated by power or ground planes. The simulation of each layer can be carried out independently. Connections between neighboring layers are realized by small holes (\"vias\"), whose computation is accomplished in a trivial final combination procedure. The total memory requirement is only related to the largest single layer. The CPU time is also found to be less than that of the full board simulation. This domain decomposition method further permits a convenient and practical way for parallel computation.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125486240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387189
J. Ahn, S. Puligundla, R. Bashirullah, R. Fox, W. Eisenstadt
This paper reports methods of signal integrity model validation for high-speed I/O chip-package systems including simultaneous switching noise, package power/ground noise and crosstalk. IBIS-models of I/O chip performance are extracted from measurements using high impedance probes. IBIS macro model based SPICE simulations and onboard measurements are compared to optimize package model over a several GHz range. A characterization IC including differential CMOS current-mode logic, (CML) and single-ended, Gunning transceiver logic, (GTL) I/O were designed with TI 65 nm digital CMOS processes. Key CMOS CML characterization data is used to investigate the effects of the package on signal integrity performance and GTL data will be forthcoming.
{"title":"In-Situ Characterization of High-Speed I/O Chip-Package Systems","authors":"J. Ahn, S. Puligundla, R. Bashirullah, R. Fox, W. Eisenstadt","doi":"10.1109/EPEP.2007.4387189","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387189","url":null,"abstract":"This paper reports methods of signal integrity model validation for high-speed I/O chip-package systems including simultaneous switching noise, package power/ground noise and crosstalk. IBIS-models of I/O chip performance are extracted from measurements using high impedance probes. IBIS macro model based SPICE simulations and onboard measurements are compared to optimize package model over a several GHz range. A characterization IC including differential CMOS current-mode logic, (CML) and single-ended, Gunning transceiver logic, (GTL) I/O were designed with TI 65 nm digital CMOS processes. Key CMOS CML characterization data is used to investigate the effects of the package on signal integrity performance and GTL data will be forthcoming.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116911073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387172
Tao Su, Xiaofeng Wang, Zhengang bai, V. Vennam
This paper describes the application of parallel algorithms for analyzing the electronic packages and PCB's in a fast and efficient manner. The effectiveness of multithreading at various stages of the analysis has been illustrated. The application of distributed computation to further accelerate the solution process is demonstrated.
{"title":"Efficient Signal and Power Integrity Analysis Using Parallel Techniques","authors":"Tao Su, Xiaofeng Wang, Zhengang bai, V. Vennam","doi":"10.1109/EPEP.2007.4387172","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387172","url":null,"abstract":"This paper describes the application of parallel algorithms for analyzing the electronic packages and PCB's in a fast and efficient manner. The effectiveness of multithreading at various stages of the analysis has been illustrated. The application of distributed computation to further accelerate the solution process is demonstrated.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127196060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387198
A. Jerome, P. Gunupudi, M. Nakhla
A new, efficient and accurate parameterized simulation method for large nonlinear VLSI circuits is presented in this paper. The proposed method was applied to practical VLSI circuits and significant speed up was obtained.
{"title":"Efficient Parameterized Nonlinear Simulation of VLSI Circuits using Domain Decomposition Techniques","authors":"A. Jerome, P. Gunupudi, M. Nakhla","doi":"10.1109/EPEP.2007.4387198","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387198","url":null,"abstract":"A new, efficient and accurate parameterized simulation method for large nonlinear VLSI circuits is presented in this paper. The proposed method was applied to practical VLSI circuits and significant speed up was obtained.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126324463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387151
Soujanna Sarkar, A. Brahme, G. Subash Chandar
In this paper, we describe the design margin methodology that comprehends uncertainties at both chip and board level for a DDR-1 interface. These include effects that are not modeled in static timing analysis and SPICE. This methodology enables to predictably ensure silicon performance.
{"title":"Design Margin Methodology for DDR Interface","authors":"Soujanna Sarkar, A. Brahme, G. Subash Chandar","doi":"10.1109/EPEP.2007.4387151","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387151","url":null,"abstract":"In this paper, we describe the design margin methodology that comprehends uncertainties at both chip and board level for a DDR-1 interface. These include effects that are not modeled in static timing analysis and SPICE. This methodology enables to predictably ensure silicon performance.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114626310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387117
M. Mondal, B. Mutnury, P. Patel, S. Connor, B. Archambeault, M. Cases
Non-uniform current return path in multi-board systems induces significant common mode noise in high speed differential signals. The effect of the common mode noise on electrical signals considering inductance of inter-board connectors is described in this paper using measurement and modeling results. An effective and accurate method for modeling the common mode noise is proposed to ensure better design practices.
{"title":"Electrical Analysis of Multi-board PCB Systems with Differential Signaling Considering Non-ideal Common Ground Connection","authors":"M. Mondal, B. Mutnury, P. Patel, S. Connor, B. Archambeault, M. Cases","doi":"10.1109/EPEP.2007.4387117","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387117","url":null,"abstract":"Non-uniform current return path in multi-board systems induces significant common mode noise in high speed differential signals. The effect of the common mode noise on electrical signals considering inductance of inter-board connectors is described in this paper using measurement and modeling results. An effective and accurate method for modeling the common mode noise is proposed to ensure better design practices.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"75 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132027276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387127
T. Moselhy, L. Daniel
In this paper we present stochastic high order basis functions suitable for the volumetric discretization of interconnect structures. The proposed basis functions are wideband, and can easily be integrated within a stochastic magneto-quasistatic (MQS) or a fullwave mixed potential integral equation (MPIE) solver, rendering the stochastic formulation computationally efficient. In addition, our high order basis functions facilitate the calculation of a correction term, improving the accuracy of the impedance ensemble average.
{"title":"Stochastic High Order Basis Functions for Volume Integral Equation with Surface Roughness","authors":"T. Moselhy, L. Daniel","doi":"10.1109/EPEP.2007.4387127","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387127","url":null,"abstract":"In this paper we present stochastic high order basis functions suitable for the volumetric discretization of interconnect structures. The proposed basis functions are wideband, and can easily be integrated within a stochastic magneto-quasistatic (MQS) or a fullwave mixed potential integral equation (MPIE) solver, rendering the stochastic formulation computationally efficient. In addition, our high order basis functions facilitate the calculation of a correction term, improving the accuracy of the impedance ensemble average.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134561096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387123
Se-jung Moon, A. Cangellaris
A SPICE-compatible equivalent circuit representation is proposed for the scattering-parameter matrix representation of passive networks that exhibit transport delay. The methodology exploits the representation of the scattering parameters in terms of a product of rational function of the complex frequency s and the transcendental function exp(-Ts), where T is the known transport delay.
{"title":"SPICE-Compatible Representations of S-Parameter Matrices of Passive Networks with Transport Delay","authors":"Se-jung Moon, A. Cangellaris","doi":"10.1109/EPEP.2007.4387123","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387123","url":null,"abstract":"A SPICE-compatible equivalent circuit representation is proposed for the scattering-parameter matrix representation of passive networks that exhibit transport delay. The methodology exploits the representation of the scattering parameters in terms of a product of rational function of the complex frequency s and the transcendental function exp(-Ts), where T is the known transport delay.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125113173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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