Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387149
Zhaoqing Chen
New methods for predicting the worst-case crosstalk caused by intersymbol interference and the worst-case eye opening including crosstalk effect are proposed. The new method for predicting the worst-case crosstalk is based on simulated or measured crosstalk caused by a single bit aggressor signal. By using the derived worst-case crosstalk and the no-crosstalk worst-case eye opening, we can get worst-case eye opening including crosstalk effect. The proposed methods are exactly valid for packaging component and system with linear I/O devices as the signal source and load. They can also be extended to some nonlinear I/O cases with approximations.
{"title":"Predictions of the Worst-Case Crosstalk Including ISI Effect and the Worst-Case Eye Opening Including Crosstalk Effect for Electronic Packaging System Design","authors":"Zhaoqing Chen","doi":"10.1109/EPEP.2007.4387149","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387149","url":null,"abstract":"New methods for predicting the worst-case crosstalk caused by intersymbol interference and the worst-case eye opening including crosstalk effect are proposed. The new method for predicting the worst-case crosstalk is based on simulated or measured crosstalk caused by a single bit aggressor signal. By using the derived worst-case crosstalk and the no-crosstalk worst-case eye opening, we can get worst-case eye opening including crosstalk effect. The proposed methods are exactly valid for packaging component and system with linear I/O devices as the signal source and load. They can also be extended to some nonlinear I/O cases with approximations.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115556903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387194
A. Sridhar, N. Nakhla, R. Achar, M. Nakhla
This paper presents an efficient method for simulating a large number of coupled interconnects in the presence of electromagnetic interference. The algorithm is based on transverse partitioning and waveform relaxation techniques. The computational cost of the proposed algorithm increases only linearly with the number of lines compared to the more than cubic growth in conventional methods. In addition, the algorithm gives leads to parallel implementation providing further savings in computational cost.
{"title":"Fast EMC Analysis of High-Speed Interconnects via Waveform Relaxation and Transverse Partitioning","authors":"A. Sridhar, N. Nakhla, R. Achar, M. Nakhla","doi":"10.1109/EPEP.2007.4387194","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387194","url":null,"abstract":"This paper presents an efficient method for simulating a large number of coupled interconnects in the presence of electromagnetic interference. The algorithm is based on transverse partitioning and waveform relaxation techniques. The computational cost of the proposed algorithm increases only linearly with the number of lines compared to the more than cubic growth in conventional methods. In addition, the algorithm gives leads to parallel implementation providing further savings in computational cost.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115737942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387150
N. Na, M. Bailey, A. Kalantarian
This paper discusses a package design technique to enhance high speed signal performance by reducing the large discontinuity effects at the vias and solder ball interfaces. In the technique, an intentional counter-discontinuity in complementary phase to existing discontinuity is inserted to mitigate the existing discontinuity. Transmission line behavior of short multiple discontinuities are analyzed using theoretical approximation and simulation examples to demonstrate the validity of the technique. The techniques are then applied to package via and solder ball transitions of high speed differential nets using 3D simulation to evaluate improvement at target frequencies versus impact in bandwidth.
{"title":"Package Performance Improvement with Counter-Discontinuity and its Effective Bandwidth","authors":"N. Na, M. Bailey, A. Kalantarian","doi":"10.1109/EPEP.2007.4387150","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387150","url":null,"abstract":"This paper discusses a package design technique to enhance high speed signal performance by reducing the large discontinuity effects at the vias and solder ball interfaces. In the technique, an intentional counter-discontinuity in complementary phase to existing discontinuity is inserted to mitigate the existing discontinuity. Transmission line behavior of short multiple discontinuities are analyzed using theoretical approximation and simulation examples to demonstrate the validity of the technique. The techniques are then applied to package via and solder ball transitions of high speed differential nets using 3D simulation to evaluate improvement at target frequencies versus impact in bandwidth.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126243885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387115
W. Beyene
Although it is well understood that a band-limited passive system can be a source of deterministic jitter, it is less obvious that the deterministic and random jitters generated by the clock or data source can be enhanced significantly by the passive channel. In this paper, modeling and simulation techniques to predict jitter enhancement across interconnect systems are presented. The conventional method of using SPICE to calculate output jitter is computationally expensive. Instead, the effect of channel on input jitter can be represented by jitter impulse response or jitter transfer function in time or frequency domains, respectively. These jitter characteristic functions can then be used to efficiently determine the increase in jitter as signal propagates across an interconnect system. The probability mass function of jitter impulse response can also be constructed to statistically predict the jitter enhancement at lower bit-error rate. Finally, the results form SPICE-based simulation and those obtained using the jitter characteristic functions are compared.
{"title":"Modeling and Analysis Techniques of Jitter Enhancement Across High-Speed Interconnect Systems","authors":"W. Beyene","doi":"10.1109/EPEP.2007.4387115","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387115","url":null,"abstract":"Although it is well understood that a band-limited passive system can be a source of deterministic jitter, it is less obvious that the deterministic and random jitters generated by the clock or data source can be enhanced significantly by the passive channel. In this paper, modeling and simulation techniques to predict jitter enhancement across interconnect systems are presented. The conventional method of using SPICE to calculate output jitter is computationally expensive. Instead, the effect of channel on input jitter can be represented by jitter impulse response or jitter transfer function in time or frequency domains, respectively. These jitter characteristic functions can then be used to efficiently determine the increase in jitter as signal propagates across an interconnect system. The probability mass function of jitter impulse response can also be constructed to statistically predict the jitter enhancement at lower bit-error rate. Finally, the results form SPICE-based simulation and those obtained using the jitter characteristic functions are compared.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"234 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126808639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387190
Qian Li, K. Melde
This paper compares four popular on-wafer calibration methods including multiline TRL, LRRM, LRM, and SOLT, based on three diverse coplanar waveguide circuits. The results show that the Multiline TRL provides the highest accuracy and repeatability for all of the circuits up to 40 GHz.
{"title":"Broadband On-Wafer Calibrations Comparison for Accuracy and Repeatability on Co-Planar Waveguide Structures","authors":"Qian Li, K. Melde","doi":"10.1109/EPEP.2007.4387190","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387190","url":null,"abstract":"This paper compares four popular on-wafer calibration methods including multiline TRL, LRRM, LRM, and SOLT, based on three diverse coplanar waveguide circuits. The results show that the Multiline TRL provides the highest accuracy and repeatability for all of the circuits up to 40 GHz.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"44 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120877400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387147
P. Patel, R. Ahmed, B. Herrman, M. Cases, P. Seidel, G. Oganessyan, R. Fox
The goal of this paper is to describe some of the design choices made in a BladeCenter system design. This paper will focus on the connector modeling that was used to make design trade-offs, unique to a 10 Gbps serial system. Connectors are a significant source of crosstalk noise in a system, which could increase jitter in the resulting eye pattern. Since crosstalk jitter is uncorrelated from the link data pattern, it is hard to remove through equalization techniques. This paper provides a process to extract accurate coupled models from connectors. It also describes how modeling was used to predict crosstalk noise and shows how a small percentage of connector crosstalk can have a significant impact on the over all signal distortion, if the connector pin assignment is done randomly.
{"title":"Crosstalk Measurement, Extraction and Validation in 10Gbps Serial Systems","authors":"P. Patel, R. Ahmed, B. Herrman, M. Cases, P. Seidel, G. Oganessyan, R. Fox","doi":"10.1109/EPEP.2007.4387147","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387147","url":null,"abstract":"The goal of this paper is to describe some of the design choices made in a BladeCenter system design. This paper will focus on the connector modeling that was used to make design trade-offs, unique to a 10 Gbps serial system. Connectors are a significant source of crosstalk noise in a system, which could increase jitter in the resulting eye pattern. Since crosstalk jitter is uncorrelated from the link data pattern, it is hard to remove through equalization techniques. This paper provides a process to extract accurate coupled models from connectors. It also describes how modeling was used to predict crosstalk noise and shows how a small percentage of connector crosstalk can have a significant impact on the over all signal distortion, if the connector pin assignment is done randomly.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133997574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387170
N. Nakhla, M. Nakhla, R. Achar, A. Ruehli
The large number of coupled lines in an interconnect structure is a serious limiting factor in simulating high-speed circuits. In this paper, a transverse partitioning algorithm is presented for transient analysis of large multiconductor transmission line circuits. The new method uses a passive delay extraction-based macromodelling algorithm which makes the method suitable for both long and short lines. The computational cost of the proposed method grows linearly with the number of coupled lines. In addition, the algorithm is highly suitable for parallel implementation leading to further significant reduction in the computational complexity.
{"title":"Parallel Simulation of High-Speed Interconnects using Delay Extraction and Transverse Partitioning","authors":"N. Nakhla, M. Nakhla, R. Achar, A. Ruehli","doi":"10.1109/EPEP.2007.4387170","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387170","url":null,"abstract":"The large number of coupled lines in an interconnect structure is a serious limiting factor in simulating high-speed circuits. In this paper, a transverse partitioning algorithm is presented for transient analysis of large multiconductor transmission line circuits. The new method uses a passive delay extraction-based macromodelling algorithm which makes the method suitable for both long and short lines. The computational cost of the proposed method grows linearly with the number of coupled lines. In addition, the algorithm is highly suitable for parallel implementation leading to further significant reduction in the computational complexity.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"69 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113970194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387160
B. Young
A comprehensive sweep of detailed time-domain simulations using 3D PEEC models of the package and PCB are used to map out the design space and to set performance expectations for 0402 and 0204 ceramic chip capacitors for use as on-package decoupling capacitors.
{"title":"Selection Criteria and Tradeoffs for 0402 and 0204 Ceramic Chip Capacitors for On-Package Decoupling Applications","authors":"B. Young","doi":"10.1109/EPEP.2007.4387160","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387160","url":null,"abstract":"A comprehensive sweep of detailed time-domain simulations using 3D PEEC models of the package and PCB are used to map out the design space and to set performance expectations for 0402 and 0204 ceramic chip capacitors for use as on-package decoupling capacitors.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124655413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387135
S. Mehta, P. Petre
We will report on HRL Laboratories' progress in developing state-of-the-art, extremely miniature, combline filters. These filters utilize standard semiconductor substrates, and are fabricated and packaged at the wafer-level -this ensures high reproducibility in device performance, and allows large scale production at a significant cost reduction. The salient filter features are: small size, low insertion loss, tunability, high EM isolation, high power handling capability, and high out of band rejection.
{"title":"Wafer Level Fabrication and Packaging of Miniature Combline Filters","authors":"S. Mehta, P. Petre","doi":"10.1109/EPEP.2007.4387135","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387135","url":null,"abstract":"We will report on HRL Laboratories' progress in developing state-of-the-art, extremely miniature, combline filters. These filters utilize standard semiconductor substrates, and are fabricated and packaged at the wafer-level -this ensures high reproducibility in device performance, and allows large scale production at a significant cost reduction. The salient filter features are: small size, low insertion loss, tunability, high EM isolation, high power handling capability, and high out of band rejection.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127456444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387195
K. Butt, I. Jeffrey, Feng Ling, V. Okhmatovski
From the results of the previous section it is apparent that kernel evaluations by means of interpolation from a pre-existing database is much more time-efficient for computing both the near-interactions and the matrix-vector product. In fact, the Best-MEM method provides completely unacceptable computational time and should not even be considered as an option unless the computational environment possesses severe memory limitations. On the other hand, for large, multiscale geometries involving millions of unknowns, it may not be possible to store the entire kernel database. In these cases, it is our recommendation to select po(p) larger than the radius of near interactions. In this way, the near-matrix-fill time will remain unchanged and both memory levels and MVP times will be acceptable. Obviously, for distributed systems with significant amounts of memory, computational time will benefit if as much of the database is stored as memory permits.
{"title":"Parallel Discrete Complex Image Method for Barnes-Hut Accelerated Capacitance Extraction in Multilayered Substrates","authors":"K. Butt, I. Jeffrey, Feng Ling, V. Okhmatovski","doi":"10.1109/EPEP.2007.4387195","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387195","url":null,"abstract":"From the results of the previous section it is apparent that kernel evaluations by means of interpolation from a pre-existing database is much more time-efficient for computing both the near-interactions and the matrix-vector product. In fact, the Best-MEM method provides completely unacceptable computational time and should not even be considered as an option unless the computational environment possesses severe memory limitations. On the other hand, for large, multiscale geometries involving millions of unknowns, it may not be possible to store the entire kernel database. In these cases, it is our recommendation to select po(p) larger than the radius of near interactions. In this way, the near-matrix-fill time will remain unchanged and both memory levels and MVP times will be acceptable. Obviously, for distributed systems with significant amounts of memory, computational time will benefit if as much of the database is stored as memory permits.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124150464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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