Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387148
Haikun Zhu, Chung-Kuan Cheng, A. Deutsch, G. Katopis
As electronic system design evolves to the era of chip-packaging co-design, signal quality prediction and optimization are becoming important for system level interconnects. In this paper, an analytical method for predicting the worst-case jitter and eye-opening based on an arbitrary bitonic step response is proposed. Experimental results show that the proposed technique is able to achieve as small as less than 5% error compared to Hspice simulation. The analytical method is then utilized for fast optimization of a novel distributive passive compensation scheme.
{"title":"Predicting and Optimizing Jitter and Eye-Opening Based on Bitonic Step Response","authors":"Haikun Zhu, Chung-Kuan Cheng, A. Deutsch, G. Katopis","doi":"10.1109/EPEP.2007.4387148","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387148","url":null,"abstract":"As electronic system design evolves to the era of chip-packaging co-design, signal quality prediction and optimization are becoming important for system level interconnects. In this paper, an analytical method for predicting the worst-case jitter and eye-opening based on an arbitrary bitonic step response is proposed. Experimental results show that the proposed technique is able to achieve as small as less than 5% error compared to Hspice simulation. The analytical method is then utilized for fast optimization of a novel distributive passive compensation scheme.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129916840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387200
A. Varma, M. Steer, P. Franzon
System level simulation and validation of a new macromodeling methodology based on IBIS (Input/Output Buffer Information Specification) models is presented. Enhancements of the black-box techniques discussed in [1] are discussed. The proposed macromodel is circuit based and can be customized by model makers or users. The new macromodel produces models that can be simulated accurately for Simultaneous Switching Noise (SSN). To demonstrate the solution, a CMOS voltage-mode driver circuit and a MICRON DDR2 driver are simulated using real life package models and compared with equivalent circuits created with IBIS models of the same drivers.
{"title":"System level Validation of Improved IO Buffer Behavioral Modeling Methodology Based on IBIS","authors":"A. Varma, M. Steer, P. Franzon","doi":"10.1109/EPEP.2007.4387200","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387200","url":null,"abstract":"System level simulation and validation of a new macromodeling methodology based on IBIS (Input/Output Buffer Information Specification) models is presented. Enhancements of the black-box techniques discussed in [1] are discussed. The proposed macromodel is circuit based and can be customized by model makers or users. The new macromodel produces models that can be simulated accurately for Simultaneous Switching Noise (SSN). To demonstrate the solution, a CMOS voltage-mode driver circuit and a MICRON DDR2 driver are simulated using real life package models and compared with equivalent circuits created with IBIS models of the same drivers.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126795163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387165
V. Pynttari, R. Makinen, J. Lilja, V. Pekkanen, M. Mantysalo, P. Mansikkamaki, M. Kivikoski
The conductor loss of very thin lossy printed silver nanoparticle traces manufactured using the printable electronics technology is characterized up to 10 GHz by simulations and measurements. Microstrip resonators are used as test structures.
{"title":"High-frequency characterization and simulation of conductor loss in printable electronics technology","authors":"V. Pynttari, R. Makinen, J. Lilja, V. Pekkanen, M. Mantysalo, P. Mansikkamaki, M. Kivikoski","doi":"10.1109/EPEP.2007.4387165","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387165","url":null,"abstract":"The conductor loss of very thin lossy printed silver nanoparticle traces manufactured using the printable electronics technology is characterized up to 10 GHz by simulations and measurements. Microstrip resonators are used as test structures.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"515 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123071242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387182
Y. Nakazono, H. Asai
In this paper, we propose a fast electromagnetic simulation technique using multi-rate FDTD (finite-difference time-domain) method. In this work, the time step size is selected according to the grid cell size of each part in the given space. Then, this method can reduce the calculation costs without violating the stability condition. Finally, some electromagnetic simulations of the example 2-D free space are performed by the proposed method. From the simulation results, the validity and the efficiency of this technique is verified.
{"title":"Multi-Rate FDTD Method for Fast Electromagnetic Simulation","authors":"Y. Nakazono, H. Asai","doi":"10.1109/EPEP.2007.4387182","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387182","url":null,"abstract":"In this paper, we propose a fast electromagnetic simulation technique using multi-rate FDTD (finite-difference time-domain) method. In this work, the time step size is selected according to the grid cell size of each part in the given space. Then, this method can reduce the calculation costs without violating the stability condition. Finally, some electromagnetic simulations of the example 2-D free space are performed by the proposed method. From the simulation results, the validity and the efficiency of this technique is verified.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130121189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387164
A. Suntives, R. Abhari
The enclosed volume by a substrate integrated waveguide interconnect is re-utilized to increase the channel capacity. A stripline is embedded inside the waveguide, thus a dual-mode or hybrid interconnect structure is created. Isolation and transmission characteristics of the two signal channels are evaluated by fullwave simulations. Measurements of the fabricated prototype demonstrate that the hybrid platform handles an aggregate data rate of 8.5 Gb/s.
{"title":"Dual-Mode High-Speed Data Transmission Using Substrate Integrated Waveguide Interconnects","authors":"A. Suntives, R. Abhari","doi":"10.1109/EPEP.2007.4387164","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387164","url":null,"abstract":"The enclosed volume by a substrate integrated waveguide interconnect is re-utilized to increase the channel capacity. A stripline is embedded inside the waveguide, thus a dual-mode or hybrid interconnect structure is created. Isolation and transmission characteristics of the two signal channels are evaluated by fullwave simulations. Measurements of the fabricated prototype demonstrate that the hybrid platform handles an aggregate data rate of 8.5 Gb/s.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133928603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387185
Feng Sheng, S. Chakravarty, D. Jiao
This paper proposes an efficient technique for reducing a 3D layered system matrix to a 2D layered one in the framework of the frequency-domain layered finite element method. This technique is capable of solving the volume-unknown based matrix equation in linear complexity, and hence reducing the complexity of 3D-to-2D reduction from O(M3) to O(M2), with M being the number of top/bottom surface unknowns in a single layer. The numerical procedure is rigorous without making any approximation. The technique applies to any arbitrarily-shaped multilayer IC problem. Numerical and experimental results have demonstrated its accuracy and efficiency.
{"title":"An Efficient 3D-to-2D Reduction Technique for Frequency-Domain Layered Finite Element Analysis of Large-Scale High-Frequency Integrated Circuits","authors":"Feng Sheng, S. Chakravarty, D. Jiao","doi":"10.1109/EPEP.2007.4387185","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387185","url":null,"abstract":"This paper proposes an efficient technique for reducing a 3D layered system matrix to a 2D layered one in the framework of the frequency-domain layered finite element method. This technique is capable of solving the volume-unknown based matrix equation in linear complexity, and hence reducing the complexity of 3D-to-2D reduction from O(M3) to O(M2), with M being the number of top/bottom surface unknowns in a single layer. The numerical procedure is rigorous without making any approximation. The technique applies to any arbitrarily-shaped multilayer IC problem. Numerical and experimental results have demonstrated its accuracy and efficiency.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130792583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387176
E. Kulali, E. Wasserman, Ji Zheng
A compact SPICE equivalent circuit model of full-chip power network is proposed in this paper to address the system power integrity co-design and optimization. The theory and procedures for the generation of the compact chip power model is described. The accuracy validation of the chip power model is also presented.
{"title":"Chip Power Model - A New Methodology for System Power Integrity Analysis and Design","authors":"E. Kulali, E. Wasserman, Ji Zheng","doi":"10.1109/EPEP.2007.4387176","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387176","url":null,"abstract":"A compact SPICE equivalent circuit model of full-chip power network is proposed in this paper to address the system power integrity co-design and optimization. The theory and procedures for the generation of the compact chip power model is described. The accuracy validation of the chip power model is also presented.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124824167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387184
K. Srinivasan, P. Yadav, E. Engin, M. Swaminathan
Transient EM simulation using Laguerre polynomials is unconditionally stable and therefore, has the advantage of not being limited by any time-step. In the Laguerre method, the transient waveform of the field of interest is obtained by solving for a set of coefficients. These coefficients are used as weights and the weighted sum of Laguerre basis functions represents the time-domain waveform. This paper proposes a numerical solution to solve for the right number of basis coefficients in order to maximize the accuracy of the output transient waveform of interest. The method of choosing the right number of basis functions outlined in this paper is a key step for automation of the transient simulation technique using Laguerre polynomials.
{"title":"Choosing the Right Number of Basis Functions in Multiscale Transient Simulation Using Laguerre Polynomials","authors":"K. Srinivasan, P. Yadav, E. Engin, M. Swaminathan","doi":"10.1109/EPEP.2007.4387184","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387184","url":null,"abstract":"Transient EM simulation using Laguerre polynomials is unconditionally stable and therefore, has the advantage of not being limited by any time-step. In the Laguerre method, the transient waveform of the field of interest is obtained by solving for a set of coefficients. These coefficients are used as weights and the weighted sum of Laguerre basis functions represents the time-domain waveform. This paper proposes a numerical solution to solve for the right number of basis coefficients in order to maximize the accuracy of the output transient waveform of interest. The method of choosing the right number of basis functions outlined in this paper is a key step for automation of the transient simulation technique using Laguerre polynomials.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130211685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387129
Timo Tarvainentl, Tuukka Ruokamo, Lauri Hynynen, llkka Kelander, Pia Kotiranta
Control of noise coupling between high-speed interconnections and RF components in mobile devices is vital. This paper discusses software-hardware-electromagnetics modeling flow for early on EMI optimization of component, such as high speed interconnection, placement.
{"title":"SW-HW-EM modeling flow for multi-port EMI optimization of component placement in mobile devices","authors":"Timo Tarvainentl, Tuukka Ruokamo, Lauri Hynynen, llkka Kelander, Pia Kotiranta","doi":"10.1109/EPEP.2007.4387129","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387129","url":null,"abstract":"Control of noise coupling between high-speed interconnections and RF components in mobile devices is vital. This paper discusses software-hardware-electromagnetics modeling flow for early on EMI optimization of component, such as high speed interconnection, placement.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130722153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387114
B. Wang, Min Wang, W. Ryu
6b9b encoding scheme is proposed to effectively reduces single-ended interconnect. The noise reduction also translates into smaller silicon timing jitter numbers and additional system bandwidth. Moreover, this scheme also reduces active power consumption by 25%.
{"title":"6b9b Encoding Scheme for Improving Single-Ended Interface Bandwidth and Reducing Power Consumption without Pin Count Increase","authors":"B. Wang, Min Wang, W. Ryu","doi":"10.1109/EPEP.2007.4387114","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387114","url":null,"abstract":"6b9b encoding scheme is proposed to effectively reduces single-ended interconnect. The noise reduction also translates into smaller silicon timing jitter numbers and additional system bandwidth. Moreover, this scheme also reduces active power consumption by 25%.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130915469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：