Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387199
I. Stievano, C. Siviero, I. Maio, F. Canavero
This paper addresses the generation of enhanced behavioral models for digital IC buffers. The proposed models can reproduce the behavior of real devices also for large fluctuations of the power supply voltage. The models can be easily estimated from port transient responses and can be effectively implemented in any commercial tool as SPICE subcircuits or VHDL-AMS descriptions.
{"title":"Macromodels of IC Buffers Allowing for Large Power Supply Fluctuations","authors":"I. Stievano, C. Siviero, I. Maio, F. Canavero","doi":"10.1109/EPEP.2007.4387199","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387199","url":null,"abstract":"This paper addresses the generation of enhanced behavioral models for digital IC buffers. The proposed models can reproduce the behavior of real devices also for large fluctuations of the power supply voltage. The models can be easily estimated from port transient responses and can be effectively implemented in any commercial tool as SPICE subcircuits or VHDL-AMS descriptions.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126474251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387188
B. McCoy, J. Coker, R. Techentin, B. Gilbert, E. Daniel
A rapid link analysis technique is presented which simulates link performance using 4-port S-parameter models and pseudorandom driver stimulus. The mathematical technique and validation through simulation and hardware measurements of eye diagrams are presented.
{"title":"A Rapid Link Analysis Technique Using Four-Port Scattering Parameters","authors":"B. McCoy, J. Coker, R. Techentin, B. Gilbert, E. Daniel","doi":"10.1109/EPEP.2007.4387188","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387188","url":null,"abstract":"A rapid link analysis technique is presented which simulates link performance using 4-port S-parameter models and pseudorandom driver stimulus. The mathematical technique and validation through simulation and hardware measurements of eye diagrams are presented.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125110862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387139
Jeng-Hau Lin, Wei-Da Guo, G. Shiue, Chien-Min Lin, Tian-Wei Huang, R. Wu
A novel algorithm for fast and accurately determining the height and width of eye diagrams at the receiving ends of transmission lines is proposed. While the two parameters concerned in the conductive and dielectric losses in response to the impulse stimulus are derived, the transfer function associated with the propagation coefficient to represent the signaling mechanism on the eye diagram can be developed. A systematic flow is implemented to acquire the predictable eye diagrams in a good agreement with the analysis results by the time-domain circuit simulator for varying designed geometries.
{"title":"Fast Algorithm for Determining Eye-Diagram Characteristics of Lossy Transmission Lines","authors":"Jeng-Hau Lin, Wei-Da Guo, G. Shiue, Chien-Min Lin, Tian-Wei Huang, R. Wu","doi":"10.1109/EPEP.2007.4387139","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387139","url":null,"abstract":"A novel algorithm for fast and accurately determining the height and width of eye diagrams at the receiving ends of transmission lines is proposed. While the two parameters concerned in the conductive and dielectric losses in response to the impulse stimulus are derived, the transfer function associated with the propagation coefficient to represent the signaling mechanism on the eye diagram can be developed. A systematic flow is implemented to acquire the predictable eye diagrams in a good agreement with the analysis results by the time-domain circuit simulator for varying designed geometries.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"285 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131718015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387163
A. Suntives, A. Khajooeizadeh, R. Abhari
In this paper, a metamaterial interconnect is investigated and evaluated through simulations and measurements. Short-pulse propagation technique is utilized to characterize the propagation constant of the metamaterial transmission line. The extracted beta is subsequently used in the design of a metamaterial backward coupler, which is compared with a conventional microstrip coupler experimentally. The metamaterial coupler demonstrates superior performance over its conventional microstrip counterpart.
{"title":"Characterization of Metamaterial Interconnects","authors":"A. Suntives, A. Khajooeizadeh, R. Abhari","doi":"10.1109/EPEP.2007.4387163","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387163","url":null,"abstract":"In this paper, a metamaterial interconnect is investigated and evaluated through simulations and measurements. Short-pulse propagation technique is utilized to characterize the propagation constant of the metamaterial transmission line. The extracted beta is subsequently used in the design of a metamaterial backward coupler, which is compared with a conventional microstrip coupler experimentally. The metamaterial coupler demonstrates superior performance over its conventional microstrip counterpart.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132558785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387122
A. Ubolli, Stefano Grivet-Talocia
We present a general class of frequency-selective weighting schemes, allowing for a drastic accuracy improvement when embedded in passivity enforcement algorithms for linear lumped macromodels. The proposed technique minimizes the in-band model perturbation while achieving global passivity, even in the difficult case of large out-of-band passivity violations.
{"title":"Weighting Strategies for Passivity Enforcement Schemes","authors":"A. Ubolli, Stefano Grivet-Talocia","doi":"10.1109/EPEP.2007.4387122","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387122","url":null,"abstract":"We present a general class of frequency-selective weighting schemes, allowing for a drastic accuracy improvement when embedded in passivity enforcement algorithms for linear lumped macromodels. The proposed technique minimizes the in-band model perturbation while achieving global passivity, even in the difficult case of large out-of-band passivity violations.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"47 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132693978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387109
J. Weaver, M. Horowitz
Maintaining low supply impedance is a critical task in modern high-performance chip and system design, and this depends on how the current flows on the chip, package, and board power distribution layers. Using a simple inductive pickup loop previously described, we measure the per-pin via currents for a large VLSI chip in operation. Interestingly, the variation in AC current across the package was only 33%. indicating that for this chip current crowding was not an issue. Furthermore, we measured the board bypass capacitance currents as well, and found that the capacitors supplied between 80%n and 120% of the peak transient currents of the pins to which I hey were connected. Since the maximum current is only slightly larger than the current required by the attached pin, the board bypass capacitance primarily affects the pin it is connected to, and does not really bypass the other VDD pins in that region.
{"title":"Measurement of Supply Pin Current Distributions in Integrated Circuit Packages","authors":"J. Weaver, M. Horowitz","doi":"10.1109/EPEP.2007.4387109","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387109","url":null,"abstract":"Maintaining low supply impedance is a critical task in modern high-performance chip and system design, and this depends on how the current flows on the chip, package, and board power distribution layers. Using a simple inductive pickup loop previously described, we measure the per-pin via currents for a large VLSI chip in operation. Interestingly, the variation in AC current across the package was only 33%. indicating that for this chip current crowding was not an issue. Furthermore, we measured the board bypass capacitance currents as well, and found that the capacitors supplied between 80%n and 120% of the peak transient currents of the pins to which I hey were connected. Since the maximum current is only slightly larger than the current required by the attached pin, the board bypass capacitance primarily affects the pin it is connected to, and does not really bypass the other VDD pins in that region.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116119521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387130
P.E. Dahlen, T. Timpane, D. Becker, T.W. Liang, W. Martin, P. Rudrud, G.K. Bartley
This paper describes design activity which involved replacing an existing ceramic single chip module package design with a new organic laminate version, each using the same ASIC, for the purpose of cost reduction, and subject to stringent system level design constraints. Since the electrical properties and characteristics of the ceramic and organic package designs were not absolutely identical, it was necessary to perform electrical equivalency analyses at the system level.
{"title":"Maintaining System Signal and Power Integrity Characteristics as Part of a Module Cost-Reduction Exercise","authors":"P.E. Dahlen, T. Timpane, D. Becker, T.W. Liang, W. Martin, P. Rudrud, G.K. Bartley","doi":"10.1109/EPEP.2007.4387130","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387130","url":null,"abstract":"This paper describes design activity which involved replacing an existing ceramic single chip module package design with a new organic laminate version, each using the same ASIC, for the purpose of cost reduction, and subject to stringent system level design constraints. Since the electrical properties and characteristics of the ceramic and organic package designs were not absolutely identical, it was necessary to perform electrical equivalency analyses at the system level.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124731736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387131
Junho Lee, Hyunseok Kim, Kimyung Kyung, Minyoung You, Hyungdong Lee, Kunwoo Park, Byong-Tae Chung
In this paper, design procedure and analysis method of power delivery network of DDR2 memory chip are introduced. The power delivery network of memory chip is optimized by tuning the location of power/ground chip pad and on-chip decoupling capacitor's W/L size. The results show that the properly designed power/ground chip pads and decoupling capacitors greatly reduce power noise, resulting in the reduction of chip cost by using less area for on-chip decoupling capacitor.
{"title":"Design, Analysis, and Optimization of DDR2 Memory Power Delivery Network","authors":"Junho Lee, Hyunseok Kim, Kimyung Kyung, Minyoung You, Hyungdong Lee, Kunwoo Park, Byong-Tae Chung","doi":"10.1109/EPEP.2007.4387131","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387131","url":null,"abstract":"In this paper, design procedure and analysis method of power delivery network of DDR2 memory chip are introduced. The power delivery network of memory chip is optimized by tuning the location of power/ground chip pad and on-chip decoupling capacitor's W/L size. The results show that the properly designed power/ground chip pads and decoupling capacitors greatly reduce power noise, resulting in the reduction of chip cost by using less area for on-chip decoupling capacitor.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130602156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387137
J. Mao, G. Fitzgerald, A. Kuo, S. Wane
In this paper, cascade-related approach and global one-single model methodology are investigated and compared in reference to real-world System-in-Package (SiP) product, which is designed using Cadence-SiP, and analyzed using Optimal SiP-enabled tool suite. A complete multi-level path, which consists of three portions-integrated circuit (IC), package and printed-circuit-board (PCB) -is selected as a test vehicle to investigate the limit of cascade-based approach. The results from quasi-static and full-wave simulation are compared, and the advantage of full-wave as well as limitation of quasi-static model are discussed. An innovative concept, referenced as "residual S-parameter", is proposed to characterize the coupling at the interface of IC, package and PCB, which plays an important role in the cascading of individual modules. Impact of the proposed concept on power integrity (PI) and signal integrity (SI) analysis is emphasized. Comparisons between full-wave, quasi-static and measurement results for representative component elements (interconnect, coupled bond wires) are discussed.
{"title":"Coupled Analysis of Quasi-static and Full-Wave Solution towards IC, Package and Board Co-design","authors":"J. Mao, G. Fitzgerald, A. Kuo, S. Wane","doi":"10.1109/EPEP.2007.4387137","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387137","url":null,"abstract":"In this paper, cascade-related approach and global one-single model methodology are investigated and compared in reference to real-world System-in-Package (SiP) product, which is designed using Cadence-SiP, and analyzed using Optimal SiP-enabled tool suite. A complete multi-level path, which consists of three portions-integrated circuit (IC), package and printed-circuit-board (PCB) -is selected as a test vehicle to investigate the limit of cascade-based approach. The results from quasi-static and full-wave simulation are compared, and the advantage of full-wave as well as limitation of quasi-static model are discussed. An innovative concept, referenced as \"residual S-parameter\", is proposed to characterize the coupling at the interface of IC, package and PCB, which plays an important role in the cascading of individual modules. Impact of the proposed concept on power integrity (PI) and signal integrity (SI) analysis is emphasized. Comparisons between full-wave, quasi-static and measurement results for representative component elements (interconnect, coupled bond wires) are discussed.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127404874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387110
Y. Uematsu, H. Osaka, Y. Nishio, S. Hatano
Aiming to achieve double data rate-synchronous DRAM (DDR-SDRAM) at low-cost and with high noise tolerance by setting adequate Vref target impedance, we have established a measurement setup for Vref noise tolerance of DDR2-SDRAM on test board simulating actual memory module and measured various properties. The measured Vref noise tolerance has strong frequency-dependency; the higher the frequency, the larger the noise tolerance. We believe that this is because the intrinsic low pass filter consisted of on-chip electrical components in the test chip.
{"title":"A Method for Measuring Vref Noise Tolerance of DDR2-SDRAM on Test Board Simulatig Actual Memory Module","authors":"Y. Uematsu, H. Osaka, Y. Nishio, S. Hatano","doi":"10.1109/EPEP.2007.4387110","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387110","url":null,"abstract":"Aiming to achieve double data rate-synchronous DRAM (DDR-SDRAM) at low-cost and with high noise tolerance by setting adequate Vref target impedance, we have established a measurement setup for Vref noise tolerance of DDR2-SDRAM on test board simulating actual memory module and measured various properties. The measured Vref noise tolerance has strong frequency-dependency; the higher the frequency, the larger the noise tolerance. We believe that this is because the intrinsic low pass filter consisted of on-chip electrical components in the test chip.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126750070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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