Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387122
A. Ubolli, Stefano Grivet-Talocia
We present a general class of frequency-selective weighting schemes, allowing for a drastic accuracy improvement when embedded in passivity enforcement algorithms for linear lumped macromodels. The proposed technique minimizes the in-band model perturbation while achieving global passivity, even in the difficult case of large out-of-band passivity violations.
{"title":"Weighting Strategies for Passivity Enforcement Schemes","authors":"A. Ubolli, Stefano Grivet-Talocia","doi":"10.1109/EPEP.2007.4387122","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387122","url":null,"abstract":"We present a general class of frequency-selective weighting schemes, allowing for a drastic accuracy improvement when embedded in passivity enforcement algorithms for linear lumped macromodels. The proposed technique minimizes the in-band model perturbation while achieving global passivity, even in the difficult case of large out-of-band passivity violations.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"47 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132693978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387139
Jeng-Hau Lin, Wei-Da Guo, G. Shiue, Chien-Min Lin, Tian-Wei Huang, R. Wu
A novel algorithm for fast and accurately determining the height and width of eye diagrams at the receiving ends of transmission lines is proposed. While the two parameters concerned in the conductive and dielectric losses in response to the impulse stimulus are derived, the transfer function associated with the propagation coefficient to represent the signaling mechanism on the eye diagram can be developed. A systematic flow is implemented to acquire the predictable eye diagrams in a good agreement with the analysis results by the time-domain circuit simulator for varying designed geometries.
{"title":"Fast Algorithm for Determining Eye-Diagram Characteristics of Lossy Transmission Lines","authors":"Jeng-Hau Lin, Wei-Da Guo, G. Shiue, Chien-Min Lin, Tian-Wei Huang, R. Wu","doi":"10.1109/EPEP.2007.4387139","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387139","url":null,"abstract":"A novel algorithm for fast and accurately determining the height and width of eye diagrams at the receiving ends of transmission lines is proposed. While the two parameters concerned in the conductive and dielectric losses in response to the impulse stimulus are derived, the transfer function associated with the propagation coefficient to represent the signaling mechanism on the eye diagram can be developed. A systematic flow is implemented to acquire the predictable eye diagrams in a good agreement with the analysis results by the time-domain circuit simulator for varying designed geometries.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"285 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131718015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387141
Yu Chang, D. Oh
Accurate prediction of I/O system performance including random and deterministic jitter requires a new simulation framework beyond traditional SPICE simulation. Recently, statistical-based simulation tools, such as StatEyereg and LinkLab, have gained a special interest. These statistical simulation tools compute system bit error rates (BER) based on the probability distribution functions (PDFs) of inter-symbolic interference (ISI) noise. The ISI distribution is calculated by convolving the ISI cursors from the single bit response (SBR) of passive channels [4]. Although this approach produces fast and accurate results, it is limited to differential systems with linear drivers [1]. For more general applications, such as nonlinear single-end signaling drivers as well as the support for coding schemes, transient simulation is desirable but it is also limited by the large simulation time. In this paper, we propose a new approach based on the theory of extreme value distribution (EVD) to speed up the ISI distribution calculation. A regression test of 13 backplane channels is performed to test the accuracy and robustness of the proposed method.
{"title":"Fast ISI Characterization of Passive Channels Using Extreme Value Distribution","authors":"Yu Chang, D. Oh","doi":"10.1109/EPEP.2007.4387141","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387141","url":null,"abstract":"Accurate prediction of I/O system performance including random and deterministic jitter requires a new simulation framework beyond traditional SPICE simulation. Recently, statistical-based simulation tools, such as StatEyereg and LinkLab, have gained a special interest. These statistical simulation tools compute system bit error rates (BER) based on the probability distribution functions (PDFs) of inter-symbolic interference (ISI) noise. The ISI distribution is calculated by convolving the ISI cursors from the single bit response (SBR) of passive channels [4]. Although this approach produces fast and accurate results, it is limited to differential systems with linear drivers [1]. For more general applications, such as nonlinear single-end signaling drivers as well as the support for coding schemes, transient simulation is desirable but it is also limited by the large simulation time. In this paper, we propose a new approach based on the theory of extreme value distribution (EVD) to speed up the ISI distribution calculation. A regression test of 13 backplane channels is performed to test the accuracy and robustness of the proposed method.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"26 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114052815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387155
N. Nenadovic, E. Miersch, M. Versleijen, S. Wane
In this paper an application of an integral analysis technique is demonstrated for determining signal integrity (SI) and power integrity (PI) of complex and advanced package solutions. A representative system-in-package (SiP) product has been selected as a carrier for our study, which is focused on analysis methodology, tools and flow. In particular, possibility to easily support what-if simulations for SI and PI, including analysis with distributed on-chip decoupling capacitors is investigated and highlighted. Importance of balancing between accuracy, CPU time and ease-of-use is also underlined.
{"title":"Application of Integral Analysis Technique to Determine Signal- and Power Integrity of Advanced Packages","authors":"N. Nenadovic, E. Miersch, M. Versleijen, S. Wane","doi":"10.1109/EPEP.2007.4387155","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387155","url":null,"abstract":"In this paper an application of an integral analysis technique is demonstrated for determining signal integrity (SI) and power integrity (PI) of complex and advanced package solutions. A representative system-in-package (SiP) product has been selected as a carrier for our study, which is focused on analysis methodology, tools and flow. In particular, possibility to easily support what-if simulations for SI and PI, including analysis with distributed on-chip decoupling capacitors is investigated and highlighted. Importance of balancing between accuracy, CPU time and ease-of-use is also underlined.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116758583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387173
Xiren Wang, V. Jandhyala
Parallelized electromagnetic solvers are now becoming more prominent as computational architectures, both multicore and distributed clusters, enable multithreaded multi-tasking, and the need for larger capacity solvers is also growing with the exponential growth in complexity of microelectronic systems being analyzed with these solvers. Several techniques are proposed for improved parallel performance of fast integral equation solvers, including a 2-step balancing scheme, and restricted and hierarchical communication.
{"title":"Parallel Algorithms for Fast Integral Equation Based Solvers","authors":"Xiren Wang, V. Jandhyala","doi":"10.1109/EPEP.2007.4387173","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387173","url":null,"abstract":"Parallelized electromagnetic solvers are now becoming more prominent as computational architectures, both multicore and distributed clusters, enable multithreaded multi-tasking, and the need for larger capacity solvers is also growing with the exponential growth in complexity of microelectronic systems being analyzed with these solvers. Several techniques are proposed for improved parallel performance of fast integral equation solvers, including a 2-step balancing scheme, and restricted and hierarchical communication.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117136500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387121
P. Triverio, Michel S. Nakhla, Stefano Grivet-Talocia
We propose a numerical technique to compute, from tabulated frequency data, compact macromodels parameterized by design variables, to be used for efficient optimization, Monte Carlo analysis and design centering of complex systems. Important theoretical results on the stability of parameter-dependent models are also presented.
{"title":"Parametric Macromodeling of Multiport Networks from Tabulated Data","authors":"P. Triverio, Michel S. Nakhla, Stefano Grivet-Talocia","doi":"10.1109/EPEP.2007.4387121","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387121","url":null,"abstract":"We propose a numerical technique to compute, from tabulated frequency data, compact macromodels parameterized by design variables, to be used for efficient optimization, Monte Carlo analysis and design centering of complex systems. Important theoretical results on the stability of parameter-dependent models are also presented.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126521082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387111
M. Lamson
An integrated circuit device developed through a JEDEC standards committee with multiple, selectable, and controllable CMOS output drivers is installed in a complex plastic ball grid array package with multiple power and ground planes. A specialized circuit board is designed and used to mount the package and loads, to facilitate device control from an external signal source, and to provide output measurement ports. Measurements of simultaneous switching noise (SSN) are made under various conditions of the test chip operation, measurement points, and ground port configurations. The switching characteristics of the output drivers are shown to depend on the configuration of the package connections and the number of active outputs. Computer models of the system were generated and the data are compared to the measured values. Good correlation with models is observed to be highly dependant on using accurate driver switching characteristics.
{"title":"Test Chip Electrical Measurements with Model Correlation","authors":"M. Lamson","doi":"10.1109/EPEP.2007.4387111","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387111","url":null,"abstract":"An integrated circuit device developed through a JEDEC standards committee with multiple, selectable, and controllable CMOS output drivers is installed in a complex plastic ball grid array package with multiple power and ground planes. A specialized circuit board is designed and used to mount the package and loads, to facilitate device control from an external signal source, and to provide output measurement ports. Measurements of simultaneous switching noise (SSN) are made under various conditions of the test chip operation, measurement points, and ground port configurations. The switching characteristics of the output drivers are shown to depend on the configuration of the package connections and the number of active outputs. Computer models of the system were generated and the data are compared to the measured values. Good correlation with models is observed to be highly dependant on using accurate driver switching characteristics.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124815849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387134
Yaping Zhou, P. Harvey, B. Flachs, J. Liberty, G. Gervais, R. Mandrekar, H.H. Chen, T. Tamura
Noise characterization of the 65 nm multicore Cell Broadband Enginetrade (Cell/B.E.)* processor was performed using highly configurable workloads and selective stimulation of identical cores to study noise distribution throughout the chip. On-chip power supply noise propagation velocity and attenuation were found to be influenced by chip/package resonance in the power distribution system. Hypothesis for this phenomenon is proposed.
{"title":"Distributed On-chip Power Supply Noise Characterization of the Cell Broadband Engine","authors":"Yaping Zhou, P. Harvey, B. Flachs, J. Liberty, G. Gervais, R. Mandrekar, H.H. Chen, T. Tamura","doi":"10.1109/EPEP.2007.4387134","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387134","url":null,"abstract":"Noise characterization of the 65 nm multicore Cell Broadband Enginetrade (Cell/B.E.)* processor was performed using highly configurable workloads and selective stimulation of identical cores to study noise distribution throughout the chip. On-chip power supply noise propagation velocity and attenuation were found to be influenced by chip/package resonance in the power distribution system. Hypothesis for this phenomenon is proposed.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"272 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131545561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387203
K. Han, E. Engin, M. Swaminathan
PEEC method with global basis functions on the cylindrical coordinates is presented for efficient modeling of bond wires in system-in-package. Combination of a few basis functions accurately describes high-frequency effects of closely located wires with shorter simulation time compared to the conventional PEEC method. Simplified equivalent circuit from the proposed method is also favorable for modeling of large coupling structures.
{"title":"Cylindrical Conduction Mode Basis Functions for Modeling of Inductive Couplings in System-in-Package (SiP)","authors":"K. Han, E. Engin, M. Swaminathan","doi":"10.1109/EPEP.2007.4387203","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387203","url":null,"abstract":"PEEC method with global basis functions on the cylindrical coordinates is presented for efficient modeling of bond wires in system-in-package. Combination of a few basis functions accurately describes high-frequency effects of closely located wires with shorter simulation time compared to the conventional PEEC method. Simplified equivalent circuit from the proposed method is also favorable for modeling of large coupling structures.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131331684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387161
Gang Huang, M. Bakir, A. Naeemi, H. Chen, J. Meindl
Three-dimensional (3D) integration creates vast opportunities to improve performance and the level of integration in nanoelectronic systems. However, 3D integration presents many challenges for power delivery network design due to larger supply currents and longer power delivery paths compared to 2D systems. In this paper, an analytical physical model is derived to incorporate the impact of 3D-integration on power supply noise. The model has less than 4% error compared to SPICE simulations. Based on the model, design guidelines and opportunities for reducing power supply noise, such as inserting "decap" die and through-vias, are discussed in this paper.
{"title":"Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implication","authors":"Gang Huang, M. Bakir, A. Naeemi, H. Chen, J. Meindl","doi":"10.1109/EPEP.2007.4387161","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387161","url":null,"abstract":"Three-dimensional (3D) integration creates vast opportunities to improve performance and the level of integration in nanoelectronic systems. However, 3D integration presents many challenges for power delivery network design due to larger supply currents and longer power delivery paths compared to 2D systems. In this paper, an analytical physical model is derived to incorporate the impact of 3D-integration on power supply noise. The model has less than 4% error compared to SPICE simulations. Based on the model, design guidelines and opportunities for reducing power supply noise, such as inserting \"decap\" die and through-vias, are discussed in this paper.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114958259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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