Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200671
G. Shahidi, B. Davari, T. Bucelot, D. Zicherman, P. McFarland, A. Fink, S. Brodsky, K. Pettrilo, N. Mazzeo, R. Lombardi, M. Rodriguez, M. Polcari, T. Ning
It is shown that ultrathin SOI offers a device design advantage for operation of CMOS circuits at 77 K. The use of ultrathin SOI makes it possible to achieve low threshold at relatively high channel doping, which is necessary for reduction of short channel effects. Very-high-performance loaded NAND inverters (with delays of less than 100 ps at 2 V) were fabricated.<>
{"title":"A high performance low temperature 0.3 mu m CMOS on SIMOX","authors":"G. Shahidi, B. Davari, T. Bucelot, D. Zicherman, P. McFarland, A. Fink, S. Brodsky, K. Pettrilo, N. Mazzeo, R. Lombardi, M. Rodriguez, M. Polcari, T. Ning","doi":"10.1109/VLSIT.1992.200671","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200671","url":null,"abstract":"It is shown that ultrathin SOI offers a device design advantage for operation of CMOS circuits at 77 K. The use of ultrathin SOI makes it possible to achieve low threshold at relatively high channel doping, which is necessary for reduction of short channel effects. Very-high-performance loaded NAND inverters (with delays of less than 100 ps at 2 V) were fabricated.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123904066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200647
I. Sakai, H. Abiko, H. Kawaguchi, T. Hirayama, L.E.G. Johansson, K. Okabe
A Ti salicide process featuring pre-amorphization before Ti film deposition and sequential two-step sintering (PASET) for sub-half-micron CMOS is discussed. Pre-amorphization by As implantation can realize low and uniform sheet resistance TiSi/sub 2/ on highly As-doped n+ poly and diffusion layers with sub-half micron line width. Implanted As for pre-amorphization and sequential two step sintering prevents the TiSi/sub 2/ overgrowth on p+ poly and diffusion layers. The PASET process technology widens the process window. The resulting n- and p-MOSFETs show excellent characteristics.<>
{"title":"A new salicide process (PASET) for sub-half micron CMOS","authors":"I. Sakai, H. Abiko, H. Kawaguchi, T. Hirayama, L.E.G. Johansson, K. Okabe","doi":"10.1109/VLSIT.1992.200647","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200647","url":null,"abstract":"A Ti salicide process featuring pre-amorphization before Ti film deposition and sequential two-step sintering (PASET) for sub-half-micron CMOS is discussed. Pre-amorphization by As implantation can realize low and uniform sheet resistance TiSi/sub 2/ on highly As-doped n+ poly and diffusion layers with sub-half micron line width. Implanted As for pre-amorphization and sequential two step sintering prevents the TiSi/sub 2/ overgrowth on p+ poly and diffusion layers. The PASET process technology widens the process window. The resulting n- and p-MOSFETs show excellent characteristics.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124647661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200648
N. Yokoyama, S. Kumura, T. Yoshimura, H. Goto, N. Kobayashi, Y. Homma, E. Takeda
The fabrication of fine contact metallization down to 0.08 mu m in diameter for future 0.1- mu m-level ULSIs is discussed, and the electrical characteristics are evaluated. A two-layered etch mask, PMMA/poly-Si, was used for electron-beam delineation. Low-temperature dry etching permits the accurate patterning of the poly-Si layer in accordance with the PMMA mask, by increasing the PMMA etch-rate selectivity from 0.63 in ordinary dry etching to 15. Contact holes as small as 0.08 mu m in diameter are opened following application of the poly-Si as a mask. The combination of SiH/sub 2/F/sub 2/-reduced blanket CVD W (0.2 mu m thick)/sputtered W (30 nm thick) is used for metallization. Typical resistances are 1.5 k Omega on a 0.13- mu m-diameter contact to p/sup +/-Si and 107 Omega on a 0.18- mu m-diameter contact to n/sup +/-Si. Contact resistivities of these 0.1- mu m-level contacts are of the same levels as those of holes with diameters larger than 0.25 mu m.<>
{"title":"0.1 mu m contact metallization with SiH/sub 2/F/sub 2/-reduced CVD W","authors":"N. Yokoyama, S. Kumura, T. Yoshimura, H. Goto, N. Kobayashi, Y. Homma, E. Takeda","doi":"10.1109/VLSIT.1992.200648","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200648","url":null,"abstract":"The fabrication of fine contact metallization down to 0.08 mu m in diameter for future 0.1- mu m-level ULSIs is discussed, and the electrical characteristics are evaluated. A two-layered etch mask, PMMA/poly-Si, was used for electron-beam delineation. Low-temperature dry etching permits the accurate patterning of the poly-Si layer in accordance with the PMMA mask, by increasing the PMMA etch-rate selectivity from 0.63 in ordinary dry etching to 15. Contact holes as small as 0.08 mu m in diameter are opened following application of the poly-Si as a mask. The combination of SiH/sub 2/F/sub 2/-reduced blanket CVD W (0.2 mu m thick)/sputtered W (30 nm thick) is used for metallization. Typical resistances are 1.5 k Omega on a 0.13- mu m-diameter contact to p/sup +/-Si and 107 Omega on a 0.18- mu m-diameter contact to n/sup +/-Si. Contact resistivities of these 0.1- mu m-level contacts are of the same levels as those of holes with diameters larger than 0.25 mu m.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122056514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200643
T. Onai, K. Nakazato, Y. Kiyota, T. Nakamura
It is shown that in the fully radiative current path structure (FRACS) transistor the maximum cutoff frequency (f/sub T/) is enhanced by the equivalent drift field induced in the base by the radiative diffusion current from a small emitter-base (E-B) junction to a large collector-base (C-B) junction. The f/sub T/ can be increased by reducing the emitter size as well as by reducing the base width. Theoretical analysis and experimental results show that the f/sub T/ is enhanced as the emitter becomes smaller. FRACS is thus a suitable structure for future sub-0.1- mu m emitter transistors.<>
{"title":"FRACS (fully radiative current path structure)-A high speed bipolar transistor with sub-0.1 mu m emitter","authors":"T. Onai, K. Nakazato, Y. Kiyota, T. Nakamura","doi":"10.1109/VLSIT.1992.200643","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200643","url":null,"abstract":"It is shown that in the fully radiative current path structure (FRACS) transistor the maximum cutoff frequency (f/sub T/) is enhanced by the equivalent drift field induced in the base by the radiative diffusion current from a small emitter-base (E-B) junction to a large collector-base (C-B) junction. The f/sub T/ can be increased by reducing the emitter size as well as by reducing the base width. Theoretical analysis and experimental results show that the f/sub T/ is enhanced as the emitter becomes smaller. FRACS is thus a suitable structure for future sub-0.1- mu m emitter transistors.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124091719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200676
R. Pease, G. Owen, R. Hsieh, A. Grenville, R. V. von Bunau, N. Maluf
A mostly reflective approach to 0.25- mu m lithography that has great simplicity (only two or three critical optical elements) and outstanding performance is described. A 1/6 scale prototype system has demonstrated 0.25- mu m resolution in a commercially available resist using a conventional mask, and 0.125- mu m resolution using a phase-shifting mask. The approach is particularly amenable to depth of focus enhancement by aperture apodization, and a fundamental trade-off inherent in this technique is described.<>
{"title":"Lithography for 0.25 mu m and below using simple high-performance optics","authors":"R. Pease, G. Owen, R. Hsieh, A. Grenville, R. V. von Bunau, N. Maluf","doi":"10.1109/VLSIT.1992.200676","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200676","url":null,"abstract":"A mostly reflective approach to 0.25- mu m lithography that has great simplicity (only two or three critical optical elements) and outstanding performance is described. A 1/6 scale prototype system has demonstrated 0.25- mu m resolution in a commercially available resist using a conventional mask, and 0.125- mu m resolution using a phase-shifting mask. The approach is particularly amenable to depth of focus enhancement by aperture apodization, and a fundamental trade-off inherent in this technique is described.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124459798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200629
R. Doering
It is pointed out that one of the most significant trends in semiconductor manufacturing over the past three decades has been the gradual replacement of batch processing with single-wafer processing. Two other trends, the use of larger silicon wafers (to reduce manufacturing cost) and the necessity for more demanding process-performance specifications (to allow continued device circuit scaling), have driven this move to single-wafer equipment for many processes. It is now technically feasible to produce silicon integrated circuits with 100% single-wafer processing. In the next decade, it may also become economically feasible to do so.<>
{"title":"Trends in single-wafer processing","authors":"R. Doering","doi":"10.1109/VLSIT.1992.200629","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200629","url":null,"abstract":"It is pointed out that one of the most significant trends in semiconductor manufacturing over the past three decades has been the gradual replacement of batch processing with single-wafer processing. Two other trends, the use of larger silicon wafers (to reduce manufacturing cost) and the necessity for more demanding process-performance specifications (to allow continued device circuit scaling), have driven this move to single-wafer equipment for many processes. It is now technically feasible to produce silicon integrated circuits with 100% single-wafer processing. In the next decade, it may also become economically feasible to do so.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114240595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200651
H. Nishimura, T. Yamada, R. Sinclair, S. Ogawa
A technology using Al-Si-Cu alloy high-temperature sputter filling and a thin Ti underlayer to prevent Si from precipitating is discussed. Complete filling of a 0.15- mu m-diameter via with aspect ratio of 4.5 has been achieved. The resistance of the 0.3- mu m sputter filled via was 0.71 Omega . This is about one order of magnitude lower than that for a conventional via. The electromigration resistance of the 0.3- mu m filled via was found to be four orders of magnitude greater than that of the conventional vias. Superior stress-induced migration resistance of 0.5- mu m wide lines was confirmed.<>
{"title":"A highly reliable sub-half-micron via and interconnect technology using Al alloy high-temperature sputter filling","authors":"H. Nishimura, T. Yamada, R. Sinclair, S. Ogawa","doi":"10.1109/VLSIT.1992.200651","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200651","url":null,"abstract":"A technology using Al-Si-Cu alloy high-temperature sputter filling and a thin Ti underlayer to prevent Si from precipitating is discussed. Complete filling of a 0.15- mu m-diameter via with aspect ratio of 4.5 has been achieved. The resistance of the 0.3- mu m sputter filled via was 0.71 Omega . This is about one order of magnitude lower than that for a conventional via. The electromigration resistance of the 0.3- mu m filled via was found to be four orders of magnitude greater than that of the conventional vias. Superior stress-induced migration resistance of 0.5- mu m wide lines was confirmed.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127430984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200641
M. Moslehi, L. Velo, H. Najm, T. Breedijk, B. Dostalik
An integrated sensor system for conductive layer deposition process control is presented. The process equipment employs a multizone illuminator and noninvasive sensors for dynamic process uniformity control, real-time process and end-pointing, and process diagnosis. Various modes of sensor fusion have been implemented for improved equipment/process performance. Several noninvasive in situ sensors developed and integrated in a rapid thermal chemical-vapor-deposition (CVD) system for CVD tungsten (CVD-W) process control and diagnosis are presented.<>
{"title":"Sensor fusion for ULSI manufacturing process control","authors":"M. Moslehi, L. Velo, H. Najm, T. Breedijk, B. Dostalik","doi":"10.1109/VLSIT.1992.200641","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200641","url":null,"abstract":"An integrated sensor system for conductive layer deposition process control is presented. The process equipment employs a multizone illuminator and noninvasive sensors for dynamic process uniformity control, real-time process and end-pointing, and process diagnosis. Various modes of sensor fusion have been implemented for improved equipment/process performance. Several noninvasive in situ sensors developed and integrated in a rapid thermal chemical-vapor-deposition (CVD) system for CVD tungsten (CVD-W) process control and diagnosis are presented.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122579521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200626
T. Ohmi, J. Takano, T. Tsuga, M. Kogure, S. Aoyama, K. Matsumoto, Kanjuro MAKIHARA
It is pointed out that the surface microhardness dominating the electrical properties of very thin oxide films is strictly influenced by the wafer quality. The increase of the surface microhardness in some processes is shown to depend strongly on the silicon vacancy cluster concentration in the wafer. An epitaxial wafer having low silicon vacancy concentration is superior for sub-half-micron ULSI devices.<>
{"title":"Wafer quality specification for future sub-half-micron ULSI devices","authors":"T. Ohmi, J. Takano, T. Tsuga, M. Kogure, S. Aoyama, K. Matsumoto, Kanjuro MAKIHARA","doi":"10.1109/VLSIT.1992.200626","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200626","url":null,"abstract":"It is pointed out that the surface microhardness dominating the electrical properties of very thin oxide films is strictly influenced by the wafer quality. The increase of the surface microhardness in some processes is shown to depend strongly on the silicon vacancy cluster concentration in the wafer. An epitaxial wafer having low silicon vacancy concentration is superior for sub-half-micron ULSI devices.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133852572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200632
T. Maeda, H. Gojohbori, K. Inoue, K. Ishimaru, A. Suzuki, H. Kato, M. Kakumu
A high-performance 0.5- mu m BiCMOS technology for 4-Mb BiCMOS SRAM for low-voltage operation is discussed. 1.5* performance improvement and low power relative to 0.8- mu m BiCMOS technology are achieved with reduced operation of 3.3 V. In particular, although power-supply voltage is reduced, none of device performance is so severe as to constrain the feasibility of a 0.5- mu m and below BiCMOS technology even for a high-density 4-Mb SRAM. A 16-b 4-Mb BiCMOS SRAM was fabricated to prove the developed 0.5- mu m BiCMOS technology combined with a quadruple poly Si and double Al process. The cell size is 3.5 mu m*5.7 mu m, and the chip size is 8.7mm*18.8 mm. Parametric testing of the 4-Mb BiCMOS SRAM confirmed the expected 9-ns access time at 3.3-V operation. Moreover, the total power dissipation can be managed below 500 mW, which is available for plastic packaging.<>
讨论了一种用于低压工作的4mb BiCMOS SRAM的高性能0.5 μ m BiCMOS技术。与0.8 μ m BiCMOS技术相比，在降低3.3 V电压的情况下实现了1.5*的性能提升和低功耗。特别是，虽然电源电压降低了，但器件性能没有严重到限制0.5 μ m及以下BiCMOS技术的可行性，即使是高密度的4mb SRAM。为了验证所开发的0.5 μ m BiCMOS技术与四重多晶硅和双铝工艺的结合，制作了一个16-b 4mb的BiCMOS SRAM。电池尺寸为3.5 μ m*5.7 μ m，芯片尺寸为8.7mm*18.8 mm。4mb BiCMOS SRAM的参数测试证实了在3.3 v工作时预期的9 ns访问时间。此外，总功耗可控制在500 mW以下，可用于塑料包装。
{"title":"High performance BiCMOS technology design for sub-10 ns 4 Mbit BiCMOS SRAM with 3.3 V operation","authors":"T. Maeda, H. Gojohbori, K. Inoue, K. Ishimaru, A. Suzuki, H. Kato, M. Kakumu","doi":"10.1109/VLSIT.1992.200632","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200632","url":null,"abstract":"A high-performance 0.5- mu m BiCMOS technology for 4-Mb BiCMOS SRAM for low-voltage operation is discussed. 1.5* performance improvement and low power relative to 0.8- mu m BiCMOS technology are achieved with reduced operation of 3.3 V. In particular, although power-supply voltage is reduced, none of device performance is so severe as to constrain the feasibility of a 0.5- mu m and below BiCMOS technology even for a high-density 4-Mb SRAM. A 16-b 4-Mb BiCMOS SRAM was fabricated to prove the developed 0.5- mu m BiCMOS technology combined with a quadruple poly Si and double Al process. The cell size is 3.5 mu m*5.7 mu m, and the chip size is 8.7mm*18.8 mm. Parametric testing of the 4-Mb BiCMOS SRAM confirmed the expected 9-ns access time at 3.3-V operation. Moreover, the total power dissipation can be managed below 500 mW, which is available for plastic packaging.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114838760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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