Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200692
K. Washio, H. Shimamoto, T. Nakamura
An ultra-high-speed high-density self-aligned pump technology for complementary bipolar ULSIs which is fully compatible with the npn process is discussed. A low sheet-resistance p/sup +/ buried layer and an extrinsic n/sup +/ polysilicon layer with U-grooved isolation enable the transistor size to be scaled down to about 20 mu m/sup 2/. A shallow emitter junction depth of 45 nm and narrow base width of 30 nm improve maximum cutoff frequency to 35 GHz. The power dissipation of a pnp pull-down complementary emitter-follower ECL circuit for the loaded case is calculated to be reduced to 1/5 compared with the conventional ECL circuit.<>
{"title":"A 35-GHz 20- mu m/sup 2/ self-aligned PNP technology for ultra-high-speed high-density complementary bipolar ULSIs","authors":"K. Washio, H. Shimamoto, T. Nakamura","doi":"10.1109/VLSIT.1992.200692","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200692","url":null,"abstract":"An ultra-high-speed high-density self-aligned pump technology for complementary bipolar ULSIs which is fully compatible with the npn process is discussed. A low sheet-resistance p/sup +/ buried layer and an extrinsic n/sup +/ polysilicon layer with U-grooved isolation enable the transistor size to be scaled down to about 20 mu m/sup 2/. A shallow emitter junction depth of 45 nm and narrow base width of 30 nm improve maximum cutoff frequency to 35 GHz. The power dissipation of a pnp pull-down complementary emitter-follower ECL circuit for the loaded case is calculated to be reduced to 1/5 compared with the conventional ECL circuit.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124881798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200621
M. Nakano, N. Shinmura, K. Iguchi, T. Watanabe, K. Sakiyama
An integrated process, composed of a vapor HF processor, a wafer carrier box with N/sub 2/ flow, and an SiN LPCVD system with N/sub 2/ flow load-lock, for realizing native-oxide free SiN formation is discussed. It has been found that an ON film having the equivalent oxide thickness of 4 nm can be obtained and further improvement may be possible. Therefore, it is expected to be a promising technology for the 64-Mb DRAM and beyond.<>
{"title":"A native-oxide-free process for 4 nm capacitor dielectrics","authors":"M. Nakano, N. Shinmura, K. Iguchi, T. Watanabe, K. Sakiyama","doi":"10.1109/VLSIT.1992.200621","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200621","url":null,"abstract":"An integrated process, composed of a vapor HF processor, a wafer carrier box with N/sub 2/ flow, and an SiN LPCVD system with N/sub 2/ flow load-lock, for realizing native-oxide free SiN formation is discussed. It has been found that an ON film having the equivalent oxide thickness of 4 nm can be obtained and further improvement may be possible. Therefore, it is expected to be a promising technology for the 64-Mb DRAM and beyond.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123305160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200634
F. Hayashi, M. Kitakata
A 0.4- mu m polysilicon TFT with I/sub on/ of 5 mu A and I/sub off/ of 10 fA developed by use of the LDO (lightly doped offset) structure and RTA (rapid thermal annealing) and plasma hydrogenation treatment is discussed. These technologies have proved to be essential in realizing high-performance deep submicron TFTs. Highly stable and low-power SRAMs of 16 Mb and beyond can be realized by employing these technologies. Models and mechanisms to explain the effects of various treatments on the performances of the TFTs are proposed.<>
{"title":"A high performance polysilicon TFT using RTA and plasma hydrogenation applicable to highly stable SRAMs of 16 Mbit and beyond","authors":"F. Hayashi, M. Kitakata","doi":"10.1109/VLSIT.1992.200634","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200634","url":null,"abstract":"A 0.4- mu m polysilicon TFT with I/sub on/ of 5 mu A and I/sub off/ of 10 fA developed by use of the LDO (lightly doped offset) structure and RTA (rapid thermal annealing) and plasma hydrogenation treatment is discussed. These technologies have proved to be essential in realizing high-performance deep submicron TFTs. Highly stable and low-power SRAMs of 16 Mb and beyond can be realized by employing these technologies. Models and mechanisms to explain the effects of various treatments on the performances of the TFTs are proposed.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124695081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200665
N. Shimoyama, K. Machida, K. Murase, T. Tsuchiya
The effect of water and/or silanols in TEOS/O/sub 3/-oxide on hot-carrier degradation is discussed. Hot-carrier degradation in MOSFETs is a serious problem as the thickness of the TEOS/O/sub 3/-oxide interlayer dielectric increases. This results mainly from enhanced hot-electron trapping and also from interface-trap generation, which are related to water and/or silanols in TEOS/O/sub 3/-oxide diffusing into the gate oxide. It is pointed out that by applying an ECR (electron cyclotron resonance) SiO/sub 2/ layer under the TEOS/O/sub 3/-oxide layer, tolerance against hot-carrier damage is improved to the level of MOSFETs without the TEOS/O/sub 3/-oxide layer.<>
{"title":"Enhanced hot-carrier degradation due to water in TEOS/O/sub 3/-oxide and water blocking effect of ECR-SiO/sub 2/","authors":"N. Shimoyama, K. Machida, K. Murase, T. Tsuchiya","doi":"10.1109/VLSIT.1992.200665","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200665","url":null,"abstract":"The effect of water and/or silanols in TEOS/O/sub 3/-oxide on hot-carrier degradation is discussed. Hot-carrier degradation in MOSFETs is a serious problem as the thickness of the TEOS/O/sub 3/-oxide interlayer dielectric increases. This results mainly from enhanced hot-electron trapping and also from interface-trap generation, which are related to water and/or silanols in TEOS/O/sub 3/-oxide diffusing into the gate oxide. It is pointed out that by applying an ECR (electron cyclotron resonance) SiO/sub 2/ layer under the TEOS/O/sub 3/-oxide layer, tolerance against hot-carrier damage is improved to the level of MOSFETs without the TEOS/O/sub 3/-oxide layer.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115808998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200637
G. J. Hu, L. Tran, P. Keshtbod, J. Segal, K. Park, T. Amin, B. Prickett, S.C. Tsao, J. Yen, E. Smith, J. Bornstein, A. Alvarez
An advanced BiCMOS floating gate avalanche MOS (BiFAMOS) technology for high-speed and high-density EPROM applications is described. It is of great interest to develop chips with access times of 20 ns or less to support 33-to-50-MHz systems without a SRAM interface. Since channel hot carrier injection is used in EPROM programming, the high-current and high-voltage programming conditions limit the size of the FET that can be used in the cell and hence the low cell current directly affects speed. A two-transistor cell has been previously introduced to overcome this speed limitation but at the expense of area. Here, BiCMOS technology is used to alleviate this speed/area tradeoff. Fast bipolar sense amplifiers and high-current NPN drivers allow very-high-speed access without a large cell current. With a 1-T cell, an access time of 12 ns was obtained on a 1-Mb EPROM, demonstrating that this 0.8- mu m BiFAMOS is capable of sub-20-ns 4M EPROMs.<>
{"title":"BiFAMOS technology for high speed mega-bit EPROMs","authors":"G. J. Hu, L. Tran, P. Keshtbod, J. Segal, K. Park, T. Amin, B. Prickett, S.C. Tsao, J. Yen, E. Smith, J. Bornstein, A. Alvarez","doi":"10.1109/VLSIT.1992.200637","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200637","url":null,"abstract":"An advanced BiCMOS floating gate avalanche MOS (BiFAMOS) technology for high-speed and high-density EPROM applications is described. It is of great interest to develop chips with access times of 20 ns or less to support 33-to-50-MHz systems without a SRAM interface. Since channel hot carrier injection is used in EPROM programming, the high-current and high-voltage programming conditions limit the size of the FET that can be used in the cell and hence the low cell current directly affects speed. A two-transistor cell has been previously introduced to overcome this speed limitation but at the expense of area. Here, BiCMOS technology is used to alleviate this speed/area tradeoff. Fast bipolar sense amplifiers and high-current NPN drivers allow very-high-speed access without a large cell current. With a 1-T cell, an access time of 12 ns was obtained on a 1-Mb EPROM, demonstrating that this 0.8- mu m BiFAMOS is capable of sub-20-ns 4M EPROMs.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126101560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200618
K. Sagara, T. Kure, S. Shukuri, J. Yugami, N. Hasegawa, H. Shinriki, H. Goto, H. Yamashita, E. Takeda
A recessed stacked capacitor (RSTC) structure to achieve both fine-pattern delineation and high cell capacitance is presented. Using a RSTC structure, an experimental memory array with 0.25 mu m phase-shift lithography and CVD-W plate technology has been fabricated. A 25-fF/cell capacitance was obtained in a 0.72 mu m/sup 2/ cell.<>
{"title":"A 0.72 mu m/sup 2/ recessed STC (RSTC) technology for 256 Mbit DRAMs using quarter-micron phase-shift lithography","authors":"K. Sagara, T. Kure, S. Shukuri, J. Yugami, N. Hasegawa, H. Shinriki, H. Goto, H. Yamashita, E. Takeda","doi":"10.1109/VLSIT.1992.200618","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200618","url":null,"abstract":"A recessed stacked capacitor (RSTC) structure to achieve both fine-pattern delineation and high cell capacitance is presented. Using a RSTC structure, an experimental memory array with 0.25 mu m phase-shift lithography and CVD-W plate technology has been fabricated. A 25-fF/cell capacitance was obtained in a 0.72 mu m/sup 2/ cell.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125892630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200619
J. Ahn, Y.W. Park, J. Shin, S.T. Kim, S. Shim, S. Nam, W.M. Park, H. Shin, C. Choi, K.T. Kim, D. Chin, O. Kwon, C. Hwang
Micro villus patterning (MVP) technology which delivers the maximized cell capacitance is discussed. The key feature of the MVP technology is the formation of a hemispherical grain (HSG) archipelago and its transference to the underlayered oxide. The HSG archipelago pattern is produced on the oxide layer, and, by using that pattern as an etch mask, the oxide archipelago pattern is again transferred to the storage poly for the formation of villus bars by anisotropic dry etch. After the etching process, the oxide etch mask pattern is stripped away by using oxide wet etchant, so that additional Fin undercut structure is achieved underneath the main body. The main body of the storage electrode can be formed by single deposition and etch process, so that the storage electrode structure is strong enough to maintain its physical stability in spite of the complication of its shape. A 256-Mb DRAM-cell size of 0.6 approximately 0.8 mu m/sup 2/ having more than 30 fF of cell capacitance with a stack structure, has been realized.<>
讨论了微绒毛图像化(MVP)技术，该技术提供了最大的电池电容。MVP技术的关键特点是形成半球形颗粒(HSG)群岛，并将其转移到下层氧化物中。HSG群岛图案在氧化层上产生，并且，通过使用该图案作为蚀刻掩膜，氧化物群岛图案再次转移到存储聚体上，通过各向异性干蚀刻形成绒毛棒。在蚀刻过程结束后，使用氧化物湿式蚀刻将氧化物蚀刻掩模图案剥离，从而在主体下方实现额外的翅片凹边结构。存储电极的主体可以通过一次沉积和蚀刻工艺形成，使得存储电极结构足够坚固，尽管其形状复杂，但仍能保持其物理稳定性。已经实现了256 mb的dram单元尺寸为0.6(约0.8 mu m/sup 2)，具有超过30ff的堆叠结构单元电容。
{"title":"Micro villus patterning (MVP) technology for 256 Mb DRAM stack cell","authors":"J. Ahn, Y.W. Park, J. Shin, S.T. Kim, S. Shim, S. Nam, W.M. Park, H. Shin, C. Choi, K.T. Kim, D. Chin, O. Kwon, C. Hwang","doi":"10.1109/VLSIT.1992.200619","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200619","url":null,"abstract":"Micro villus patterning (MVP) technology which delivers the maximized cell capacitance is discussed. The key feature of the MVP technology is the formation of a hemispherical grain (HSG) archipelago and its transference to the underlayered oxide. The HSG archipelago pattern is produced on the oxide layer, and, by using that pattern as an etch mask, the oxide archipelago pattern is again transferred to the storage poly for the formation of villus bars by anisotropic dry etch. After the etching process, the oxide etch mask pattern is stripped away by using oxide wet etchant, so that additional Fin undercut structure is achieved underneath the main body. The main body of the storage electrode can be formed by single deposition and etch process, so that the storage electrode structure is strong enough to maintain its physical stability in spite of the complication of its shape. A 256-Mb DRAM-cell size of 0.6 approximately 0.8 mu m/sup 2/ having more than 30 fF of cell capacitance with a stack structure, has been realized.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"176 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134162747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200662
T. Horiuchi, T. Homma, Y. Murao, K. Okumura
It is shown that a 45% on-current increase can be achieved for an MOSFET without sacrificing hot carrier immunity by applying an asymmetric LDD sidewall spacer technology. The asymmetric spacer is fabricated by using a selective oxide deposition technique, which gives a wide design feasibility of implementing asymmetric structures in the CMOS process. The process requires no additional masking steps and is independent of wafer orientation. Based on an optimized asymmetric LDD design, 5-V operation of a 0.45- mu m nMOSFET is demonstrated. A simple on-current model for asymmetric LDD is also presented.<>
结果表明，在不牺牲热载流子抗扰度的情况下，应用非对称LDD侧壁间隔技术可以使MOSFET的导通电流增加45%。采用选择性氧化沉积技术制备了非对称间隔层，为在CMOS工艺中实现非对称结构提供了广泛的设计可行性。该工艺不需要额外的掩蔽步骤，并且与晶圆方向无关。基于优化的非对称LDD设计，演示了0.45 μ m nMOSFET的5v工作。本文还提出了一种简单的非对称LDD导通电流模型。
{"title":"A high performance asymmetric LDD MOSFET using selective oxide deposition technique","authors":"T. Horiuchi, T. Homma, Y. Murao, K. Okumura","doi":"10.1109/VLSIT.1992.200662","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200662","url":null,"abstract":"It is shown that a 45% on-current increase can be achieved for an MOSFET without sacrificing hot carrier immunity by applying an asymmetric LDD sidewall spacer technology. The asymmetric spacer is fabricated by using a selective oxide deposition technique, which gives a wide design feasibility of implementing asymmetric structures in the CMOS process. The process requires no additional masking steps and is independent of wafer orientation. Based on an optimized asymmetric LDD design, 5-V operation of a 0.45- mu m nMOSFET is demonstrated. A simple on-current model for asymmetric LDD is also presented.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132040457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200650
T. Rucker, N. Mencinger, V. Murali, K. Regis, R. Shukla, R. Sundahl, B. Siu
A high-performance microprocessor and cache core based on a silicon-on-silicon multichip module technology is discussed. The technology was designed to have low interconnect parasitics and low cost. A 12-chip module operating at over 75 MHz using this technology was built incorporating an i486 microprocessor, a cache controller, and 256 K of SRAM cache. This represents a 40-50% clock rate improvement over a conventional packaged part approach. The dice were attached to a four-layer metal and polyimide silicon substrate using controlled collapse chip connection (C4) technology. The unit was assembled into a 350 pin ceramic pin grid array (PGA) package. A low-dielectric-constant polyimide and a flip chip die interconnection process minimized RC delay and inductance, and the module can operate at over 160 MHz. The module can dissipate up to 20 W using an array of thermal bumps spaced over the die surface and attached to staircase vias through the substrate.<>
{"title":"A high performance Si on Si multichip module technology","authors":"T. Rucker, N. Mencinger, V. Murali, K. Regis, R. Shukla, R. Sundahl, B. Siu","doi":"10.1109/VLSIT.1992.200650","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200650","url":null,"abstract":"A high-performance microprocessor and cache core based on a silicon-on-silicon multichip module technology is discussed. The technology was designed to have low interconnect parasitics and low cost. A 12-chip module operating at over 75 MHz using this technology was built incorporating an i486 microprocessor, a cache controller, and 256 K of SRAM cache. This represents a 40-50% clock rate improvement over a conventional packaged part approach. The dice were attached to a four-layer metal and polyimide silicon substrate using controlled collapse chip connection (C4) technology. The unit was assembled into a 350 pin ceramic pin grid array (PGA) package. A low-dielectric-constant polyimide and a flip chip die interconnection process minimized RC delay and inductance, and the module can operate at over 160 MHz. The module can dissipate up to 20 W using an array of thermal bumps spaced over the die surface and attached to staircase vias through the substrate.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122229966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200643
T. Onai, K. Nakazato, Y. Kiyota, T. Nakamura
It is shown that in the fully radiative current path structure (FRACS) transistor the maximum cutoff frequency (f/sub T/) is enhanced by the equivalent drift field induced in the base by the radiative diffusion current from a small emitter-base (E-B) junction to a large collector-base (C-B) junction. The f/sub T/ can be increased by reducing the emitter size as well as by reducing the base width. Theoretical analysis and experimental results show that the f/sub T/ is enhanced as the emitter becomes smaller. FRACS is thus a suitable structure for future sub-0.1- mu m emitter transistors.<>
{"title":"FRACS (fully radiative current path structure)-A high speed bipolar transistor with sub-0.1 mu m emitter","authors":"T. Onai, K. Nakazato, Y. Kiyota, T. Nakamura","doi":"10.1109/VLSIT.1992.200643","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200643","url":null,"abstract":"It is shown that in the fully radiative current path structure (FRACS) transistor the maximum cutoff frequency (f/sub T/) is enhanced by the equivalent drift field induced in the base by the radiative diffusion current from a small emitter-base (E-B) junction to a large collector-base (C-B) junction. The f/sub T/ can be increased by reducing the emitter size as well as by reducing the base width. Theoretical analysis and experimental results show that the f/sub T/ is enhanced as the emitter becomes smaller. FRACS is thus a suitable structure for future sub-0.1- mu m emitter transistors.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124091719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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