Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200640
T. Kure, Y. Gotoh, H. Kawakami, S. Tachi
Anisotropic etching which can be performed effectively with a low-pressure and high-density plasma may sometimes produce nonuniform patterns. Such a phenomenon has been observed in Si trench etching and poly-Si etching. Although this phenomenon is thought to be based on the local electric field, the mechanism for its generation is not clear. The nonuniformity of the ion direction, which is a serious problem in the fabrication of higher-packing-density patterns of future ULSIs such as 256 M DRAMs is considered. Time-modulated (TM) etching based on a model featuring pattern-plasma interaction is also discussed. It was found that peripheral patterns are inclined by the local electric field generated by the secondary electron effect. Using TM etching with an alternately supplied bias, such nonuniformity was reduced, and quarter-micron-level anisotropic etching of dense Si patterns was achieved.<>
各向异性刻蚀可以在低压和高密度等离子体中有效地进行，但有时会产生不均匀的图案。这种现象在硅沟槽刻蚀和多晶硅刻蚀中都有观察到。虽然这种现象被认为是基于局部电场，但其产生的机制尚不清楚。离子方向的不均匀性，这是一个严重的问题，在制造更高的封装密度的未来ulsi，如256 M dram。本文还讨论了基于模式-等离子体相互作用模型的时间调制蚀刻。发现二次电子效应所产生的局域电场使外围图案发生倾斜。采用交替提供偏压的TM蚀刻，这种不均匀性得到了降低，并实现了四分之一微米级的致密硅图案的各向异性蚀刻。
{"title":"Highly anisotropic microwave plasma etching for high packing density silicon patterns","authors":"T. Kure, Y. Gotoh, H. Kawakami, S. Tachi","doi":"10.1109/VLSIT.1992.200640","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200640","url":null,"abstract":"Anisotropic etching which can be performed effectively with a low-pressure and high-density plasma may sometimes produce nonuniform patterns. Such a phenomenon has been observed in Si trench etching and poly-Si etching. Although this phenomenon is thought to be based on the local electric field, the mechanism for its generation is not clear. The nonuniformity of the ion direction, which is a serious problem in the fabrication of higher-packing-density patterns of future ULSIs such as 256 M DRAMs is considered. Time-modulated (TM) etching based on a model featuring pattern-plasma interaction is also discussed. It was found that peripheral patterns are inclined by the local electric field generated by the secondary electron effect. Using TM etching with an alternately supplied bias, such nonuniformity was reduced, and quarter-micron-level anisotropic etching of dense Si patterns was achieved.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125193950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200625
S. Verhaverbeke, M. Meuris, M. Schaekers, L. Haspeslagh, P. Mertens, M. Heyns, R. de Blank, A. Philipossian
A cleaning mixture which consists of HF with minute amounts of IPA added is discussed. This solution prevents the deposition of particles on the Si surface during HF-dipping and subsequent deionized-water rinsing and does not change the chemical state of the surface significantly. The characteristics of a thin gate oxide grown after this treatment show a markedly improved performance over the standard HF-last or RCA-cleaned samples. The addition of IPA to the HF mixture gives electrical breakdown results which are comparable to or better than the best results for HF-last samples. This demonstrates that the physisorbed IPA poses no problem for the gate oxide growth. It was observed that the contact angle directly correlates with the gate oxide yield. It is, therefore, a very powerful and fast technique for characterizing the Si surface after various treatments.<>
{"title":"A new modified HF-last cleaning process for high-performance gate dielectrics","authors":"S. Verhaverbeke, M. Meuris, M. Schaekers, L. Haspeslagh, P. Mertens, M. Heyns, R. de Blank, A. Philipossian","doi":"10.1109/VLSIT.1992.200625","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200625","url":null,"abstract":"A cleaning mixture which consists of HF with minute amounts of IPA added is discussed. This solution prevents the deposition of particles on the Si surface during HF-dipping and subsequent deionized-water rinsing and does not change the chemical state of the surface significantly. The characteristics of a thin gate oxide grown after this treatment show a markedly improved performance over the standard HF-last or RCA-cleaned samples. The addition of IPA to the HF mixture gives electrical breakdown results which are comparable to or better than the best results for HF-last samples. This demonstrates that the physisorbed IPA poses no problem for the gate oxide growth. It was observed that the contact angle directly correlates with the gate oxide yield. It is, therefore, a very powerful and fast technique for characterizing the Si surface after various treatments.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130339667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200668
K. Macwilliams, L. Lowry, D. Swanson, J. Scarpulla
It is pointed out that wafer-mapping of physical stresses by X-ray diffraction of a silicided CMOS process shows regions of both very high and low stress levels. The regions of high stress consistently have increased subthreshold slopes and are much more sensitive to hot-carrier induced threshold voltage shifts. Hot carrier lifetime variations over two orders of magnitude are explicitly shown to correlate with the physical stress level within a given highly stressed wafer. To optimally deliver maximum device performance with high reliability, it is essential that physical stress levels be measured, understood, and minimized.<>
{"title":"Wafer-mapping of hot carrier lifetime due to physical stress effects (MOSFET)","authors":"K. Macwilliams, L. Lowry, D. Swanson, J. Scarpulla","doi":"10.1109/VLSIT.1992.200668","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200668","url":null,"abstract":"It is pointed out that wafer-mapping of physical stresses by X-ray diffraction of a silicided CMOS process shows regions of both very high and low stress levels. The regions of high stress consistently have increased subthreshold slopes and are much more sensitive to hot-carrier induced threshold voltage shifts. Hot carrier lifetime variations over two orders of magnitude are explicitly shown to correlate with the physical stress level within a given highly stressed wafer. To optimally deliver maximum device performance with high reliability, it is essential that physical stress levels be measured, understood, and minimized.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122073776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200646
F. Sato, T. Hashimoto, T. Tashiro, T. Tatsumi, M. Hiroi, T. Niino
A selective epitaxial growth (SEG) technology using Si/sub 2/H/sub 6/+GeH/sub 4/+Cl/sub 2/ under cold-wall ultra-high-vacuum (UHV)/CVD conditions is described. By using this technology, a self-aligned SiGe HBT with selective epitaxial base is realized. This technology also makes possible the void-free selective growth of SiGe/Si epitaxial layers on Si under polysilicon with overhanging structure, as well as on the open region. As for the transistor characteristics, h/sub FE/ of 100 and BV/sub CEO/ of 5.0 V were obtained.<>
{"title":"A novel selective SiGe epitaxial growth technology for self-aligned HBTs","authors":"F. Sato, T. Hashimoto, T. Tashiro, T. Tatsumi, M. Hiroi, T. Niino","doi":"10.1109/VLSIT.1992.200646","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200646","url":null,"abstract":"A selective epitaxial growth (SEG) technology using Si/sub 2/H/sub 6/+GeH/sub 4/+Cl/sub 2/ under cold-wall ultra-high-vacuum (UHV)/CVD conditions is described. By using this technology, a self-aligned SiGe HBT with selective epitaxial base is realized. This technology also makes possible the void-free selective growth of SiGe/Si epitaxial layers on Si under polysilicon with overhanging structure, as well as on the open region. As for the transistor characteristics, h/sub FE/ of 100 and BV/sub CEO/ of 5.0 V were obtained.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132605174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200633
H. Honda, K. Uga, M. Ishida, Y. Ishigaki, J. Takahashi, T. Shiomi, S. Ohbayashi, Y. Kohno
The described technology uses a quintuple poly-Si and double-metal process architecture. The emitter and base of a bipolar transistor are self-aligned. The retrograde well for MOS transistors and the P isolation for bipolar transistors are formed by using high-energy ion implantation, while the concentration of the collector is determined by an N epitaxial layer only. As thick oxide remains at the base region before sidewall formation of MOS transistors, an ideal base current flows. The delay times of ECL, CMOS, and BiNMOS are 87 ps, 97 ps, and 130 ps, respectively. BiNMOS has a speed advantage over CMOS down to 2.5 V. A 5-ns 256 K (32 K*8) TTL SRAM has been fabricated with a 0.6- mu m BiCMOS SRAM technology.<>
{"title":"A high performance 0.6 mu m BiCMOS SRAM technology with emitter-base self-aligned bipolar transistors and retrograde well for MOS transistors","authors":"H. Honda, K. Uga, M. Ishida, Y. Ishigaki, J. Takahashi, T. Shiomi, S. Ohbayashi, Y. Kohno","doi":"10.1109/VLSIT.1992.200633","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200633","url":null,"abstract":"The described technology uses a quintuple poly-Si and double-metal process architecture. The emitter and base of a bipolar transistor are self-aligned. The retrograde well for MOS transistors and the P isolation for bipolar transistors are formed by using high-energy ion implantation, while the concentration of the collector is determined by an N epitaxial layer only. As thick oxide remains at the base region before sidewall formation of MOS transistors, an ideal base current flows. The delay times of ECL, CMOS, and BiNMOS are 87 ps, 97 ps, and 130 ps, respectively. BiNMOS has a speed advantage over CMOS down to 2.5 V. A 5-ns 256 K (32 K*8) TTL SRAM has been fabricated with a 0.6- mu m BiCMOS SRAM technology.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116630973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200631
T.M. Liu, G. Chin, M. Morris, D. Jeon, V. Archer, H.H. Kim, M. Cerullo, K.F. Lee, J. Sung, K. Lau, T. Chiu, A. Voshchenkov, R. Swartz
An ultra-high-speed half-micron non-overlapped super self-aligned BiCMOS technology that uses a silicon fillet self-aligned contact technology (SIFT) for both bipolar and MOS transistors is discussed. The SIFT process reduces the device capacitances and series resistances by minimizing the diffusion region area as well as the polysilicon electrode area. Deep trench isolation for bipolar transistors allows the device area to be much reduced for VLSI applications. The ECL gate delay is demonstrated to be 31 ps for devices with emitter polysilicon widths of 0.6 mu m. The CMOS ring oscillator gate delays are 58 ps for 0.5- mu m gate length and 67 ps for 0.6- mu m gate length at 5 V.<>
{"title":"An ultra high speed ECL-bipolar CMOS technology with silicon fillet self-aligned contacts","authors":"T.M. Liu, G. Chin, M. Morris, D. Jeon, V. Archer, H.H. Kim, M. Cerullo, K.F. Lee, J. Sung, K. Lau, T. Chiu, A. Voshchenkov, R. Swartz","doi":"10.1109/VLSIT.1992.200631","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200631","url":null,"abstract":"An ultra-high-speed half-micron non-overlapped super self-aligned BiCMOS technology that uses a silicon fillet self-aligned contact technology (SIFT) for both bipolar and MOS transistors is discussed. The SIFT process reduces the device capacitances and series resistances by minimizing the diffusion region area as well as the polysilicon electrode area. Deep trench isolation for bipolar transistors allows the device area to be much reduced for VLSI applications. The ECL gate delay is demonstrated to be 31 ps for devices with emitter polysilicon widths of 0.6 mu m. The CMOS ring oscillator gate delays are 58 ps for 0.5- mu m gate length and 67 ps for 0.6- mu m gate length at 5 V.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"15 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133357116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200645
C. Nguyen, S. Kuehne, S.S. Wong
Fabrication of bipolar transistors employing selective epitaxial growth (SEG) and chemo-mechanical polishing (CMP) is demonstrated. The SEG/CMP combination allows for lithography-limited isolation and results in inherently planar surfaces. The pedestal structure made possible by these technologies facilitates reduction of extrinsic base-collector capacitance and reduces the edge leakage common in SEG structures. The pedestals protect the SEG sidewalls from any potential contaminants or oxidation-induced stress during subsequent processing, and hence help eliminate any induced leakage.<>
{"title":"Single-poly bipolar transistor with selective epitaxial silicon and chemo-mechanical polishing","authors":"C. Nguyen, S. Kuehne, S.S. Wong","doi":"10.1109/VLSIT.1992.200645","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200645","url":null,"abstract":"Fabrication of bipolar transistors employing selective epitaxial growth (SEG) and chemo-mechanical polishing (CMP) is demonstrated. The SEG/CMP combination allows for lithography-limited isolation and results in inherently planar surfaces. The pedestal structure made possible by these technologies facilitates reduction of extrinsic base-collector capacitance and reduces the edge leakage common in SEG structures. The pedestals protect the SEG sidewalls from any potential contaminants or oxidation-induced stress during subsequent processing, and hence help eliminate any induced leakage.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116391940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200661
R. Yan, K. Lee, D. Jeon, Y.O. Kim, B. Park, M. Pinto, C. Rafferty, D. Tennant, E. Westerwick, G. Chin, M. Morris, K. Early, P. Mulgrew, W. Mansfield, R. Watts, A.M. Voshchenkov, J. Bokor, R. Swartz, A. Ourmazd
The design and implementation of 0.15- mu m-channel N-MOSFETs with very high current drive and good short channel behavior at room temperature are discussed. Measured subthreshold characteristics show a slope of 84 mV/dec and a shift for 75 mV for Delta V/sub ds/=1 V. A peak g/sub m/ of 570 mS/mm was recorded, leading to a unity-current-gain cutoff frequency (f/sub T/) of 89 GHz. Key process steps include the formation of 40-AA gate oxides and sub-500-AA junctions. Vertical doping engineering was used to minimize doping at the surface and beneath the junctions, while maintaining good turn-off characteristics.<>
{"title":"High performance 0.1- mu m room temperature Si MOSFETs","authors":"R. Yan, K. Lee, D. Jeon, Y.O. Kim, B. Park, M. Pinto, C. Rafferty, D. Tennant, E. Westerwick, G. Chin, M. Morris, K. Early, P. Mulgrew, W. Mansfield, R. Watts, A.M. Voshchenkov, J. Bokor, R. Swartz, A. Ourmazd","doi":"10.1109/VLSIT.1992.200661","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200661","url":null,"abstract":"The design and implementation of 0.15- mu m-channel N-MOSFETs with very high current drive and good short channel behavior at room temperature are discussed. Measured subthreshold characteristics show a slope of 84 mV/dec and a shift for 75 mV for Delta V/sub ds/=1 V. A peak g/sub m/ of 570 mS/mm was recorded, leading to a unity-current-gain cutoff frequency (f/sub T/) of 89 GHz. Key process steps include the formation of 40-AA gate oxides and sub-500-AA junctions. Vertical doping engineering was used to minimize doping at the surface and beneath the junctions, while maintaining good turn-off characteristics.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114960779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200664
A. Mazure, R. Subrahmanyan, C. Gunderson, M. Orlowski
Based on simulation and experimental work it is shown that the most important parameters are the LDD dose and the p/sup +/ source/drain junction depth, not the buried junction channel. It is also shown that buried channels can readily be scaled down to 0.2 mu m geometries by adjusting the source/drain construction. The design considerations presented are confirmed by fabricated 0.25- mu m-gate (L/sub eff/ approximately=0.19 mu m) buried p MOSFETs with off-leakage current below 1 pA/ mu m at V/sub G/=0 V, V/sub DS/=-3.3 V. In addition, it is shown that buried channels can readily be scaled down to 0.2- mu m geometries by adjusting the source/drain parameters while maintaining a reasonably high back-end thermal budget.<>
{"title":"Design considerations for sub-0.35 mu m buried channel P-MOSFET devices","authors":"A. Mazure, R. Subrahmanyan, C. Gunderson, M. Orlowski","doi":"10.1109/VLSIT.1992.200664","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200664","url":null,"abstract":"Based on simulation and experimental work it is shown that the most important parameters are the LDD dose and the p/sup +/ source/drain junction depth, not the buried junction channel. It is also shown that buried channels can readily be scaled down to 0.2 mu m geometries by adjusting the source/drain construction. The design considerations presented are confirmed by fabricated 0.25- mu m-gate (L/sub eff/ approximately=0.19 mu m) buried p MOSFETs with off-leakage current below 1 pA/ mu m at V/sub G/=0 V, V/sub DS/=-3.3 V. In addition, it is shown that buried channels can readily be scaled down to 0.2- mu m geometries by adjusting the source/drain parameters while maintaining a reasonably high back-end thermal budget.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133269363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200673
M. Endo, Y. Tani, T. Koizumi, S. Kobayashi, K. Yamashita, M. Sasago, N. Nomura
For quarter-micron KrF excimer laser lithography, a chemically amplified positive resist with high stability and process compatibility has been developed. 0.25- mu m line and space patterns and 0.35- mu m contact hole patterns have been obtained using this resist. The multiple interference effect due to reflection from air and substrate is reduced by using an overcoat film or antireflective coating. The overcoat film is made of a water-soluble polyvinylalcohol derivative. The refractive index of this polymer is 1.3, which is suitable for the resist (index
{"title":"Quarter micron KrF excimer laser lithography","authors":"M. Endo, Y. Tani, T. Koizumi, S. Kobayashi, K. Yamashita, M. Sasago, N. Nomura","doi":"10.1109/VLSIT.1992.200673","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200673","url":null,"abstract":"For quarter-micron KrF excimer laser lithography, a chemically amplified positive resist with high stability and process compatibility has been developed. 0.25- mu m line and space patterns and 0.35- mu m contact hole patterns have been obtained using this resist. The multiple interference effect due to reflection from air and substrate is reduced by using an overcoat film or antireflective coating. The overcoat film is made of a water-soluble polyvinylalcohol derivative. The refractive index of this polymer is 1.3, which is suitable for the resist (index","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125796871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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