Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200691
H. Takemura, C. Ogawa, M. Kurisu, G. Uemura, T. Morikawa, T. Tashiro
The development of a Si bipolar transistor with f/sub max/ (maximum frequency of oscillation) of 40 GHz by employing a process which independently optimizes the cutoff frequency (f/sub T/) and the base resistance (r/sub b/) is discussed. By using a A-BSA (advanced BSG self-aligned) technology, the resistance of the link region, the intermediate base region between the intrinsic and extrinsic ones, is controlled by the rediffusion from the BSG side wall to the link region. This process does not degrade f/sub T/. As a result, f/sub max/ of 40 GHz and f/sub T/ of 43 GHz are realized simultaneously. Using this transistor of 1/16 dynamic frequency divider that operates up to 35 GHz has been constructed. The application of Si bipolar transistors will extend to the millimeter-wave frequency region.<>
{"title":"A Si bipolar transistor with f/sub max/ of 40 GHz and its application to a 35 GHz 1/16 dynamic frequency divider","authors":"H. Takemura, C. Ogawa, M. Kurisu, G. Uemura, T. Morikawa, T. Tashiro","doi":"10.1109/VLSIT.1992.200691","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200691","url":null,"abstract":"The development of a Si bipolar transistor with f/sub max/ (maximum frequency of oscillation) of 40 GHz by employing a process which independently optimizes the cutoff frequency (f/sub T/) and the base resistance (r/sub b/) is discussed. By using a A-BSA (advanced BSG self-aligned) technology, the resistance of the link region, the intermediate base region between the intrinsic and extrinsic ones, is controlled by the rediffusion from the BSG side wall to the link region. This process does not degrade f/sub T/. As a result, f/sub max/ of 40 GHz and f/sub T/ of 43 GHz are realized simultaneously. Using this transistor of 1/16 dynamic frequency divider that operates up to 35 GHz has been constructed. The application of Si bipolar transistors will extend to the millimeter-wave frequency region.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114117732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200649
T. Iijima, A. Nishiyama, Y. Ushiku, T. Ohguro, I. Kunishima, K. Suguro, H. Iwai
A contact filling-technique that utilizes polysilicon plug formation followed by Ni silicidation with a TiN barrier at the polysilicon plug bottom is described. Self-aligned complete silicidation of both shallow and deep contacts can be achieved at the same time by using the TiN silicidation stop. By using this technique in place of a polysilicon plug, low contact resistance was achieved for both n/sup +/ and p/sup +/ contacts. A completely silicided plug for both shallow and deep contact holes can be achieved at the same time. The low leakage current of junction diodes and lack of transistor characteristic degradation when using the Ni silicide plug demonstrate the integrity of the technique.<>
{"title":"A novel selective Ni/sub 3/Si contact plug technique for deep-submicron ULSIs","authors":"T. Iijima, A. Nishiyama, Y. Ushiku, T. Ohguro, I. Kunishima, K. Suguro, H. Iwai","doi":"10.1109/VLSIT.1992.200649","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200649","url":null,"abstract":"A contact filling-technique that utilizes polysilicon plug formation followed by Ni silicidation with a TiN barrier at the polysilicon plug bottom is described. Self-aligned complete silicidation of both shallow and deep contacts can be achieved at the same time by using the TiN silicidation stop. By using this technique in place of a polysilicon plug, low contact resistance was achieved for both n/sup +/ and p/sup +/ contacts. A completely silicided plug for both shallow and deep contact holes can be achieved at the same time. The low leakage current of junction diodes and lack of transistor characteristic degradation when using the Ni silicide plug demonstrate the integrity of the technique.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"324 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120938678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200630
G. Shahidi, J. Warnock, B. Davari, B. Wu, Y. Taur, C. Wong, C. Chen, M. Rodriguez, D. Tang, K. Jenkins, P. McFarland, R. Schulz, D. Zicherman, P. Coane, D. Klaus, J. Sun, M. Polcari, T. Ning
In this technology, first the CMOS is defined and a major part of the heat cycle is carried out. Then, the bipolar is fabricated by the rest of the CMOS. Patterned subcollector definition and epitaxial silicon growth are followed by the deep and shallow trench isolation processes. Next are the npn collector reach-through and anneal, CMOS well and threshold implants, gate oxidation and poly deposition. CMOS gate definition, reoxidation, and nMOS n/sup +/ implant. Electron-beam lithography is used to pattern the gate level in order to achieve a minimum gate poly width of 0.3 mu m. Next, the CMOS region is protected, while fabricating the bipolar. The annealing cycles for base and emitter during the process are compatible with the CMOS requirements. The minimum final emitter size is 0.5 mu m. CMOS ring oscillators with 50-ps delay per stage at 2.5-V supply, ECL ring oscillator delays of 48 ps at 1.2 mA, and fast loaded BiNMOS gate delays have been achieved.<>
{"title":"A high performance BiCMOS technology using 0.25 mu m CMOS and double poly 47 GHz bipolar","authors":"G. Shahidi, J. Warnock, B. Davari, B. Wu, Y. Taur, C. Wong, C. Chen, M. Rodriguez, D. Tang, K. Jenkins, P. McFarland, R. Schulz, D. Zicherman, P. Coane, D. Klaus, J. Sun, M. Polcari, T. Ning","doi":"10.1109/VLSIT.1992.200630","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200630","url":null,"abstract":"In this technology, first the CMOS is defined and a major part of the heat cycle is carried out. Then, the bipolar is fabricated by the rest of the CMOS. Patterned subcollector definition and epitaxial silicon growth are followed by the deep and shallow trench isolation processes. Next are the npn collector reach-through and anneal, CMOS well and threshold implants, gate oxidation and poly deposition. CMOS gate definition, reoxidation, and nMOS n/sup +/ implant. Electron-beam lithography is used to pattern the gate level in order to achieve a minimum gate poly width of 0.3 mu m. Next, the CMOS region is protected, while fabricating the bipolar. The annealing cycles for base and emitter during the process are compatible with the CMOS requirements. The minimum final emitter size is 0.5 mu m. CMOS ring oscillators with 50-ps delay per stage at 2.5-V supply, ECL ring oscillator delays of 48 ps at 1.2 mA, and fast loaded BiNMOS gate delays have been achieved.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126963606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200670
T. Yamamoto, T. Mogami, K. Terada
A CMOS structure with a local well contact that allows the application of forward substrate bias for both p- and n-well with a single substrate supply is described. Higher driving capability and smaller short channel effects can be realized without device area increase. A propagation delay of 95 ps/stage at V/sub dd/=1.5 V and a temperature of 77 K was obtained with a 0.4- mu m gate length, which is about 1.5 times faster than that of the conventional CMOS structure.<>
{"title":"A new CMOS structure for low temperature operation with forward substrate bias","authors":"T. Yamamoto, T. Mogami, K. Terada","doi":"10.1109/VLSIT.1992.200670","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200670","url":null,"abstract":"A CMOS structure with a local well contact that allows the application of forward substrate bias for both p- and n-well with a single substrate supply is described. Higher driving capability and smaller short channel effects can be realized without device area increase. A propagation delay of 95 ps/stage at V/sub dd/=1.5 V and a temperature of 77 K was obtained with a 0.4- mu m gate length, which is about 1.5 times faster than that of the conventional CMOS structure.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126885431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200666
K. Shimokawa, T. Usami, S. Tokitou, N. Hirashita, M. Yoshimaru, M. Ino
The effects of absorbed water of spin-on glass (SOG) and tetraethylorthosilicate (TEOS)-O/sub 3/ NSG on MOS transistor hot carrier degradation were investigated. It was found that the absorbed water in SOG and TEOS-O/sub 3/ NSG film desorbs from the film during subsequent low temperature annealing and causes hot carrier degradation. It was also found that plasma CVD silicon oxide (P-SiO) deposited under certain conditions suppresses the hot carrier degradation drastically. Because the P-SiO film has a small water absorption rate, it blocks water penetration to the silicon surface.<>
{"title":"Suppression of the MOS transistor hot carrier degradation caused by water desorbed from intermetal dielectric","authors":"K. Shimokawa, T. Usami, S. Tokitou, N. Hirashita, M. Yoshimaru, M. Ino","doi":"10.1109/VLSIT.1992.200666","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200666","url":null,"abstract":"The effects of absorbed water of spin-on glass (SOG) and tetraethylorthosilicate (TEOS)-O/sub 3/ NSG on MOS transistor hot carrier degradation were investigated. It was found that the absorbed water in SOG and TEOS-O/sub 3/ NSG film desorbs from the film during subsequent low temperature annealing and causes hot carrier degradation. It was also found that plasma CVD silicon oxide (P-SiO) deposited under certain conditions suppresses the hot carrier degradation drastically. Because the P-SiO film has a small water absorption rate, it blocks water penetration to the silicon surface.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122681028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200663
A. Shimizu, N. Ohki, H. Ishida, T. Yamanaka, N. Hashimoto, T. Hashimoto, E. Takeda
It was found that a MOSFET with a non-doped poly-Si spacer LDD (SLDD) structure has high current drivability and high reliability in deep submicron regions. The high gate-fringing field effect caused by this spacer introduces lower lateral electric fields and accumulated n/sup -/ regions. The thin SiO/sub 2/ films under the spacer, which vary the gate-fringing field, affect the performance, in particular the hot-carrier effects of the SLDD. Nondoped poly-Si is a good material for this spacer. SLDDs with thin SiO/sub 2/ films (Tsox) varying from 7 to 25 nm under the nondoped poly-Si spacer were investigated. Both the current drivability and the reliability of the SLDD structure strongly depend on Tsox and are better than for the LDD structure with a SiO/sub 2/ spacer (OLDD).<>
{"title":"High drivability and high reliability MOSFETs with non-doped poly-Si spacer LDD structure (SLDD)","authors":"A. Shimizu, N. Ohki, H. Ishida, T. Yamanaka, N. Hashimoto, T. Hashimoto, E. Takeda","doi":"10.1109/VLSIT.1992.200663","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200663","url":null,"abstract":"It was found that a MOSFET with a non-doped poly-Si spacer LDD (SLDD) structure has high current drivability and high reliability in deep submicron regions. The high gate-fringing field effect caused by this spacer introduces lower lateral electric fields and accumulated n/sup -/ regions. The thin SiO/sub 2/ films under the spacer, which vary the gate-fringing field, affect the performance, in particular the hot-carrier effects of the SLDD. Nondoped poly-Si is a good material for this spacer. SLDDs with thin SiO/sub 2/ films (Tsox) varying from 7 to 25 nm under the nondoped poly-Si spacer were investigated. Both the current drivability and the reliability of the SLDD structure strongly depend on Tsox and are better than for the LDD structure with a SiO/sub 2/ spacer (OLDD).<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131891450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200615
F. Masuoka
It is pointed out that the EEPROMs have the potential to replace magnetic hard and floppy disks as computer memories. The cost and technical aspects of EEPROM devices are discussed. The particular advantages of NAND EEPROMs are also considered.<>
{"title":"Technology trend of flash-EEPROM-Can flash-EEPROM overcome DRAM?","authors":"F. Masuoka","doi":"10.1109/VLSIT.1992.200615","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200615","url":null,"abstract":"It is pointed out that the EEPROMs have the potential to replace magnetic hard and floppy disks as computer memories. The cost and technical aspects of EEPROM devices are discussed. The particular advantages of NAND EEPROMs are also considered.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133008861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200622
K. Schuegraf, C. C. King, Chenming Hu
Modifications are made to Fowler-Nordheim tunneling current analysis to model accurately the measured conduction characteristics of insulator layers thinner than 6 nm. The most significant is direct tunneling for which a closed-form expression is introduced. Polysilicon depletion and electron wave interference are also considered. 4 nm is found to a practical limit for SiO/sub 2/ scaling in VLSI applications due to direct tunneling leakage almost independent of power supply voltage. The convergence of the intrinsic TDDB and gate leakage criteria is established and the possibility that gate leakage will set the ultimate limit to oxide scaling at 4 nm is suggested.<>
{"title":"Ultra-thin silicon dioxide leakage current and scaling limit","authors":"K. Schuegraf, C. C. King, Chenming Hu","doi":"10.1109/VLSIT.1992.200622","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200622","url":null,"abstract":"Modifications are made to Fowler-Nordheim tunneling current analysis to model accurately the measured conduction characteristics of insulator layers thinner than 6 nm. The most significant is direct tunneling for which a closed-form expression is introduced. Polysilicon depletion and electron wave interference are also considered. 4 nm is found to a practical limit for SiO/sub 2/ scaling in VLSI applications due to direct tunneling leakage almost independent of power supply voltage. The convergence of the intrinsic TDDB and gate leakage criteria is established and the possibility that gate leakage will set the ultimate limit to oxide scaling at 4 nm is suggested.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114440274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200667
A. Hamada, E. Takeda
An AC hot-carrier effect observed under uniaxial mechanical stress is discussed. The effect is due to trap level lowering induced by compressive mechanical stress. In channel hot electron injection, the trap level lowering results in an electron detrapping and a reduction of surface state generation which is not observed for DC stress. These results are significant for nanoscale device design.<>
{"title":"AC hot-carrier effect under mechanical stress (MOSFET)","authors":"A. Hamada, E. Takeda","doi":"10.1109/VLSIT.1992.200667","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200667","url":null,"abstract":"An AC hot-carrier effect observed under uniaxial mechanical stress is discussed. The effect is due to trap level lowering induced by compressive mechanical stress. In channel hot electron injection, the trap level lowering results in an electron detrapping and a reduction of surface state generation which is not observed for DC stress. These results are significant for nanoscale device design.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"24 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120926618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200639
K. Tsujimoto, T. Kumihashi, N. Kohuji, S. Tachi
A high-rate-gas-flow plasma etching technique using a very low gas pressure and very high pumping rate is described. The principle of high-flow etching is discussed. A high etch rate of 1300 nm/min at 0.5 mtorr has been obtained for the Cl/sub 2/ ECR high-flow system with a bias of -50 V. Low gas pressure discharge with high flow rate is applicable to VLSI processing. Highly directional, low-contamination etching is possible using this etching system.<>
{"title":"High-rate-gas-flow microwave plasma etching of silicon","authors":"K. Tsujimoto, T. Kumihashi, N. Kohuji, S. Tachi","doi":"10.1109/VLSIT.1992.200639","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200639","url":null,"abstract":"A high-rate-gas-flow plasma etching technique using a very low gas pressure and very high pumping rate is described. The principle of high-flow etching is discussed. A high etch rate of 1300 nm/min at 0.5 mtorr has been obtained for the Cl/sub 2/ ECR high-flow system with a bias of -50 V. Low gas pressure discharge with high flow rate is applicable to VLSI processing. Highly directional, low-contamination etching is possible using this etching system.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130421483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：