Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200636
K. Yoshikawa, E. Sakagami, S. Mori, N. Arai, K. Narita, Y. Yamaguchi, Y. Ohshima, K. Naruke
The design and performance of a stacked-gate nonvolatile memory (EPROM/flash) cell operated with a 3.3-V/sub cc/ power supply are discussed. It is shown that optimally redesigned 5-V cells with thinner gate oxide reduced V/sub t/, and greater channel width can be operated on a 3.3-V V/sub cc/ should also be applicable to the next generation of 64-Mb devices and beyond.<>
讨论了在3.3 v /sub / cc/电源下工作的堆叠栅非易失性存储器(EPROM/flash)电池的设计和性能。研究表明，优化设计的具有更薄栅极氧化物的5-V电池可以降低V/sub /，并且可以在3.3 V V/sub / cc/下工作，通道宽度更大，也适用于下一代64mb及以上的设备。
{"title":"A 3.3 V operation nonvolatile memory cell technology","authors":"K. Yoshikawa, E. Sakagami, S. Mori, N. Arai, K. Narita, Y. Yamaguchi, Y. Ohshima, K. Naruke","doi":"10.1109/VLSIT.1992.200636","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200636","url":null,"abstract":"The design and performance of a stacked-gate nonvolatile memory (EPROM/flash) cell operated with a 3.3-V/sub cc/ power supply are discussed. It is shown that optimally redesigned 5-V cells with thinner gate oxide reduced V/sub t/, and greater channel width can be operated on a 3.3-V V/sub cc/ should also be applicable to the next generation of 64-Mb devices and beyond.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126877380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200674
H. Jinbo, Y. Yamashita
A blind mask and a simplified-blind (S-blind) mask proposed for phase shifting lithography are discussed. They both have very simple structures. Both the blind and S-blind methods are very effective in solving the bridging problem in single-layer-shifter phase-shifting lithography. These phase-shifting methods are suitable for 0.3- mu m lithography for the manufacture of 64-Mb DRAMs.<>
{"title":"Application of blind method to phase-shifting lithography","authors":"H. Jinbo, Y. Yamashita","doi":"10.1109/VLSIT.1992.200674","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200674","url":null,"abstract":"A blind mask and a simplified-blind (S-blind) mask proposed for phase shifting lithography are discussed. They both have very simple structures. Both the blind and S-blind methods are very effective in solving the bridging problem in single-layer-shifter phase-shifting lithography. These phase-shifting methods are suitable for 0.3- mu m lithography for the manufacture of 64-Mb DRAMs.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"395 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126891410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200644
W. Lee, J. Sun, J. Warnock, K. Jenkins
The fundamental limits on device performance imposed by geometrical effects are studied. Results of an extensive three-dimensional (3D) device simulation study are given and compared with experimental results of a 0.25- mu m bipolar technology. It is shown in this study that geometrical factors alone can result in lower DC current gain and lower f/sub T/ at low current densities for smaller devices. It is also shown that perimeter effects are beneficial for small emitter devices at high current densities. This is a particularly important design consideration for high current operation as in BiCMOS gates.<>
{"title":"Perimeter effects in small geometry bipolar transistors","authors":"W. Lee, J. Sun, J. Warnock, K. Jenkins","doi":"10.1109/VLSIT.1992.200644","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200644","url":null,"abstract":"The fundamental limits on device performance imposed by geometrical effects are studied. Results of an extensive three-dimensional (3D) device simulation study are given and compared with experimental results of a 0.25- mu m bipolar technology. It is shown in this study that geometrical factors alone can result in lower DC current gain and lower f/sub T/ at low current densities for smaller devices. It is also shown that perimeter effects are beneficial for small emitter devices at high current densities. This is a particularly important design consideration for high current operation as in BiCMOS gates.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127621790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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