Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583808
D. Disney, H. Pein, J. Plummer
This paper describes a novel SOI trench-gate Lateral Insulated-Gate Bipolar Transistor (LIGBT) structure which exhibits 2.5 times higher latching current densities than an equivalent, conventional LIGBT. This improvement is achieved by allowing most of the hole current to reach the cathode contact without flowing under the N+ source region. In addition, two Lateral MOS-Controlled Thyristor (LMCT) structures in Silicon-on-Insulator (SOI) substrates are presented. These devices achieve on-state performance which is far superior to that of equivalent LIGBT devices, and switching speeds which are nearly equivalent to the LIGBT. The two LMCT configurations are compared in terms of their Maximum Controllable Current (MCC), which exceeds 100 A/cm/sup 2/ for some configurations.
{"title":"A trench-gate LIGBT structure and two LMCT structures in SOI substrates","authors":"D. Disney, H. Pein, J. Plummer","doi":"10.1109/ISPSD.1994.583808","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583808","url":null,"abstract":"This paper describes a novel SOI trench-gate Lateral Insulated-Gate Bipolar Transistor (LIGBT) structure which exhibits 2.5 times higher latching current densities than an equivalent, conventional LIGBT. This improvement is achieved by allowing most of the hole current to reach the cathode contact without flowing under the N+ source region. In addition, two Lateral MOS-Controlled Thyristor (LMCT) structures in Silicon-on-Insulator (SOI) substrates are presented. These devices achieve on-state performance which is far superior to that of equivalent LIGBT devices, and switching speeds which are nearly equivalent to the LIGBT. The two LMCT configurations are compared in terms of their Maximum Controllable Current (MCC), which exceeds 100 A/cm/sup 2/ for some configurations.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115126746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583664
I. Widjaja, A. Kurnia, D. Divan, K. Shenai
The next generation of power semiconductor devices will be designed and optimized to meet the specific application requirements. Resonant dc link concept is gaining wide popularity in a range of soft-switching applications because of superior power conversion efficiency and improved overall system reliability. Mixed-mode simulations are used to study the carrier dynamics in non punchthrough IGBT structures during turn-off under soft- and hard-switching conditions. The simulation results are shown to qualitatively predict the measured bump in the tail current with varying output dv/dt conditions.
{"title":"Computer simulation and design optimization of IGBT's in soft-switching converters","authors":"I. Widjaja, A. Kurnia, D. Divan, K. Shenai","doi":"10.1109/ISPSD.1994.583664","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583664","url":null,"abstract":"The next generation of power semiconductor devices will be designed and optimized to meet the specific application requirements. Resonant dc link concept is gaining wide popularity in a range of soft-switching applications because of superior power conversion efficiency and improved overall system reliability. Mixed-mode simulations are used to study the carrier dynamics in non punchthrough IGBT structures during turn-off under soft- and hard-switching conditions. The simulation results are shown to qualitatively predict the measured bump in the tail current with varying output dv/dt conditions.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129609240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583721
N. Iwamuro, B. J. Baliga, R. Kurlagunda, G. Mann, A. Kelley
The reverse biased safe operating area (RBSOA), at snubberless inductive load state, of 600 V and 2500 V emitter switched thyristors (ESTs) has been analyzed numerically and experimentally for the first time and compared to those for the IGBT and MCT. The dependence of the RBSOA upon the P base resistance (R/sub b/) in the main thyristor structure of the EST, which affects the triggering and holding currents of the device, has also been investigated. Two types of destructive failure mechanisms have been identified. One is due to the voltage-induced avalanche multiplication, the other is attributed to the current-induced latch-up of the parasitic thyristor. Physical analysis of the RBSOA's configuration is also discussed.
{"title":"Comparison of RBSOA of ESTs with IGBTs and MCTs","authors":"N. Iwamuro, B. J. Baliga, R. Kurlagunda, G. Mann, A. Kelley","doi":"10.1109/ISPSD.1994.583721","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583721","url":null,"abstract":"The reverse biased safe operating area (RBSOA), at snubberless inductive load state, of 600 V and 2500 V emitter switched thyristors (ESTs) has been analyzed numerically and experimentally for the first time and compared to those for the IGBT and MCT. The dependence of the RBSOA upon the P base resistance (R/sub b/) in the main thyristor structure of the EST, which affects the triggering and holding currents of the device, has also been investigated. Two types of destructive failure mechanisms have been identified. One is due to the voltage-induced avalanche multiplication, the other is attributed to the current-induced latch-up of the parasitic thyristor. Physical analysis of the RBSOA's configuration is also discussed.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127579209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583768
R. Fujishima, A. Kitamura, Y. Nagayasu
A new lateral DMOSFET which utilizes oxide sidewall-spacers is described. The effective channel length is precisely controlled by the length of the spacer. The lateral DMOSFET with a channel length of 0.4 /spl mu/m shows a low channel resistance keeping high punch-through blocking capability. The process is compatible with the conventional 1 /spl mu/m Bi-CMOS process. The device characteristics are predicted by two-dimensional process and device simulators. Measurement results are also described. The developed DMOSFET shows an excellent specific on-resistance of 0.143 /spl Omega//spl middot/mm/sup 2/ and can withstand up to around 80 V.
{"title":"High-performance lateral DMOSFET with oxide sidewall-spacers","authors":"R. Fujishima, A. Kitamura, Y. Nagayasu","doi":"10.1109/ISPSD.1994.583768","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583768","url":null,"abstract":"A new lateral DMOSFET which utilizes oxide sidewall-spacers is described. The effective channel length is precisely controlled by the length of the spacer. The lateral DMOSFET with a channel length of 0.4 /spl mu/m shows a low channel resistance keeping high punch-through blocking capability. The process is compatible with the conventional 1 /spl mu/m Bi-CMOS process. The device characteristics are predicted by two-dimensional process and device simulators. Measurement results are also described. The developed DMOSFET shows an excellent specific on-resistance of 0.143 /spl Omega//spl middot/mm/sup 2/ and can withstand up to around 80 V.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116390427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583764
S. P. Robb, J.L. Sutor
This paper describes some of the latest advances in the field of power integrated circuits. The recent market forces and applications that drive the power IC technologies are identified. The power IC technologies that serve these applications are described and reasons are given why a particular technology is used for a given application.
{"title":"Recent advances in power integrated circuits with high level integration","authors":"S. P. Robb, J.L. Sutor","doi":"10.1109/ISPSD.1994.583764","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583764","url":null,"abstract":"This paper describes some of the latest advances in the field of power integrated circuits. The recent market forces and applications that drive the power IC technologies are identified. The power IC technologies that serve these applications are described and reasons are given why a particular technology is used for a given application.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121526895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583732
T. Vogler, A. Schlogl, D. Schroder
The application of power semiconductors at cryogenic temperatures has recently gained significance in protection elements of SMES (superconducting magnetic energy storage) operating at LHT (liquid helium temperature). The evolution of HT (high temperature)-superconductors, however, is still proceeding and will provide in the near future magnetic insensitive materials operating at LNT (liquid nitrogen temperature). Due to the low price of LN, it will then make sense to reconsider the additional cooling of power electronic topologies and, consequently, to take advantage of improving characteristics of power semiconductors with decreasing temperature. One objective of this paper is to characterize the temperature dependence of different devices' static and dynamic behaviour both by measurement and physical analysis by means of recently published circuit models. Secondly physical assumptions in these models are validated, proving their capability to act as the circuit and device designer's right hand.
{"title":"Modeling and characterizing power semiconductors at low temperatures","authors":"T. Vogler, A. Schlogl, D. Schroder","doi":"10.1109/ISPSD.1994.583732","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583732","url":null,"abstract":"The application of power semiconductors at cryogenic temperatures has recently gained significance in protection elements of SMES (superconducting magnetic energy storage) operating at LHT (liquid helium temperature). The evolution of HT (high temperature)-superconductors, however, is still proceeding and will provide in the near future magnetic insensitive materials operating at LNT (liquid nitrogen temperature). Due to the low price of LN, it will then make sense to reconsider the additional cooling of power electronic topologies and, consequently, to take advantage of improving characteristics of power semiconductors with decreasing temperature. One objective of this paper is to characterize the temperature dependence of different devices' static and dynamic behaviour both by measurement and physical analysis by means of recently published circuit models. Secondly physical assumptions in these models are validated, proving their capability to act as the circuit and device designer's right hand.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125888394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583785
S. Matsumoto, F. Yoshino, H. Ishii, T. Ohno
Selective CVD is used to develop a low on-resistance, high-speed UMOSFET with a new double-layer gate electrode made of tungsten. The experimental UMOSFET has an active device area of 1 mm/sup 2/, an on-resistance of 90 m/spl Omega/ and a breakdown voltage of 70 V. Its corner frequency (-3 dB)is extended to 2.14 MHz. This value is 1.8 times higher than that of a conventional poly-Si-gate UMOSFET.
{"title":"A 70-V, 90-m/spl Omega/ mm/sup 2/, high-speed double-layer gate UMOSFET realized by selective CVD tungsten","authors":"S. Matsumoto, F. Yoshino, H. Ishii, T. Ohno","doi":"10.1109/ISPSD.1994.583785","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583785","url":null,"abstract":"Selective CVD is used to develop a low on-resistance, high-speed UMOSFET with a new double-layer gate electrode made of tungsten. The experimental UMOSFET has an active device area of 1 mm/sup 2/, an on-resistance of 90 m/spl Omega/ and a breakdown voltage of 70 V. Its corner frequency (-3 dB)is extended to 2.14 MHz. This value is 1.8 times higher than that of a conventional poly-Si-gate UMOSFET.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125169067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583729
I. Grekhov, L. S. Kostina, E.I. Belakova, I.A. Rolnik
Silicon Direct Bonding (SDB) technique has been used for designing GTO with a double-layer p-base in which a net of highly doped stripes was made at the interface between the two p-type layers. The device provides a-higher (by an order of magnitude or more) emitter blocking voltage and a lower (nearly 5 times) p-base tangential resistance than in the conventional GTO. This allows one to control a large operating area, to simplify the technology and improve the heat removal. The device has good static and dynamic characteristics with abrupt main current and control current breakage during the turn-off process in contrast to the conventional GTO.
{"title":"Gate turn-off thyristor on the basis of the SDB-technique","authors":"I. Grekhov, L. S. Kostina, E.I. Belakova, I.A. Rolnik","doi":"10.1109/ISPSD.1994.583729","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583729","url":null,"abstract":"Silicon Direct Bonding (SDB) technique has been used for designing GTO with a double-layer p-base in which a net of highly doped stripes was made at the interface between the two p-type layers. The device provides a-higher (by an order of magnitude or more) emitter blocking voltage and a lower (nearly 5 times) p-base tangential resistance than in the conventional GTO. This allows one to control a large operating area, to simplify the technology and improve the heat removal. The device has good static and dynamic characteristics with abrupt main current and control current breakage during the turn-off process in contrast to the conventional GTO.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125245048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583799
R.K. Williams, A. Chang, B. Conckin, G. Pham
A fully-integrated motor-control servo power IC designed for driving small form factor hard disk drives (HDDs) is described. The "combo chip" IC features a novel head retract technique which eliminates the need for external Schottky diodes, yet guarantees the spindle motor's generated emf delivers uninterrupted power for emergency head retract operation. By eliminating the diode and its associated voltage drop, improved spindle motor startup current is achieved using smaller power MOSFETs. Other benefits of this approach include improved running efficiency, reduced head seek times, and increased time (and voltage margin) available to perform emergency head retract. The concept of an auxiliary supply is introduced, as is the method and motivation for eliminating the drain-to-source antiparallel diode in each of the high-side power MOSFETs.
{"title":"A fully integrated HDD power IC with novel head retract feature","authors":"R.K. Williams, A. Chang, B. Conckin, G. Pham","doi":"10.1109/ISPSD.1994.583799","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583799","url":null,"abstract":"A fully-integrated motor-control servo power IC designed for driving small form factor hard disk drives (HDDs) is described. The \"combo chip\" IC features a novel head retract technique which eliminates the need for external Schottky diodes, yet guarantees the spindle motor's generated emf delivers uninterrupted power for emergency head retract operation. By eliminating the diode and its associated voltage drop, improved spindle motor startup current is achieved using smaller power MOSFETs. Other benefits of this approach include improved running efficiency, reduced head seek times, and increased time (and voltage margin) available to perform emergency head retract. The concept of an auxiliary supply is introduced, as is the method and motivation for eliminating the drain-to-source antiparallel diode in each of the high-side power MOSFETs.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130818356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583706
M. S. Shekar, J. Korec, B. J. Baliga
A new MOS-gated Emitter Switched Thyristor (EST) structure using trench gate technology is reported for the first time. In this new trench gate EST, the voltage drop across the series lateral MOSFET is reduced due to an increase in channel density resulting in forward voltage drops equal to thyristors and MCTs. In addition, the parasitic thyristor that is inherent in the conventional EST is completely eliminated in this structure, allowing higher maximum controllable current densities for ESTs. The trench gate allows homogenous current distribution in the EST and preserves the unique feature of gate controlled current saturation of the thyristor current. The characteristics of 600 V forward blocking trench EST obtained from two dimensional numerical simulations is described and compared with that of the trench IGBT and MCT. Resistive load simulations for the trench EST indicate turn-off times comparable to trench IGBTs and MCTs.
{"title":"Trench gate emitter switched thyristors","authors":"M. S. Shekar, J. Korec, B. J. Baliga","doi":"10.1109/ISPSD.1994.583706","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583706","url":null,"abstract":"A new MOS-gated Emitter Switched Thyristor (EST) structure using trench gate technology is reported for the first time. In this new trench gate EST, the voltage drop across the series lateral MOSFET is reduced due to an increase in channel density resulting in forward voltage drops equal to thyristors and MCTs. In addition, the parasitic thyristor that is inherent in the conventional EST is completely eliminated in this structure, allowing higher maximum controllable current densities for ESTs. The trench gate allows homogenous current distribution in the EST and preserves the unique feature of gate controlled current saturation of the thyristor current. The characteristics of 600 V forward blocking trench EST obtained from two dimensional numerical simulations is described and compared with that of the trench IGBT and MCT. Resistive load simulations for the trench EST indicate turn-off times comparable to trench IGBTs and MCTs.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133546813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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