Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583811
M. Harada, T. Minato, H. Takahashi, H. Nishihara, K. Inoue, I. Takata
We have developed a large area trench MOS process and experimentally manufactured a 600 V, 50 A class trench IGBT. By narrowing the trench pitch, the devices achieved a superior ON state voltage(V/sub CE/(sat)=1.4 V, t/sub f/=230 ns @ 200 A/cm/sup 2/) and much better endurance property (dI/sub c//dt/spl ap/2500 A/(s/spl middot/cm/sup 2/)) for latch-up than planar IGBTs. Trench IGBTs also showed a higher breakdown voltage(BV/sub CES/) than planar IGBTs. We have confirmed that the trench IGBT realizes the ideal structure, "PIN diode+MOS gate", which was proposed at the start of the IGBT development. The trench IGBT would be expected to be a superior high voltage device, especially due to its endurance property for latch-up operation.
我们开发了大面积沟槽MOS工艺，并实验制造了600v, 50a级沟槽IGBT。通过缩小沟槽间距，器件获得了比平面igbt更好的ON状态电压(V/sub CE/(sat)=1.4 V, t/sub f/=230 ns @ 200 a /cm/sup 2/)和更好的锁存性能(dI/sub c//dt/spl ap/2500 a /(s/spl中点/cm/sup 2/))。沟槽型igbt的击穿电压(BV/sub CES/)也高于平面型igbt。我们已经证实，沟槽型IGBT实现了IGBT开发之初提出的“PIN二极管+MOS栅极”的理想结构。沟槽IGBT有望成为一种优越的高压器件，特别是由于其闭锁操作的持久性能。
{"title":"600 V trench IGBT in comparison with planar IGBT-an evaluation of the limit of IGBT performance","authors":"M. Harada, T. Minato, H. Takahashi, H. Nishihara, K. Inoue, I. Takata","doi":"10.1109/ISPSD.1994.583811","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583811","url":null,"abstract":"We have developed a large area trench MOS process and experimentally manufactured a 600 V, 50 A class trench IGBT. By narrowing the trench pitch, the devices achieved a superior ON state voltage(V/sub CE/(sat)=1.4 V, t/sub f/=230 ns @ 200 A/cm/sup 2/) and much better endurance property (dI/sub c//dt/spl ap/2500 A/(s/spl middot/cm/sup 2/)) for latch-up than planar IGBTs. Trench IGBTs also showed a higher breakdown voltage(BV/sub CES/) than planar IGBTs. We have confirmed that the trench IGBT realizes the ideal structure, \"PIN diode+MOS gate\", which was proposed at the start of the IGBT development. The trench IGBT would be expected to be a superior high voltage device, especially due to its endurance property for latch-up operation.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134263759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583815
Y. Sugawara, M. Inaba, H. Arakawa
For realization of complementary transistors needed in high voltage, high speed analog ICs, high voltage, high performances lateral pnp transistors have been developed by utilizing the SADDL transistor structure. The developed lateral pnp transistor has a high h/sub FE/ of l00, high f/sub T/ of 320 MHz and low noise figure of 3 dB in spite of a high BV/sub CEO/ of 150 V. When BV/sub CEO/ of the developed SADDL transistor is 340 V, h/sub FE/ is 50 and f/sub T/ is 120 MHz. These f/sub T/'s are about 5 times those of the best conventional lateral pnp transistors with the same BV/sub CEO/, as reported to date.
{"title":"A 150 V, 320 MHz, low noise self-aligned double diffused lateral (SADDL) pnp transistor","authors":"Y. Sugawara, M. Inaba, H. Arakawa","doi":"10.1109/ISPSD.1994.583815","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583815","url":null,"abstract":"For realization of complementary transistors needed in high voltage, high speed analog ICs, high voltage, high performances lateral pnp transistors have been developed by utilizing the SADDL transistor structure. The developed lateral pnp transistor has a high h/sub FE/ of l00, high f/sub T/ of 320 MHz and low noise figure of 3 dB in spite of a high BV/sub CEO/ of 150 V. When BV/sub CEO/ of the developed SADDL transistor is 340 V, h/sub FE/ is 50 and f/sub T/ is 120 MHz. These f/sub T/'s are about 5 times those of the best conventional lateral pnp transistors with the same BV/sub CEO/, as reported to date.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123808659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583724
H. Lendenmann, W. Fichtner
In this paper we present the phenomenological mechanisms leading to turn-off failures for large size MCT devices under inductive loading. Depending on the device current and the clamping voltage two different mechanisms lead to turn-off failures. At lower clamping voltages or in soft switching conditions the SOA is limited by the MOSFET and cathode design rules. At higher voltages and in hard switched conditions the dynamic formation of filaments limits the SOA. The failure phenomena were found to be independent, of cathode layout details, anode structuring, device size, and load circuit, thus representing the fundamental limits of the MCT. However, for optimal selection of these parameters, the failure level can be pushed to high power permitting industrial application of the device. The experimental investigation was carried out with MCT samples of different sizes and layout features and by analysis of destructed devices. The device simulator SIMUL_/sub ISE/ was used to identify the failure mechanisms.
{"title":"Turn-off failure mechanisms in large (2.2 kV, 20 A) MCT devices","authors":"H. Lendenmann, W. Fichtner","doi":"10.1109/ISPSD.1994.583724","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583724","url":null,"abstract":"In this paper we present the phenomenological mechanisms leading to turn-off failures for large size MCT devices under inductive loading. Depending on the device current and the clamping voltage two different mechanisms lead to turn-off failures. At lower clamping voltages or in soft switching conditions the SOA is limited by the MOSFET and cathode design rules. At higher voltages and in hard switched conditions the dynamic formation of filaments limits the SOA. The failure phenomena were found to be independent, of cathode layout details, anode structuring, device size, and load circuit, thus representing the fundamental limits of the MCT. However, for optimal selection of these parameters, the failure level can be pushed to high power permitting industrial application of the device. The experimental investigation was carried out with MCT samples of different sizes and layout features and by analysis of destructed devices. The device simulator SIMUL_/sub ISE/ was used to identify the failure mechanisms.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134140816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583648
H.P. Yee, P. Lauritzen, R. Darling, M. Wakatabe, A. Sugai, K. Horiguchi
A new lateral Advanced IGBT (A-IGBT) that includes an additional P-MOSFET for faster turn-off is presented. The added P-MOSFET removes injected minority carriers in the base of A-IGBT during turn-off, achieving faster turn-off times without increasing IGBT on-state voltages. Device simulations indicate an A-IGBT has a factor of 10 improvement in turn-off time over the standard IGBT.
{"title":"The fast turn off advanced IGBT, a new device concept","authors":"H.P. Yee, P. Lauritzen, R. Darling, M. Wakatabe, A. Sugai, K. Horiguchi","doi":"10.1109/ISPSD.1994.583648","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583648","url":null,"abstract":"A new lateral Advanced IGBT (A-IGBT) that includes an additional P-MOSFET for faster turn-off is presented. The added P-MOSFET removes injected minority carriers in the base of A-IGBT during turn-off, achieving faster turn-off times without increasing IGBT on-state voltages. Device simulations indicate an A-IGBT has a factor of 10 improvement in turn-off time over the standard IGBT.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134239776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583631
Y. Takahashi, T. Koga, H. Kirihata, Y. Seki
A 2.5 kV 100 A /spl mu/(micro)-stack IGBT has been developed. This is the first work to demonstrate the possibility of a high voltage, high current and high reliable flat-packaged MOS controlled device. The 20 mm square chip is press-contacted with an emitter electrode having four rectangular p-base regions on which the MOS gate is not arranged. The great advantage of this structure is the double side cooling and the bondingless emitter wire. The /spl mu/-stack IGBT shows the high blocking voltage of 2.5 kV, the typical saturation voltage of 3.5 V at the collector current Ic=100 A, the turn-off capability of 3/spl times/Ic, and the good pressure contact for the electrical and thermal characteristics in the range from 100 to 800 kg/chip.
{"title":"2.5 kV 100 A /spl mu/-stack IGBT","authors":"Y. Takahashi, T. Koga, H. Kirihata, Y. Seki","doi":"10.1109/ISPSD.1994.583631","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583631","url":null,"abstract":"A 2.5 kV 100 A /spl mu/(micro)-stack IGBT has been developed. This is the first work to demonstrate the possibility of a high voltage, high current and high reliable flat-packaged MOS controlled device. The 20 mm square chip is press-contacted with an emitter electrode having four rectangular p-base regions on which the MOS gate is not arranged. The great advantage of this structure is the double side cooling and the bondingless emitter wire. The /spl mu/-stack IGBT shows the high blocking voltage of 2.5 kV, the typical saturation voltage of 3.5 V at the collector current Ic=100 A, the turn-off capability of 3/spl times/Ic, and the good pressure contact for the electrical and thermal characteristics in the range from 100 to 800 kg/chip.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133970185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583782
R. Sunkavalli, B. J. Baliga, Y. Huang
The temperature dependence of the static parameters of the 550 V RESURF DI LDMOSFET is reported. High temperature measurements were carried out from 25/spl deg/C-200/spl deg/C at intervals of 25/spl deg/C. The parameters measured include the on-resistance, threshold voltage, transconductance, effect of substrate bias, breakdown voltage and leakage current. Accurate analytic models, supported by extensive two-dimensional numerical simulations, have been developed to explain and predict device performance.
{"title":"High temperature performance of dielectrically isolated LDMOSFET: characterization, simulation and analysis","authors":"R. Sunkavalli, B. J. Baliga, Y. Huang","doi":"10.1109/ISPSD.1994.583782","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583782","url":null,"abstract":"The temperature dependence of the static parameters of the 550 V RESURF DI LDMOSFET is reported. High temperature measurements were carried out from 25/spl deg/C-200/spl deg/C at intervals of 25/spl deg/C. The parameters measured include the on-resistance, threshold voltage, transconductance, effect of substrate bias, breakdown voltage and leakage current. Accurate analytic models, supported by extensive two-dimensional numerical simulations, have been developed to explain and predict device performance.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114069056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583644
P. Turkes, W. Kiffe, R. Kuhnert
Due to the dissipated power and the thermal impedance of the package, power devices like the IGBT are subject to significant temperature stress. This paper describes the behaviour of an IGBT within an electrical circuit, at a critical switching condition-the dynamic short. The dissipated electrical power and the resulting temperature rise are analyzed in order to get an insight into the device behaviour close to destruction. Our goal was to evaluate the simulated results in terms of the device temperature to get information about the maximum time the device can survive within this mode of operation.
{"title":"Critical switching condition of a non-punch-through IGBT investigated by electrothermal circuit simulation","authors":"P. Turkes, W. Kiffe, R. Kuhnert","doi":"10.1109/ISPSD.1994.583644","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583644","url":null,"abstract":"Due to the dissipated power and the thermal impedance of the package, power devices like the IGBT are subject to significant temperature stress. This paper describes the behaviour of an IGBT within an electrical circuit, at a critical switching condition-the dynamic short. The dissipated electrical power and the resulting temperature rise are analyzed in order to get an insight into the device behaviour close to destruction. Our goal was to evaluate the simulated results in terms of the device temperature to get information about the maximum time the device can survive within this mode of operation.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121891618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583640
Y. Shimizu, Y. Nakano, Y. Kono, N. Sakurai, Y. Sugawara, S. Otaka
We have proposed a 600 V, 30 A IGBT, having a novel overcurrent protection circuit, on one chip. The protection circuit was fabricated on a silicon wafer coated with a polycrystalline silicon film. A Zener diode was used in the gate suppress circuit to keep the gate voltage at the controlled value. An overcurrent limitation function was successfully obtained with no oscillation. The fabricated device has an on-state voltage of 1.50 V at 100 A/cm/sup 2/. The turn-off fall time is 0.28 /spl mu/s. This trade-off value is almost at the limit of this class of planer-gate IGBT.
{"title":"A high performance intelligent IGBT with overcurrent protection","authors":"Y. Shimizu, Y. Nakano, Y. Kono, N. Sakurai, Y. Sugawara, S. Otaka","doi":"10.1109/ISPSD.1994.583640","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583640","url":null,"abstract":"We have proposed a 600 V, 30 A IGBT, having a novel overcurrent protection circuit, on one chip. The protection circuit was fabricated on a silicon wafer coated with a polycrystalline silicon film. A Zener diode was used in the gate suppress circuit to keep the gate voltage at the controlled value. An overcurrent limitation function was successfully obtained with no oscillation. The fabricated device has an on-state voltage of 1.50 V at 100 A/cm/sup 2/. The turn-off fall time is 0.28 /spl mu/s. This trade-off value is almost at the limit of this class of planer-gate IGBT.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129389898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583734
A. Ludikhuize
The voltage handling capability of Resurf LDMOS and of junction isolated islands in HV IC's is observed to decrease at high current density. This is attributed to the Kirk effect.
高压集成电路中，重熔LDMOS和结孤岛的电压处理能力在高电流密度下下降。这归因于柯克效应。
{"title":"Kirk effect limitations in high voltage IC's","authors":"A. Ludikhuize","doi":"10.1109/ISPSD.1994.583734","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583734","url":null,"abstract":"The voltage handling capability of Resurf LDMOS and of junction isolated islands in HV IC's is observed to decrease at high current density. This is attributed to the Kirk effect.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122545786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583740
J. Ecrabey, L. Hébrard, C. Klingeihofer, F. Gaffiot, G. Jacquemod, J. Berger-Toussan, M. Le Helley
This paper presents the validation of SETIPIC-an electrothermal simulator for power integrated circuits. SETIPIC works by alternation of electrical simulations, using a SPICE-like simulator and thermal simulations using PICMOST-a three-dimensional thermal simulator we wrote to obtain the thermal distribution on the layout surface in a transient or stationary mode. Also, an infrared thermal measurement experimental set up was built to validate SETIPIC on an industrial IC and some thermal results are given.
{"title":"Experimental validation of electrothermal simulations using SETIPIC for analogue integrated circuits","authors":"J. Ecrabey, L. Hébrard, C. Klingeihofer, F. Gaffiot, G. Jacquemod, J. Berger-Toussan, M. Le Helley","doi":"10.1109/ISPSD.1994.583740","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583740","url":null,"abstract":"This paper presents the validation of SETIPIC-an electrothermal simulator for power integrated circuits. SETIPIC works by alternation of electrical simulations, using a SPICE-like simulator and thermal simulations using PICMOST-a three-dimensional thermal simulator we wrote to obtain the thermal distribution on the layout surface in a transient or stationary mode. Also, an infrared thermal measurement experimental set up was built to validate SETIPIC on an industrial IC and some thermal results are given.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116956725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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