Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583697
N. Thaper, B. J. Baliga
A new IGBT structure incorporating a shallow diverter between adjacent cells is proposed in this paper with the aim of widening the Forward Bias Safe Operating Area (FBSOA) of the IGBT. The latchup limit of the IGBT increased from 700 A/cm/sup 2/ to 1100 A/cm/sup 2/ in case of the n-channel IGBT and from 1200 A/cm/sup 2/ to 2100 A/cm/sup 2/ for the p-channel IGBT. Although there was a no improvement in the dynamic avalanche limit in the case of the p-channel IGBT, it improved significantly for the n-channel IGBT making its FBSOA much wider than that of the conventional IGBT. The incorporation of the diverter was found to result in an increase in the forward voltage drop (at a current density of 200 A/cm/sup 2/) from 1.7 V to 2.3 V and -2.3 V to -3.9 V for the n- and the p-channel IGBT, respectively.
{"title":"A new IGBT structure with a wider safe operating area (SOA)","authors":"N. Thaper, B. J. Baliga","doi":"10.1109/ISPSD.1994.583697","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583697","url":null,"abstract":"A new IGBT structure incorporating a shallow diverter between adjacent cells is proposed in this paper with the aim of widening the Forward Bias Safe Operating Area (FBSOA) of the IGBT. The latchup limit of the IGBT increased from 700 A/cm/sup 2/ to 1100 A/cm/sup 2/ in case of the n-channel IGBT and from 1200 A/cm/sup 2/ to 2100 A/cm/sup 2/ for the p-channel IGBT. Although there was a no improvement in the dynamic avalanche limit in the case of the p-channel IGBT, it improved significantly for the n-channel IGBT making its FBSOA much wider than that of the conventional IGBT. The incorporation of the diverter was found to result in an increase in the forward voltage drop (at a current density of 200 A/cm/sup 2/) from 1.7 V to 2.3 V and -2.3 V to -3.9 V for the n- and the p-channel IGBT, respectively.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122262775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583667
A. Litwin, T. Arnborg
A new type of bipolar transistor on SOI material (Silicon-On-Insulator) without buried layer has been fabricated in a standard 1.3 /spl mu/m CMOS process with only few additional mask steps. It is shown by measurements that the I-V characteristics of both pnp and npn transistors are comparable to conventional vertical transistors with buried layer. The voltage capability of devices made in thin silicon layers is substantially high and strongly affected by substrate bias effects. The transistors designed in a few micrometer thick silicon layer have a breakdown voltage BVceo of about 200 volts and also a remarkably high Early voltage, with highest measured value of 4000 V. The transistor will have a strong impact on the feasibility to realise mixed analogue and digital signal circuits with high and low voltage functions on the same chip.
采用标准的1.3 /spl μ m CMOS工艺制备了一种新型无埋层SOI材料(绝缘体上硅)双极晶体管，仅需少量附加掩膜步骤。测量结果表明，pnp和npn晶体管的I-V特性与传统的埋层垂直晶体管相当。在薄硅层中制造的器件的电压能力基本上很高，并且受到衬底偏置效应的强烈影响。在几微米厚的硅层上设计的晶体管击穿电压BVceo约为200伏，早期电压非常高，最高测量值为4000 V。晶体管将对在同一芯片上实现具有高低电压功能的混合模拟和数字信号电路的可行性产生重大影响。
{"title":"Compact very high voltage CMOS compatible bipolar silicon-on-insulator transistor","authors":"A. Litwin, T. Arnborg","doi":"10.1109/ISPSD.1994.583667","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583667","url":null,"abstract":"A new type of bipolar transistor on SOI material (Silicon-On-Insulator) without buried layer has been fabricated in a standard 1.3 /spl mu/m CMOS process with only few additional mask steps. It is shown by measurements that the I-V characteristics of both pnp and npn transistors are comparable to conventional vertical transistors with buried layer. The voltage capability of devices made in thin silicon layers is substantially high and strongly affected by substrate bias effects. The transistors designed in a few micrometer thick silicon layer have a breakdown voltage BVceo of about 200 volts and also a remarkably high Early voltage, with highest measured value of 4000 V. The transistor will have a strong impact on the feasibility to realise mixed analogue and digital signal circuits with high and low voltage functions on the same chip.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134360775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583817
E. Yanokura, T. Seki, I. Takei, Y. Maruyama, Y. Fujita, M. Katsueda, I. Yoshida, M. Ohnishi, K. Sekine
We have developed a highly efficient Si power MOSFET that can operate at 1.5 GHz. This device has a double-ion-implanted layer in an offset region which achieves high drain current density as well as high breakdown voltage. It also has a 0.8-/spl mu/m Mo gate structure for high-frequency operation. In addition, we have successfully designed an internal matching circuit that overcomes the impedance-lowering problem of high-power MOSFETs operated at over 1 GHz. As a result, we obtain an output power of 35 W and a power-added efficiency of 50%, with excellent linearity of power gain.
{"title":"A 1.5 GHz, 35-W Si-MOSFET with an internal matching circuit","authors":"E. Yanokura, T. Seki, I. Takei, Y. Maruyama, Y. Fujita, M. Katsueda, I. Yoshida, M. Ohnishi, K. Sekine","doi":"10.1109/ISPSD.1994.583817","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583817","url":null,"abstract":"We have developed a highly efficient Si power MOSFET that can operate at 1.5 GHz. This device has a double-ion-implanted layer in an offset region which achieves high drain current density as well as high breakdown voltage. It also has a 0.8-/spl mu/m Mo gate structure for high-frequency operation. In addition, we have successfully designed an internal matching circuit that overcomes the impedance-lowering problem of high-power MOSFETs operated at over 1 GHz. As a result, we obtain an output power of 35 W and a power-added efficiency of 50%, with excellent linearity of power gain.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132131554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583674
N. Thapar, B. J. Baliga
To reduce the conduction and switching losses in a MOSFET, it is desirable to reduce its specific on-resistance (R/sub on,sp/) and the specific input capacitance (C/sub in,sp/). In this paper, the Atomic Lattice Layout (ALL) and the Circular Layout (CL) are compared for a high frequency 400 V n-channel MOSFET with the goal of obtaining the lowest R/sub on/C/sub in/ product. The terrace gate design on ALL, with 6000 /spl Aring/ field oxide under the terrace gate region resulted in a R/sub on/C/sub in/ product of 603 /spl Omega/-pf which is nearly 4 times lower than the conventional DMOS design. It was also found to be superior to the same gate design on a CL. In the cell structure with a floating P/sup +/ diffusion, the gate-drain component (C/sub gd/) of the input capacitance (C/sub in/) was reduced by moving the floating P/sup +/ diffusion edge closer to the P-base edge at the expense of increasing the on-resistance. By studying the variation of the R/sub on/C/sub in/ product as a function of the position of the floating P/sup +/ edge, lowest R/sub on/C/sub in/ products of 452 /spl Omega/-pf and 360 /spl Omega/-pf were obtained for the ALL and CL, respectively. Although the R/sub on/C/sub in/ product of this structure is smaller than the terraced gate structures, the specific on-resistance is larger (98 m/spl Omega/-cm/sup 2/ vs 68 m/spl Omega/-cm/sup 2/ for the ALL and 137 m/spl Omega/-cm/sup 2/ vs 86 m/spl Omega/-cm/sup 2/ for the CL), which implies an increase in the die area. It was shown through simulations that the specific on-resistance did not increase appreciably with a reduction in the gate bias from 10 V to 5 V. Hence operation at 5 V gate bias is recommended to reduce the gate switching losses, which increase as the square of the gate drive voltage.
为了降低MOSFET的传导和开关损耗，需要降低其比导通电阻(R/sub on,sp/)和比输入电容(C/sub in,sp/)。本文对高频400 V n沟道MOSFET的原子点阵布局(ALL)和圆形布局(CL)进行了比较，目的是获得最低的R/sub on/C/sub In /积。阶地栅极在ALL上设计，阶地栅极区域下有6000 /spl Aring/ field oxide, R/sub on/C/sub in/ product为603 /spl Omega/-pf，比传统DMOS设计低近4倍。它也被发现优于相同的闸门设计在一个CL。在具有浮动P/sup +/扩散的电池结构中，通过将浮动P/sup +/扩散边缘移近P基边缘，以增加导通电阻为代价，减小了输入电容(C/sub In /)的栅极漏极分量(C/sub gd/)。通过研究R/sub on/C/sub in/ product随浮P/sup +/边缘位置的变化规律，得到ALL和CL的R/sub on/C/sub in/ product的最低值分别为452 /spl Omega/-pf和360 /spl Omega/-pf。虽然这种结构的R/sub - on/C/sub - in/乘积小于梯级栅极结构，但比导通电阻更大(ALL为98 m/spl Omega/-cm/sup 2/ vs 68 m/spl Omega/-cm/sup 2/， CL为137 m/spl Omega/-cm/sup 2/ vs 86 m/spl Omega/-cm/sup 2/)，这意味着模具面积增加。模拟结果表明，栅极偏置从10 V减小到5 V时，导通电阻没有明显增加。因此，建议在5 V栅极偏置下工作，以减少栅极开关损耗，栅极开关损耗随栅极驱动电压的平方而增加。
{"title":"A comparison of high frequency cell designs for high voltage DMOSFETs","authors":"N. Thapar, B. J. Baliga","doi":"10.1109/ISPSD.1994.583674","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583674","url":null,"abstract":"To reduce the conduction and switching losses in a MOSFET, it is desirable to reduce its specific on-resistance (R/sub on,sp/) and the specific input capacitance (C/sub in,sp/). In this paper, the Atomic Lattice Layout (ALL) and the Circular Layout (CL) are compared for a high frequency 400 V n-channel MOSFET with the goal of obtaining the lowest R/sub on/C/sub in/ product. The terrace gate design on ALL, with 6000 /spl Aring/ field oxide under the terrace gate region resulted in a R/sub on/C/sub in/ product of 603 /spl Omega/-pf which is nearly 4 times lower than the conventional DMOS design. It was also found to be superior to the same gate design on a CL. In the cell structure with a floating P/sup +/ diffusion, the gate-drain component (C/sub gd/) of the input capacitance (C/sub in/) was reduced by moving the floating P/sup +/ diffusion edge closer to the P-base edge at the expense of increasing the on-resistance. By studying the variation of the R/sub on/C/sub in/ product as a function of the position of the floating P/sup +/ edge, lowest R/sub on/C/sub in/ products of 452 /spl Omega/-pf and 360 /spl Omega/-pf were obtained for the ALL and CL, respectively. Although the R/sub on/C/sub in/ product of this structure is smaller than the terraced gate structures, the specific on-resistance is larger (98 m/spl Omega/-cm/sup 2/ vs 68 m/spl Omega/-cm/sup 2/ for the ALL and 137 m/spl Omega/-cm/sup 2/ vs 86 m/spl Omega/-cm/sup 2/ for the CL), which implies an increase in the die area. It was shown through simulations that the specific on-resistance did not increase appreciably with a reduction in the gate bias from 10 V to 5 V. Hence operation at 5 V gate bias is recommended to reduce the gate switching losses, which increase as the square of the gate drive voltage.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130188634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583762
H. Zeller
Recently a new cosmic ray induced failure mode of high current-high voltage semiconductor devices has been discovered. The failure affects diodes, thyristors and GTO's as well. it consists of a localised breakdown in the bulk of the device and is not related to junction termination instabilities. The onset of the breakdown occurs without a precursor within a few nanoseconds. The failure rate is constant in time, strongly dependent on applied voltage and nearly independent of temperature. The effect is reduced by screening and thus it is generally believed that the failure is cosmic ray induced. We have measured GTO's, diodes and thyristors of 2.5 kV and 4.5 kV ratings at various test voltages and also have obtained field data from customers.
{"title":"Cosmic ray induced breakdown in high voltage semiconductor devices, microscopic model and phenomenological lifetime prediction","authors":"H. Zeller","doi":"10.1109/ISPSD.1994.583762","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583762","url":null,"abstract":"Recently a new cosmic ray induced failure mode of high current-high voltage semiconductor devices has been discovered. The failure affects diodes, thyristors and GTO's as well. it consists of a localised breakdown in the bulk of the device and is not related to junction termination instabilities. The onset of the breakdown occurs without a precursor within a few nanoseconds. The failure rate is constant in time, strongly dependent on applied voltage and nearly independent of temperature. The effect is reduced by screening and thus it is generally believed that the failure is cosmic ray induced. We have measured GTO's, diodes and thyristors of 2.5 kV and 4.5 kV ratings at various test voltages and also have obtained field data from customers.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132876964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583671
H. Neubrand, R. Constapel, R. Boot, M. Fullmann, A. Boose
Simulated temperature distributions for SOI-structures with various film thicknesses for different operating conditions (on state, turn-off and pulse overload) and different SOI sheet thicknesses (20 /spl mu/m, 5 /spl mu/m) are presented and discussed. The temperature increase was in the range between 5 K and 400 K. The calculated results have been verified experimentally for a fabricated device. An important result is the reduced pulse overload capacity of thin SOI-devices in the 10 /spl mu/s to 100 /spl mu/s range. Consequences for application of SOI-devices are discussed.
{"title":"Thermal behaviour of lateral power devices on SOI substrates","authors":"H. Neubrand, R. Constapel, R. Boot, M. Fullmann, A. Boose","doi":"10.1109/ISPSD.1994.583671","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583671","url":null,"abstract":"Simulated temperature distributions for SOI-structures with various film thicknesses for different operating conditions (on state, turn-off and pulse overload) and different SOI sheet thicknesses (20 /spl mu/m, 5 /spl mu/m) are presented and discussed. The temperature increase was in the range between 5 K and 400 K. The calculated results have been verified experimentally for a fabricated device. An important result is the reduced pulse overload capacity of thin SOI-devices in the 10 /spl mu/s to 100 /spl mu/s range. Consequences for application of SOI-devices are discussed.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126150850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583752
N. Andersson, M. Gronlund, P. Kuivalainen, H. Pohjonen
We have developed a new extensive model library for MOS-gated power devices aimed for CAD and the simulation of power integrated circuits and power electronics. Comparisons between the compact physical models implemented in an open circuit simulator, Aplac, and semiempirical SPICE compatible subcircuit models show that the accuracy of the subcircuit models approaches that of the physical models, if the components of the subcircuit are modelled properly.
{"title":"A comparative study of physical and subcircuit models for MOS-gated power devices","authors":"N. Andersson, M. Gronlund, P. Kuivalainen, H. Pohjonen","doi":"10.1109/ISPSD.1994.583752","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583752","url":null,"abstract":"We have developed a new extensive model library for MOS-gated power devices aimed for CAD and the simulation of power integrated circuits and power electronics. Comparisons between the compact physical models implemented in an open circuit simulator, Aplac, and semiempirical SPICE compatible subcircuit models show that the accuracy of the subcircuit models approaches that of the physical models, if the components of the subcircuit are modelled properly.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123956421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583647
T. Chow, D. Pattanayak, B. J. Baliga, M. Adler
A novel reverse-channel lateral IGBT has been studied with numerical simulations and demonstrated experimentally for the first time. It exhibits a negative differential resistance (NDR) region, which is dependent on the gate voltage and has large peak to valley ratios (10 to >1000), in the I-V characteristics. Also, during dynamic switching, it has been shown to be self-current limiting and hence not to latch up.
{"title":"A reverse-channel, high-voltage lateral IGBT","authors":"T. Chow, D. Pattanayak, B. J. Baliga, M. Adler","doi":"10.1109/ISPSD.1994.583647","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583647","url":null,"abstract":"A novel reverse-channel lateral IGBT has been studied with numerical simulations and demonstrated experimentally for the first time. It exhibits a negative differential resistance (NDR) region, which is dependent on the gate voltage and has large peak to valley ratios (10 to >1000), in the I-V characteristics. Also, during dynamic switching, it has been shown to be self-current limiting and hence not to latch up.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123727860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583736
S. Klaka, R. Sittig
Schwarzbauer and Kuhnert proposed a novel low temperature joining (LTJ) technique to connect silicon wafers with molybdenum backplates [1989, 1991]. Investigation of the bond build-up led to the idea to influence the thermomechanical stresses between bonded materials. By measuring the temperature dependent bow of silicon disks of 26 mm diameter joined to molybdenum backplates the stresses inside both materials were determined. The experiments revealed that variation of process parameters allows one to control the temperature at which no stress occurs between the joined disks. This can be used to considerably reduce thermomechanical stress caused by temperature cycling.
{"title":"Reduction of thermomechanical stress by applying a low temperature joining technique","authors":"S. Klaka, R. Sittig","doi":"10.1109/ISPSD.1994.583736","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583736","url":null,"abstract":"Schwarzbauer and Kuhnert proposed a novel low temperature joining (LTJ) technique to connect silicon wafers with molybdenum backplates [1989, 1991]. Investigation of the bond build-up led to the idea to influence the thermomechanical stresses between bonded materials. By measuring the temperature dependent bow of silicon disks of 26 mm diameter joined to molybdenum backplates the stresses inside both materials were determined. The experiments revealed that variation of process parameters allows one to control the temperature at which no stress occurs between the joined disks. This can be used to considerably reduce thermomechanical stress caused by temperature cycling.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123874104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583748
H. Kim, J. Jin, C. Jeoun, Y. Choi, B. Kwon, S. Lim, K. Choi
In this paper, we present a novel bipolar technology featuring the trench-isolated base. When employed for a conventional 2 /spl mu/m process, the trench isolation reduces both the surface leakage and current gain of the parasitic lateral pnp transistor by at least one order, which results in the improvement of the punchthrough-induced breakdown behavior by almost a factor of two. The depletion capacitance is also diminished by about 60% thanks to the decrease of the effective base-collector junction area, suggesting that the trench isolation is a viable approach even for high frequency as well as for high voltage applications.
{"title":"A novel high voltage bipolar technology featuring trench-isolated base","authors":"H. Kim, J. Jin, C. Jeoun, Y. Choi, B. Kwon, S. Lim, K. Choi","doi":"10.1109/ISPSD.1994.583748","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583748","url":null,"abstract":"In this paper, we present a novel bipolar technology featuring the trench-isolated base. When employed for a conventional 2 /spl mu/m process, the trench isolation reduces both the surface leakage and current gain of the parasitic lateral pnp transistor by at least one order, which results in the improvement of the punchthrough-induced breakdown behavior by almost a factor of two. The depletion capacitance is also diminished by about 60% thanks to the decrease of the effective base-collector junction area, suggesting that the trench isolation is a viable approach even for high frequency as well as for high voltage applications.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116780330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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