Pub Date : 2022-05-11DOI: 10.23919/ICEP55381.2022.9795651
Chi-Hsuan Lin, Wei-ting Chen, Y. Ke, Jenn-Ming Song, K. Yasuda
In this study, coulometric reduction method was adopted to investigate the phase and thickness of surface oxide layer of sputtered copper. The samples subjected to citric acid wash and room temperature storage were investigated. Repeated reduction tests in NaOH solution was also carried out to explore the very early state of the copper surface. According to the reduction potential ranging from -0.62 to 0.65 V, the initial oxide formed in NaOH solution was CuO with the thickness of around 1.1~1.2 nm.
{"title":"Electrochemical analysis of initial oxide layers on copper surface","authors":"Chi-Hsuan Lin, Wei-ting Chen, Y. Ke, Jenn-Ming Song, K. Yasuda","doi":"10.23919/ICEP55381.2022.9795651","DOIUrl":"https://doi.org/10.23919/ICEP55381.2022.9795651","url":null,"abstract":"In this study, coulometric reduction method was adopted to investigate the phase and thickness of surface oxide layer of sputtered copper. The samples subjected to citric acid wash and room temperature storage were investigated. Repeated reduction tests in NaOH solution was also carried out to explore the very early state of the copper surface. According to the reduction potential ranging from -0.62 to 0.65 V, the initial oxide formed in NaOH solution was CuO with the thickness of around 1.1~1.2 nm.","PeriodicalId":413776,"journal":{"name":"2022 International Conference on Electronics Packaging (ICEP)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131964939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-11DOI: 10.23919/ICEP55381.2022.9795596
M. Akimoto, Makoto Yoshida, T. Miyashita
There is an unintended inductance called stray inductance in the power module. For modules with a switching function, the inductance should be reduced to make power loss during overshoot smaller. In this experiment, design variables were defined as the structure of the module, and the inductance was calculated from design variables. The design optimization was performed by the response surface methodology. As a result of calculating the performance for the optimized structure, the inductance was confirmed to be reduced by 12.1% from the original structure. The contribution distribution of each design variable to the inductance was also obtained.
{"title":"Design Optimization of power module structure for inductance reduction","authors":"M. Akimoto, Makoto Yoshida, T. Miyashita","doi":"10.23919/ICEP55381.2022.9795596","DOIUrl":"https://doi.org/10.23919/ICEP55381.2022.9795596","url":null,"abstract":"There is an unintended inductance called stray inductance in the power module. For modules with a switching function, the inductance should be reduced to make power loss during overshoot smaller. In this experiment, design variables were defined as the structure of the module, and the inductance was calculated from design variables. The design optimization was performed by the response surface methodology. As a result of calculating the performance for the optimized structure, the inductance was confirmed to be reduced by 12.1% from the original structure. The contribution distribution of each design variable to the inductance was also obtained.","PeriodicalId":413776,"journal":{"name":"2022 International Conference on Electronics Packaging (ICEP)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127365950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-11DOI: 10.23919/ICEP55381.2022.9795434
Ayano Furue, Sinei Miyasaka, Yusuke Ogushi, Riki Yamanishi, S. Matsumoto
3D power supply on chip (3D power SoC), which integrates Si based IC, Gallium Nitride (GaN) power devices and passive devices realizes high efficiency at high frequency switching and high-power density. Miniaturization makes 3D power SoC high temperature, thus, we have to take into consideration of the temperature effect when we design 3D power SoC. In this paper, we propose a virtual prototyping technique, which is coupling of thermal-device, heat conduction, thermal-electromagnetic, and thermal-circuit simulation to design the 3D power supply on chip.
3D电源芯片(3D power SoC)集成了硅基集成电路、氮化镓(GaN)功率器件和无源器件，实现了高效率的高频开关和高功率密度。小型化使得3D电源SoC的温度较高，因此在设计3D电源SoC时必须考虑温度效应。本文提出了一种结合热器件、热传导、热电磁和热电路仿真的虚拟样机技术来设计芯片上的三维电源。
{"title":"Design Consideration of 3D Power SoC Using Virtual Prototyping","authors":"Ayano Furue, Sinei Miyasaka, Yusuke Ogushi, Riki Yamanishi, S. Matsumoto","doi":"10.23919/ICEP55381.2022.9795434","DOIUrl":"https://doi.org/10.23919/ICEP55381.2022.9795434","url":null,"abstract":"3D power supply on chip (3D power SoC), which integrates Si based IC, Gallium Nitride (GaN) power devices and passive devices realizes high efficiency at high frequency switching and high-power density. Miniaturization makes 3D power SoC high temperature, thus, we have to take into consideration of the temperature effect when we design 3D power SoC. In this paper, we propose a virtual prototyping technique, which is coupling of thermal-device, heat conduction, thermal-electromagnetic, and thermal-circuit simulation to design the 3D power supply on chip.","PeriodicalId":413776,"journal":{"name":"2022 International Conference on Electronics Packaging (ICEP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129201920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-11DOI: 10.23919/ICEP55381.2022.9795627
T. Iwasaki
A materials-informatics technology for designing stable and strong interfaces has been developed by use of advanced molecular simulation that can calculate the delamination energy as the adhesion strength. Because biobased materials such as a plant-derived resin (polyamide 11) and DNAs are eco-friendly materials with carbon neutrality, these materials are considered as semiconductor package substrates and insulating materials. So, the developed informatics technology is applied to the interfaces between polyamide 11 and ceramics used as fillers. At the first stage, the lattice constants were selected as the important, dominant ceramic parameters from four ceramic parameters (the shortside and long-side lattice constants, surface energy density, and cohesive energy) by using sensitivity analysis based on the orthogonal array with the delamination-energy data calculated from advanced molecular simulation. At the second stage, the adhesion strength (delamination energy) is expressed as a function of the important ceramic parameters (i.e., the short-side and long-side lattice constants) by using a response-surface method (Kriging method). At the third stage, by solving the maximum-value problem of the function, it was found that the strongest interface was obtained when the lattice misfits between ceramics and polyamide 11 were zero. By using yttria-doped zirconia as a ceramic material, the strongest interface between polyamide 11 and ceramics was obtained because the coherent interface with no lattice misfit was obtained.
{"title":"Materials Informatics Technology for Using Bio-based Materials","authors":"T. Iwasaki","doi":"10.23919/ICEP55381.2022.9795627","DOIUrl":"https://doi.org/10.23919/ICEP55381.2022.9795627","url":null,"abstract":"A materials-informatics technology for designing stable and strong interfaces has been developed by use of advanced molecular simulation that can calculate the delamination energy as the adhesion strength. Because biobased materials such as a plant-derived resin (polyamide 11) and DNAs are eco-friendly materials with carbon neutrality, these materials are considered as semiconductor package substrates and insulating materials. So, the developed informatics technology is applied to the interfaces between polyamide 11 and ceramics used as fillers. At the first stage, the lattice constants were selected as the important, dominant ceramic parameters from four ceramic parameters (the shortside and long-side lattice constants, surface energy density, and cohesive energy) by using sensitivity analysis based on the orthogonal array with the delamination-energy data calculated from advanced molecular simulation. At the second stage, the adhesion strength (delamination energy) is expressed as a function of the important ceramic parameters (i.e., the short-side and long-side lattice constants) by using a response-surface method (Kriging method). At the third stage, by solving the maximum-value problem of the function, it was found that the strongest interface was obtained when the lattice misfits between ceramics and polyamide 11 were zero. By using yttria-doped zirconia as a ceramic material, the strongest interface between polyamide 11 and ceramics was obtained because the coherent interface with no lattice misfit was obtained.","PeriodicalId":413776,"journal":{"name":"2022 International Conference on Electronics Packaging (ICEP)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115591989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-11DOI: 10.23919/ICEP55381.2022.9795431
W. Teng, J. Lee, Hsin-Ming Tseng, Liang-Yih Hung, Don Son Jiang, Yu-Po Wang
This study explored the impact of additives on the application of underfill in large-size fan-out multichip module packages. The experimental results of a high-temperature storage test demonstrated that the selected underfill developed cracks. Optical microscope examination of a cross section of the cracks revealed an oxidation layer. Through addition of an anti-oxidation agent to the underfill, both forming of the oxidation layer and cracking in the underfill resulting from thermal oxidation were prevented. By contrast, when an underfill without an added flexibilizer was used in the large-size fan-out multichip module package and subjected to a temperature cycling test, cracks were observed in the chip corners, which had formed because of excessive stress in the package. When both the antioxidant and flexibilizer were added to the underfill, the generation of thermal oxidation–induced and stress-induced cracks in the package was prevented.
{"title":"Stress and Reliability Challenges of Underfills in Large-Size Fan-Out Multichip Module Packages","authors":"W. Teng, J. Lee, Hsin-Ming Tseng, Liang-Yih Hung, Don Son Jiang, Yu-Po Wang","doi":"10.23919/ICEP55381.2022.9795431","DOIUrl":"https://doi.org/10.23919/ICEP55381.2022.9795431","url":null,"abstract":"This study explored the impact of additives on the application of underfill in large-size fan-out multichip module packages. The experimental results of a high-temperature storage test demonstrated that the selected underfill developed cracks. Optical microscope examination of a cross section of the cracks revealed an oxidation layer. Through addition of an anti-oxidation agent to the underfill, both forming of the oxidation layer and cracking in the underfill resulting from thermal oxidation were prevented. By contrast, when an underfill without an added flexibilizer was used in the large-size fan-out multichip module package and subjected to a temperature cycling test, cracks were observed in the chip corners, which had formed because of excessive stress in the package. When both the antioxidant and flexibilizer were added to the underfill, the generation of thermal oxidation–induced and stress-induced cracks in the package was prevented.","PeriodicalId":413776,"journal":{"name":"2022 International Conference on Electronics Packaging (ICEP)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121657060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-11DOI: 10.23919/ICEP55381.2022.9795501
K. Okamoto, K. Okamoto, K. Morishita, A. Okuno
The bipolar transistor was invented in 1948 by W. Shockley at Bell Laboratories in the United States. Since then, the transistor has advanced along with the progress of integrated circuit technology, leading to today's advanced information society. Surprisingly, however, the bipolar transistor itself has not shown any significant technological progress. In this paper, we introduce the recently invented "Distar", a revolutionary transistor consisting of only LED and Si solar cell.
{"title":"Development of Photoelectric Conversion Transistor Consisting of High-power LED and Si Solar Cell","authors":"K. Okamoto, K. Okamoto, K. Morishita, A. Okuno","doi":"10.23919/ICEP55381.2022.9795501","DOIUrl":"https://doi.org/10.23919/ICEP55381.2022.9795501","url":null,"abstract":"The bipolar transistor was invented in 1948 by W. Shockley at Bell Laboratories in the United States. Since then, the transistor has advanced along with the progress of integrated circuit technology, leading to today's advanced information society. Surprisingly, however, the bipolar transistor itself has not shown any significant technological progress. In this paper, we introduce the recently invented \"Distar\", a revolutionary transistor consisting of only LED and Si solar cell.","PeriodicalId":413776,"journal":{"name":"2022 International Conference on Electronics Packaging (ICEP)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115594782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-11DOI: 10.23919/ICEP55381.2022.9795470
T. Araki, Kou-Tan Li, Naoko Kurihira, Yuko Kasai, D. Suzuki, Satsuki Yasui, Y. Kawano, T. Sekitani
Flexible hybrid electronics (FHE) has the potential to realize flexible and light large-area electronics by integrating the benefits of traditional semiconductor processing. In addition, printable electronics is expected to lead to resource and energy savings. In this study, we have developed stretchable printed circuit boards, with excellent ductility, on which light-emitting diodes (LEDs) and light sensors were mounted to fabricate sheet-type arrays. The technology developed herein for light-sensing systems based on light sources and detectors is expected to be used as a nondestructive method to inspect objects with arbitrary surfaces.
{"title":"Stretchable Printed Circuit Board for Wireless Light-Sensing System","authors":"T. Araki, Kou-Tan Li, Naoko Kurihira, Yuko Kasai, D. Suzuki, Satsuki Yasui, Y. Kawano, T. Sekitani","doi":"10.23919/ICEP55381.2022.9795470","DOIUrl":"https://doi.org/10.23919/ICEP55381.2022.9795470","url":null,"abstract":"Flexible hybrid electronics (FHE) has the potential to realize flexible and light large-area electronics by integrating the benefits of traditional semiconductor processing. In addition, printable electronics is expected to lead to resource and energy savings. In this study, we have developed stretchable printed circuit boards, with excellent ductility, on which light-emitting diodes (LEDs) and light sensors were mounted to fabricate sheet-type arrays. The technology developed herein for light-sensing systems based on light sources and detectors is expected to be used as a nondestructive method to inspect objects with arbitrary surfaces.","PeriodicalId":413776,"journal":{"name":"2022 International Conference on Electronics Packaging (ICEP)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126904918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-11DOI: 10.23919/ICEP55381.2022.9795465
Rakesh Kumar, F. Ke, Dustin England, Angie Summers, L. Young
This new development solves growing issues of halogen-free reliability and corrosion protection of next-generation, flexible and highly-dense electronics in harsh environments through an ultra-thin, completely halogen free vapor-phase coating, and also as a substrate for flexible electronics. To meet the industry’s current and future requirements worldwide, this presentation introduces a new halogen-free Parylene, ParyFree, to the electronics industry and shares the characterization and qualification results of ParyFree Parylene conformal coating for the protection, reliability and robust performance of all types of electronics. Testing on the new coating includes IPX water resistance, 85/85 exposure, corrosion resistance and qualification per IPC-CC-830B.
{"title":"A New Halogen-Free Vapor Phase Coating for High Reliability & Protection of Electronics in Corrosive and Other Harsh Environments","authors":"Rakesh Kumar, F. Ke, Dustin England, Angie Summers, L. Young","doi":"10.23919/ICEP55381.2022.9795465","DOIUrl":"https://doi.org/10.23919/ICEP55381.2022.9795465","url":null,"abstract":"This new development solves growing issues of halogen-free reliability and corrosion protection of next-generation, flexible and highly-dense electronics in harsh environments through an ultra-thin, completely halogen free vapor-phase coating, and also as a substrate for flexible electronics. To meet the industry’s current and future requirements worldwide, this presentation introduces a new halogen-free Parylene, ParyFree, to the electronics industry and shares the characterization and qualification results of ParyFree Parylene conformal coating for the protection, reliability and robust performance of all types of electronics. Testing on the new coating includes IPX water resistance, 85/85 exposure, corrosion resistance and qualification per IPC-CC-830B.","PeriodicalId":413776,"journal":{"name":"2022 International Conference on Electronics Packaging (ICEP)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127420373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-11DOI: 10.23919/ICEP55381.2022.9795453
F. Kato, S. Sato, H. Hozoji, M. Ikegawa, A. Sakai, K. Watanabe, S. Harada, H. Sato
In this paper, thermal impedance (Zth) of power modules which is assembled with a silicon carbide Schottky barrier diode (SiC-SBD) and metal oxide semiconductor field effect transistor (SiC-MOSFET) was measured and compared. SiC-MOSFETs had gate pads that accounted for 6% of the die size. SiC-MOSFETs had up to 55% higher thermal impedance and 13% higher steady-state thermal resistance compared to SiC-SBDs. Although the gate pad occupies only a small area in the device chip, it was found to have a significant difference on the thermal impedance of SiC power modules, especially in the short time region.
{"title":"Effect of Gate Pad Layout on Thermal Impedance of SiC-MOSFET","authors":"F. Kato, S. Sato, H. Hozoji, M. Ikegawa, A. Sakai, K. Watanabe, S. Harada, H. Sato","doi":"10.23919/ICEP55381.2022.9795453","DOIUrl":"https://doi.org/10.23919/ICEP55381.2022.9795453","url":null,"abstract":"In this paper, thermal impedance (Zth) of power modules which is assembled with a silicon carbide Schottky barrier diode (SiC-SBD) and metal oxide semiconductor field effect transistor (SiC-MOSFET) was measured and compared. SiC-MOSFETs had gate pads that accounted for 6% of the die size. SiC-MOSFETs had up to 55% higher thermal impedance and 13% higher steady-state thermal resistance compared to SiC-SBDs. Although the gate pad occupies only a small area in the device chip, it was found to have a significant difference on the thermal impedance of SiC power modules, especially in the short time region.","PeriodicalId":413776,"journal":{"name":"2022 International Conference on Electronics Packaging (ICEP)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126911497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-11DOI: 10.23919/ICEP55381.2022.9795524
Y. Chao, Chi-Chieh Li, C. Chung
In this study, uniaxial electrospinning was used to prepare silicon-based oxide fluorescent nanofibers. Polyvinylpyrrolidone was mixed with alcohol and dimethylformamide, and tetraethoxysilane was used as the silicon source to prepare the precursor. Finally, yttrium nitrate, calcium nitrate, and europium nitrate are added to the solution for electrospinning,Use scanning electron microscope to investigate the surface morphology of nanofibers; thermogravimetric analyzer to measure weight loss at different temperatures and water drop angle tester to test hydrophilic and hydrophobic properties. After observing the surface morphology of the nanofibers with a scanning electron microscope, the average diameter of the as-spun fibers was 143 nm and the average diameter of the fibers after calcined at 600 °C was 147 nm.
{"title":"A Study of Silicon-based Oxide Fluorescent Nanofibers by Electrospinning","authors":"Y. Chao, Chi-Chieh Li, C. Chung","doi":"10.23919/ICEP55381.2022.9795524","DOIUrl":"https://doi.org/10.23919/ICEP55381.2022.9795524","url":null,"abstract":"In this study, uniaxial electrospinning was used to prepare silicon-based oxide fluorescent nanofibers. Polyvinylpyrrolidone was mixed with alcohol and dimethylformamide, and tetraethoxysilane was used as the silicon source to prepare the precursor. Finally, yttrium nitrate, calcium nitrate, and europium nitrate are added to the solution for electrospinning,Use scanning electron microscope to investigate the surface morphology of nanofibers; thermogravimetric analyzer to measure weight loss at different temperatures and water drop angle tester to test hydrophilic and hydrophobic properties. After observing the surface morphology of the nanofibers with a scanning electron microscope, the average diameter of the as-spun fibers was 143 nm and the average diameter of the fibers after calcined at 600 °C was 147 nm.","PeriodicalId":413776,"journal":{"name":"2022 International Conference on Electronics Packaging (ICEP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125405745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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