Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377883
J. Sato, K. Takinami, Kazuaki Takahashi
Millimeter wave band is suitable for high-speed communication and high-precision sensing applications by its broadband characteristics. The key factor for these applications is to realize wireless systems that can be practically integrated by using complementary metal-oxide semiconductor (CMOS) technology. In millimeter wave bands, precise circuit models and digital calibration techniques for correcting variations of CMOS analog circuits are required for commercialization. This paper describes 60 GHz and 79 GHz CMOS chipsets for multi-gigabit wireless communications and phased-array radar applications. Additionally it introduces 140 GHz CMOS integrated circuit design as future challenges toward Terahertz era.
{"title":"Millimeter wave CMOS integrated circuit for multi-gigabit communication and radar applications","authors":"J. Sato, K. Takinami, Kazuaki Takahashi","doi":"10.1109/RFIT.2015.7377883","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377883","url":null,"abstract":"Millimeter wave band is suitable for high-speed communication and high-precision sensing applications by its broadband characteristics. The key factor for these applications is to realize wireless systems that can be practically integrated by using complementary metal-oxide semiconductor (CMOS) technology. In millimeter wave bands, precise circuit models and digital calibration techniques for correcting variations of CMOS analog circuits are required for commercialization. This paper describes 60 GHz and 79 GHz CMOS chipsets for multi-gigabit wireless communications and phased-array radar applications. Additionally it introduces 140 GHz CMOS integrated circuit design as future challenges toward Terahertz era.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"338 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123319971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377870
H. Majima
Bluetooth and Bluetooth Low Energy are one of the most popular wireless standards for short range communications. One of the key features is low power operation to minimize form factor of sensor nodes including battery in the Internet-of-Things (IoT) era. Our latest Bluetooth Low Energy SoC achieves -92 dBm receiver sensitivity with 6.3 mA peak current consumption. Transmitter maximum output power is 0 dBm. Transceiver architecture together with analog and digital circuit techniques and power management techniques are discussed.
{"title":"Low-power SoC design techniques for Bluetooth/Bluetooth Low Energy","authors":"H. Majima","doi":"10.1109/RFIT.2015.7377870","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377870","url":null,"abstract":"Bluetooth and Bluetooth Low Energy are one of the most popular wireless standards for short range communications. One of the key features is low power operation to minimize form factor of sensor nodes including battery in the Internet-of-Things (IoT) era. Our latest Bluetooth Low Energy SoC achieves -92 dBm receiver sensitivity with 6.3 mA peak current consumption. Transmitter maximum output power is 0 dBm. Transceiver architecture together with analog and digital circuit techniques and power management techniques are discussed.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123403619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377881
K. Agawa, I. Seto, D. Miyashita, M. Okano
TransferJet™ is an emerging high-speed close-proximity wireless communication standard, which enables a data transfer of up to 522 Mbps within a few centimeters transmission range. We have designed a fully integrated TransferJetTM SoC with a 4.48-GHz operating frequency and a 560-MHz signal bandwidth using a 65 nm CMOS technology. A module has also been developed employing 3D integration technology. The SoC with RF and digital baseband circuits is embedded in an organic resin substrate of the module to achieve a module size of 4.8 mm × 4.8 mm × 1.0 mm. Since RF signals are sensitive to the low height and small footprint of the module, we propose a waveform pre-emphasis scheme to handle the ultra-wide bandwidth and a programmable power attenuator for precise output power in the transmitter of the SoC to meet the TransferJetTM standard.
TransferJet™是一种新兴的高速近距离无线通信标准，可在几厘米的传输范围内实现高达522 Mbps的数据传输。我们设计了一个完全集成的TransferJetTM SoC，使用65纳米CMOS技术，工作频率为4.48 ghz，信号带宽为560 mhz。采用三维集成技术开发了一个模块。具有RF和数字基带电路的SoC嵌入在模块的有机树脂基板中，以实现模块尺寸为4.8 mm × 4.8 mm × 1.0 mm。由于射频信号对模块的低高度和小占地敏感，因此我们提出了一种波形预强调方案来处理超宽带和可编程功率衰减器，以在SoC的发射器中精确输出功率，以满足TransferJetTM标准。
{"title":"Robust design of CMOS wireless SoC for 3D-integrated small transferjet™ module","authors":"K. Agawa, I. Seto, D. Miyashita, M. Okano","doi":"10.1109/RFIT.2015.7377881","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377881","url":null,"abstract":"TransferJet™ is an emerging high-speed close-proximity wireless communication standard, which enables a data transfer of up to 522 Mbps within a few centimeters transmission range. We have designed a fully integrated TransferJetTM SoC with a 4.48-GHz operating frequency and a 560-MHz signal bandwidth using a 65 nm CMOS technology. A module has also been developed employing 3D integration technology. The SoC with RF and digital baseband circuits is embedded in an organic resin substrate of the module to achieve a module size of 4.8 mm × 4.8 mm × 1.0 mm. Since RF signals are sensitive to the low height and small footprint of the module, we propose a waveform pre-emphasis scheme to handle the ultra-wide bandwidth and a programmable power attenuator for precise output power in the transmitter of the SoC to meet the TransferJetTM standard.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129082488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377904
T. Ueno, Taichi Ogawa, T. Miyazaki, T. Itakura
This paper describes two DC-DC conversion techniques suitable for low-voltage mobile applications. Converters using the first technique realize high efficiency under light-load conditions by having an architecture with a simple common-source amplifier and a low-power differential amplifier. The measured efficiency of the first type of converter is 67% at an output current of 23 μA. A one-shot technique in the second type of converter reduces output-voltage fluctuation. A predetermined current is injected into the output capacitor when a load transient is detected by observing the capacitor current. This technique reduces overshoot voltage by 68% at a high-to-low load transient.
{"title":"DC-DC conversion techniques for low-voltage power supplies","authors":"T. Ueno, Taichi Ogawa, T. Miyazaki, T. Itakura","doi":"10.1109/RFIT.2015.7377904","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377904","url":null,"abstract":"This paper describes two DC-DC conversion techniques suitable for low-voltage mobile applications. Converters using the first technique realize high efficiency under light-load conditions by having an architecture with a simple common-source amplifier and a low-power differential amplifier. The measured efficiency of the first type of converter is 67% at an output current of 23 μA. A one-shot technique in the second type of converter reduces output-voltage fluctuation. A predetermined current is injected into the output capacitor when a load transient is detected by observing the capacitor current. This technique reduces overshoot voltage by 68% at a high-to-low load transient.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125401998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377875
Bo-Yu Chen, Yuan-Hung Hsiao, Huei Wang
In this paper, we present a broadband frequency doubler with harmonic rejection using 90nm CMOS process. The balanced frequency doubler adopts cascode topology with class C bias to maximize second order harmonic generation. An elliptic low pass filter is integrated inside the cascode structure to suppress the fourth and higher order harmonic power. The 3-dB bandwidth of this frequency doubler is from 42 to 90 GHz with 8 to 11 dB conversion loss under 5-dBm input drive.
{"title":"A broadband doubler with harmonic rejection in 90nm CMOS","authors":"Bo-Yu Chen, Yuan-Hung Hsiao, Huei Wang","doi":"10.1109/RFIT.2015.7377875","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377875","url":null,"abstract":"In this paper, we present a broadband frequency doubler with harmonic rejection using 90nm CMOS process. The balanced frequency doubler adopts cascode topology with class C bias to maximize second order harmonic generation. An elliptic low pass filter is integrated inside the cascode structure to suppress the fourth and higher order harmonic power. The 3-dB bandwidth of this frequency doubler is from 42 to 90 GHz with 8 to 11 dB conversion loss under 5-dBm input drive.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126183845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377930
Yudong Zhang, W. Rhee, Zhihua Wang, Taeik Kim, Hojin Park
A 0.55V 100MHz LDO-embedded ADPLL is implemented in 65nm CMOS. A digitally-controlled relaxation oscillator (DCRXO) with a variable-threshold inverter and a digital calibration circuit is designed for robust start up under ultra-low supply voltage. A ΔΣ modulated pseudo-digital LDO provides a PVT-insensitive dithered internal voltage for the DCRXO. The 100MHz ADPLL including the LDO consumes a 67μW from a 0.55V supply and achieves the phase noise of -82.9dBc/Hz at 1MHz offset frequency. The LDO achieves >20dB PSRR when sinusoidal noise is injected to the supply.
{"title":"A 0.55V 100MHz ADPLL with ΔΣ LDO and Relaxation DCO in 65nm CMOS","authors":"Yudong Zhang, W. Rhee, Zhihua Wang, Taeik Kim, Hojin Park","doi":"10.1109/RFIT.2015.7377930","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377930","url":null,"abstract":"A 0.55V 100MHz LDO-embedded ADPLL is implemented in 65nm CMOS. A digitally-controlled relaxation oscillator (DCRXO) with a variable-threshold inverter and a digital calibration circuit is designed for robust start up under ultra-low supply voltage. A ΔΣ modulated pseudo-digital LDO provides a PVT-insensitive dithered internal voltage for the DCRXO. The 100MHz ADPLL including the LDO consumes a 67μW from a 0.55V supply and achieves the phase noise of -82.9dBc/Hz at 1MHz offset frequency. The LDO achieves >20dB PSRR when sinusoidal noise is injected to the supply.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"1997 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128209226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377903
H. Hama, K. Itoh, K. Noguchi, T. Hirota, S. Makino
In this paper, analysis on the linearity of the balanced diode mixer driven by the square wave LO is described For the objective, the circuit analysis based on the diode model with the ideal switch and the resistor is indicated and the derived formula clarifies the linear operation under some conditions. Furthermore the normalized output powers and the third order distortion of the mixer are demonstrated with the square wave LO and the sinusoidal LO. This analytical result and experiments confirm the high linear characteristics of the balanced diode mixer driven by the square wave LO.
{"title":"Analysis on the linearity of the balanced diode mixer driven by the square wave LO","authors":"H. Hama, K. Itoh, K. Noguchi, T. Hirota, S. Makino","doi":"10.1109/RFIT.2015.7377903","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377903","url":null,"abstract":"In this paper, analysis on the linearity of the balanced diode mixer driven by the square wave LO is described For the objective, the circuit analysis based on the diode model with the ideal switch and the resistor is indicated and the derived formula clarifies the linear operation under some conditions. Furthermore the normalized output powers and the third order distortion of the mixer are demonstrated with the square wave LO and the sinusoidal LO. This analytical result and experiments confirm the high linear characteristics of the balanced diode mixer driven by the square wave LO.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131287816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377905
Y. Sugimoto
We introduce a method for designing switching power converter circuits with unified frequency characteristics independent of the input and output voltage settings and the load current change. Each circuit block is expressed as an equivalent small signal transfer function. Stability analysis of the total feedback loop was performed in both the continuous conduction mode (CCM) and discontinuous conduction mode (DCM). In addition, a system and circuit simulation method for switching power converters that enables fast and precise simulation of a transient response and frequency characteristics is introduced. Its features include acceleration of simulation time, and the ability to use a SPICE-like analog simulator and a behavioral simulator at the same time. We conclude that sophisticated circuit design and simulation of switching power converters are now available.
{"title":"Sophisticated circuit design and simulation method for switching power converters","authors":"Y. Sugimoto","doi":"10.1109/RFIT.2015.7377905","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377905","url":null,"abstract":"We introduce a method for designing switching power converter circuits with unified frequency characteristics independent of the input and output voltage settings and the load current change. Each circuit block is expressed as an equivalent small signal transfer function. Stability analysis of the total feedback loop was performed in both the continuous conduction mode (CCM) and discontinuous conduction mode (DCM). In addition, a system and circuit simulation method for switching power converters that enables fast and precise simulation of a transient response and frequency characteristics is introduced. Its features include acceleration of simulation time, and the ability to use a SPICE-like analog simulator and a behavioral simulator at the same time. We conclude that sophisticated circuit design and simulation of switching power converters are now available.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131473189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377900
T. Tsukahara, R. Ito, Kyosuke Arimura
This paper first describes the evolution of RF transceiver architectures, especially focusing on state-of-the-art CMOS system-on-a-chip (SoC) implementation and software-defined radios (SDRs). Because, in these modern RF transceivers, complex signal processing is indispensable for digital modulation/demodulation and side-band or image-signal rejection in frequency conversion processes, fundamentals of complex signal processing are reviewed. Finally, we propose a high-precision complex quadrature modulator suitable for modern RF transmitters using multi-symbol quadrature amplitude modulation (QAM), which features the inherent correction mechanism of local-oscillator (LO) phase and amplitude errors. Especially, a newly proposed "dual-LO-switching passive quadrature mixer" plays an important role in the LO-phase error correction.
{"title":"Complex signal processing used in modern RF transceivers","authors":"T. Tsukahara, R. Ito, Kyosuke Arimura","doi":"10.1109/RFIT.2015.7377900","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377900","url":null,"abstract":"This paper first describes the evolution of RF transceiver architectures, especially focusing on state-of-the-art CMOS system-on-a-chip (SoC) implementation and software-defined radios (SDRs). Because, in these modern RF transceivers, complex signal processing is indispensable for digital modulation/demodulation and side-band or image-signal rejection in frequency conversion processes, fundamentals of complex signal processing are reviewed. Finally, we propose a high-precision complex quadrature modulator suitable for modern RF transmitters using multi-symbol quadrature amplitude modulation (QAM), which features the inherent correction mechanism of local-oscillator (LO) phase and amplitude errors. Especially, a newly proposed \"dual-LO-switching passive quadrature mixer\" plays an important role in the LO-phase error correction.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134349182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377942
K. Itoh
This paper describes the high efficient bridge rectifier topology and its implementations in 100MHz and 2.4GHz bands. The rectifier topology realizes full-wave-rectification without large sized filters used in single-shunt type rectifiers. By employing the topology, further downsizing and integration can be achieved easily. High impedance operation with impedance transformer or the high-impedance antenna is employed to improve the rectification efficiency. 94% efficiency of the 100MHz band rectifier and 80% efficiency of the 2.4GHz rectenna are achieved. These values are the top-level performance with the commercial-based Si-SBD. Also the size of the 2.4GHz band rectifier is 4.5mm × 4.8mm that is the smallest implementation than the past works.
{"title":"RF bridge rectifier and its good possibility for wireless power transmission systems","authors":"K. Itoh","doi":"10.1109/RFIT.2015.7377942","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377942","url":null,"abstract":"This paper describes the high efficient bridge rectifier topology and its implementations in 100MHz and 2.4GHz bands. The rectifier topology realizes full-wave-rectification without large sized filters used in single-shunt type rectifiers. By employing the topology, further downsizing and integration can be achieved easily. High impedance operation with impedance transformer or the high-impedance antenna is employed to improve the rectification efficiency. 94% efficiency of the 100MHz band rectifier and 80% efficiency of the 2.4GHz rectenna are achieved. These values are the top-level performance with the commercial-based Si-SBD. Also the size of the 2.4GHz band rectifier is 4.5mm × 4.8mm that is the smallest implementation than the past works.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122208667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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