Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377891
R. Ma
GaN integrated switch-mode power amplifier with high output power, fast and efficient switching characteristic has been considered as a very suitable technology for implementing advanced digital radio transmitter. It is featured of energy-efficient and re-configurable operation. This paper reviews the recently reported works in this promising research topic. Key technical challenges on the device technology, modeling, and circuit designs are summarized. Future development trend is discussed.
{"title":"A review of recent development on digital transmitters with integrated GaN switch-mode amplifiers","authors":"R. Ma","doi":"10.1109/RFIT.2015.7377891","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377891","url":null,"abstract":"GaN integrated switch-mode power amplifier with high output power, fast and efficient switching characteristic has been considered as a very suitable technology for implementing advanced digital radio transmitter. It is featured of energy-efficient and re-configurable operation. This paper reviews the recently reported works in this promising research topic. Key technical challenges on the device technology, modeling, and circuit designs are summarized. Future development trend is discussed.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115430101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377946
Tsuyoshi Takahashi, Masaru Sato, K. Makiyama, Y. Nakasha, N. Hara, T. Iwai
We developed high-speed III-V devices for millimeter-wave receiver applications as InP-based high electron mobility transistors (HEMTs) that had a cavity structure and zero-bias GaAsSb-based heterojunction backward diodes. A high cutoff frequency (fT) of 517 GHz and minimum noise figure (NFmin) of 0.71 dB at 94 GHz were achieved for the InP-based HEMTs, even after the passivation process, by adopting the cavity structure. Since GaAsSb-based diodes that are based on p+-GaAsSb/i-InAlAs/n-InGaAs are mostly lattice-matched to InP, they can be easily integrated with InP-based low-noise amplifiers (LNAs). They indicated a sensitivity of 20,400 V/W at 94 GHz. By integrating the backward diodes with LNAs, highly sensitive receiver MMICs can be fabricated.
{"title":"High-speed III-V devices for millimeter-wave receiver applications (Invited)","authors":"Tsuyoshi Takahashi, Masaru Sato, K. Makiyama, Y. Nakasha, N. Hara, T. Iwai","doi":"10.1109/RFIT.2015.7377946","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377946","url":null,"abstract":"We developed high-speed III-V devices for millimeter-wave receiver applications as InP-based high electron mobility transistors (HEMTs) that had a cavity structure and zero-bias GaAsSb-based heterojunction backward diodes. A high cutoff frequency (fT) of 517 GHz and minimum noise figure (NFmin) of 0.71 dB at 94 GHz were achieved for the InP-based HEMTs, even after the passivation process, by adopting the cavity structure. Since GaAsSb-based diodes that are based on p+-GaAsSb/i-InAlAs/n-InGaAs are mostly lattice-matched to InP, they can be easily integrated with InP-based low-noise amplifiers (LNAs). They indicated a sensitivity of 20,400 V/W at 94 GHz. By integrating the backward diodes with LNAs, highly sensitive receiver MMICs can be fabricated.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114126114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377902
Xiao Xu, Xin Yang, Zheng Sun, T. Kurniawan, T. Yoshimasu
This paper presents a broadband single-pole double-throw (SPDT) switch IC in a 180-nm CMOS process. Back-gate voltage injection and floating body technique are utilized to improve the power handling capability, insertion loss and isolation performance, simultaneously. The fabricated SPDT switch IC has exhibited an input referred 0.3-dB compression point of 21.0 dBm, an isolation of 42.7 dB and an insertion loss of 1.1 dB for transmit mode at an operation frequency of 5.0 GHz.
{"title":"Highly linear high isolation SPDT switch IC with back-gate effect and floating body technique in 180-nm CMOS","authors":"Xiao Xu, Xin Yang, Zheng Sun, T. Kurniawan, T. Yoshimasu","doi":"10.1109/RFIT.2015.7377902","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377902","url":null,"abstract":"This paper presents a broadband single-pole double-throw (SPDT) switch IC in a 180-nm CMOS process. Back-gate voltage injection and floating body technique are utilized to improve the power handling capability, insertion loss and isolation performance, simultaneously. The fabricated SPDT switch IC has exhibited an input referred 0.3-dB compression point of 21.0 dBm, an isolation of 42.7 dB and an insertion loss of 1.1 dB for transmit mode at an operation frequency of 5.0 GHz.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125247198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377912
C. Hsieh, D. Pan, Zuo‐Min Tsai
A 60 GHz simple and small size sub-harmonic transceiver which incorporates with 45 degree phase shifter to implement higher order shift keying modulation ability is realized. The single chip transceiver can be transmitting mode or receiving mode by switching the single pole double throw (SPDT) easily. This transceiver is fabricated in a 90 nm CMOS process and occupied 2.8 mm2 areas. The measured 3 dB bandwidth of up-conversion gain and down-conversion gain is 6 GHz and 5 GHz individually.
{"title":"A 60 GHz single-chip CMOS transceiver for high-definition video transmission system application","authors":"C. Hsieh, D. Pan, Zuo‐Min Tsai","doi":"10.1109/RFIT.2015.7377912","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377912","url":null,"abstract":"A 60 GHz simple and small size sub-harmonic transceiver which incorporates with 45 degree phase shifter to implement higher order shift keying modulation ability is realized. The single chip transceiver can be transmitting mode or receiving mode by switching the single pole double throw (SPDT) easily. This transceiver is fabricated in a 90 nm CMOS process and occupied 2.8 mm2 areas. The measured 3 dB bandwidth of up-conversion gain and down-conversion gain is 6 GHz and 5 GHz individually.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122323549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377911
Yen-Chung Chiang, Yu-Chin Lin
In this paper, a three-stage low-noise amplifier (LNA) designed for V-band applications is presented. Each stage of the proposed LNA is the common-source topology with inductive degeneration for minimizing the noise figure (NF). The inductors at the gate and source terminals form a coupling structure which extends the bandwidth with a low NF level. This proposed LNA is implemented in the 90-nm CMOS process technology, which achieves a peak gain of 16.48 dB, a minimum NF of 4.5 dB, and an input PidB of -18.7 dBm. The proposed LNA consumes 17.47 mW power from a 1.2-V voltage supply.
{"title":"A low noise amplifier with coupled matching structure for V-band applications","authors":"Yen-Chung Chiang, Yu-Chin Lin","doi":"10.1109/RFIT.2015.7377911","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377911","url":null,"abstract":"In this paper, a three-stage low-noise amplifier (LNA) designed for V-band applications is presented. Each stage of the proposed LNA is the common-source topology with inductive degeneration for minimizing the noise figure (NF). The inductors at the gate and source terminals form a coupling structure which extends the bandwidth with a low NF level. This proposed LNA is implemented in the 90-nm CMOS process technology, which achieves a peak gain of 16.48 dB, a minimum NF of 4.5 dB, and an input PidB of -18.7 dBm. The proposed LNA consumes 17.47 mW power from a 1.2-V voltage supply.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114249332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377925
Kojiro Tokonami, Kaoru Kohira, H. Ishikuro
In this paper, a high-speed current steering DAC with wave monitor circuit is proposed. Comparator-based wave monitor circuit makes it possible to detect a glitch and adjust the skew of each bit digital signal. Fabricated test chip in 40nm-CMOS demonstrates the performance improvement by glitch detection and skew adjusting. At 1GS/sec, the fabricated DAC achieved ENOB of 5.17 bit and power consumption of 2.38mW.
{"title":"Wave monitor for glitch detection and skew adjusting in high-speed DAC","authors":"Kojiro Tokonami, Kaoru Kohira, H. Ishikuro","doi":"10.1109/RFIT.2015.7377925","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377925","url":null,"abstract":"In this paper, a high-speed current steering DAC with wave monitor circuit is proposed. Comparator-based wave monitor circuit makes it possible to detect a glitch and adjust the skew of each bit digital signal. Fabricated test chip in 40nm-CMOS demonstrates the performance improvement by glitch detection and skew adjusting. At 1GS/sec, the fabricated DAC achieved ENOB of 5.17 bit and power consumption of 2.38mW.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122077704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377892
H. Kayano
We have developed a cryogenic low noise amplifier (LNA) for phased array antenna. By using this cryogenic LNA, a low noise receiving antenna can be easily available for wireless applications such as radar systems, communication systems, and so on. In this paper, we describe an S-band cryogenic LNA with an RF interfaces having both low loss characteristic and thermal isolation characteristic. The RF interface is realized by coupling resonators with vacuum gap of 1 mm and also has narrow band characteristic. The noise temperature of the cryogenic LNA at 77 K was improved to less than 1/5 as compared with the noise temperature of the same LNA at room temperature.
{"title":"Cryogenic low noise amplifier for phased array antenna","authors":"H. Kayano","doi":"10.1109/RFIT.2015.7377892","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377892","url":null,"abstract":"We have developed a cryogenic low noise amplifier (LNA) for phased array antenna. By using this cryogenic LNA, a low noise receiving antenna can be easily available for wireless applications such as radar systems, communication systems, and so on. In this paper, we describe an S-band cryogenic LNA with an RF interfaces having both low loss characteristic and thermal isolation characteristic. The RF interface is realized by coupling resonators with vacuum gap of 1 mm and also has narrow band characteristic. The noise temperature of the cryogenic LNA at 77 K was improved to less than 1/5 as compared with the noise temperature of the same LNA at room temperature.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114256683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377877
Dong Huang, Lei Zhang, Di Li, Li Zhang, Yan Wang
This paper presents a 57-66GHz 6-bit switch type phase shifter fabricated in 65nm CMOS technology. The proposed phase shifter achieves a 6-bit resolution and a measured root mean square phase error of less than 2.3°, while the maximal insertion loss flatness is ±1.4dB. For all 64 states, the insertion loss is -20dB±3dB including pad loss over 57-66GHz. To the best of our knowledge, this is the first reported 6-bit 60GHz phase shifter in CMOS technology.
{"title":"A 60GHz 360° digitally controlled phase shifter with 6-bit resolution and 2.3° maximal rms phase error in 65nm CMOS technology","authors":"Dong Huang, Lei Zhang, Di Li, Li Zhang, Yan Wang","doi":"10.1109/RFIT.2015.7377877","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377877","url":null,"abstract":"This paper presents a 57-66GHz 6-bit switch type phase shifter fabricated in 65nm CMOS technology. The proposed phase shifter achieves a 6-bit resolution and a measured root mean square phase error of less than 2.3°, while the maximal insertion loss flatness is ±1.4dB. For all 64 states, the insertion loss is -20dB±3dB including pad loss over 57-66GHz. To the best of our knowledge, this is the first reported 6-bit 60GHz phase shifter in CMOS technology.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115911752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377909
M. Kishihara, M. Murakami, A. Yamaguchi, Y. Utsumi, I. Ohta
It has been reported that the SR (synchrotron radiation) etching process is useful to construct PTFE-based microstructures. This paper treats a trial fabrication of the PTFE-based E-plane waveguide coupler for short millimeter-wave based on the SR etching process of PTFE, with the aim of developing integrated waveguide circuits. First, a cavity-type 3-dB directional coupler is designed at 180 GHz. In this paper, an integrated PTFE pattern, in which the two 3-dB couplers and the matching section are cascaded, is fabricated. Then, the frequency characteristics of the PTFE-based E-plane waveguide coupler are measured, and the validity of the fabrication process is verified.
{"title":"Trial fabrication of PTFE-based E-plane waveguide coupler for short millimeter-wave by SR etching","authors":"M. Kishihara, M. Murakami, A. Yamaguchi, Y. Utsumi, I. Ohta","doi":"10.1109/RFIT.2015.7377909","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377909","url":null,"abstract":"It has been reported that the SR (synchrotron radiation) etching process is useful to construct PTFE-based microstructures. This paper treats a trial fabrication of the PTFE-based E-plane waveguide coupler for short millimeter-wave based on the SR etching process of PTFE, with the aim of developing integrated waveguide circuits. First, a cavity-type 3-dB directional coupler is designed at 180 GHz. In this paper, an integrated PTFE pattern, in which the two 3-dB couplers and the matching section are cascaded, is fabricated. Then, the frequency characteristics of the PTFE-based E-plane waveguide coupler are measured, and the validity of the fabrication process is verified.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130731111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377933
Toshiyuki Tanaka, Marika Nakamura, Y. Yamaguchi, M. Tsuru, Yasuki Aihara, Atsushi Yamamoto, Y. Homma, E. Taniguchi
Microwave wireless power transmission systems require a high RF-DC conversion efficiency rectifier at input power such as 1 W. To meet this requirement, a rectifying device with high breakdown voltage is developed. This paper describes a fabricated high breakdown voltage GaAs Schottky Barrier Diode (SBD) as the rectifying device. The fabricated GaAs SBD at low doping concentration of 2.6×1016 cm-3 achieves breakdown voltage of 23.5 V and the conversion efficiency of 77.2% at input power of 27 dBm under condition without harmonic tuning technique which is agreed with simulation result. When harmonic tuning technique is adopted, a 5.8 GHz-band singleshunt rectifier with the fabricated GaAs SBD achieves the conversion efficiency of 81.7% at input power of 27 dBm in simulation. This conversion efficiency is the best performance at around 1 W input power and C-band to our knowledge.
{"title":"High breakdown voltage GaAs schottky diode for a high efficiency rectifier in microwave power transmission systems","authors":"Toshiyuki Tanaka, Marika Nakamura, Y. Yamaguchi, M. Tsuru, Yasuki Aihara, Atsushi Yamamoto, Y. Homma, E. Taniguchi","doi":"10.1109/RFIT.2015.7377933","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377933","url":null,"abstract":"Microwave wireless power transmission systems require a high RF-DC conversion efficiency rectifier at input power such as 1 W. To meet this requirement, a rectifying device with high breakdown voltage is developed. This paper describes a fabricated high breakdown voltage GaAs Schottky Barrier Diode (SBD) as the rectifying device. The fabricated GaAs SBD at low doping concentration of 2.6×1016 cm-3 achieves breakdown voltage of 23.5 V and the conversion efficiency of 77.2% at input power of 27 dBm under condition without harmonic tuning technique which is agreed with simulation result. When harmonic tuning technique is adopted, a 5.8 GHz-band singleshunt rectifier with the fabricated GaAs SBD achieves the conversion efficiency of 81.7% at input power of 27 dBm in simulation. This conversion efficiency is the best performance at around 1 W input power and C-band to our knowledge.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125256050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：