Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993075
A. Droitcour, O. Boric-Lubecke, V. Lubecke, Jenshan Lin
A fully integrated direct conversion Doppler radar that detects heart and respiration movement at a distance of 50 cm is described. The 1.6 GHz transceiver is implemented in both CMOS and BiCMOS technologies, with each chip occupying 14 mm/sup 2/ using a 0.25 μm silicon processes. The effects on system sensitivity of phase noise at small offset frequencies with range correlation are assessed.
{"title":"0.25 /spl mu/m CMOS and BiCMOS single-chip direct-conversion Doppler radars for remote sensing of vital signs","authors":"A. Droitcour, O. Boric-Lubecke, V. Lubecke, Jenshan Lin","doi":"10.1109/ISSCC.2002.993075","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993075","url":null,"abstract":"A fully integrated direct conversion Doppler radar that detects heart and respiration movement at a distance of 50 cm is described. The 1.6 GHz transceiver is implemented in both CMOS and BiCMOS technologies, with each chip occupying 14 mm/sup 2/ using a 0.25 μm silicon processes. The effects on system sensitivity of phase noise at small offset frequencies with range correlation are assessed.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129010889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992945
T. Yoshikawk, T. Yoshida, T. Ebuchi, Y. Arima, T. Iwata, K. Nishimura, H. Kimura, Y. Komatsu, H. Yamauchi
A physical layer LSI has one DS-port and two /spl beta/ports in accordance with IEEE1394-2000 and P1394b Draft 1.01 respectively. The 0.25 /spl mu/m CMOS LSI realizes 800 Mb/s and 1.2 km peer-to-peer IEEE1394 networking through /spl beta/port. Each /spl beta/port requires 180 mW active power and is treated as ASIC macro for future large system integration.
{"title":"An 800 Mb/s physical layer LSI with hybrid port architecture for consumer electronics networking","authors":"T. Yoshikawk, T. Yoshida, T. Ebuchi, Y. Arima, T. Iwata, K. Nishimura, H. Kimura, Y. Komatsu, H. Yamauchi","doi":"10.1109/ISSCC.2002.992945","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992945","url":null,"abstract":"A physical layer LSI has one DS-port and two /spl beta/ports in accordance with IEEE1394-2000 and P1394b Draft 1.01 respectively. The 0.25 /spl mu/m CMOS LSI realizes 800 Mb/s and 1.2 km peer-to-peer IEEE1394 networking through /spl beta/port. Each /spl beta/port requires 180 mW active power and is treated as ASIC macro for future large system integration.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122365038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993038
A. Mantyniemi, T. Rahkonen, J. Kostamovaara
An integrated 9-channel time digitizer with 30 ps RMS resolution, 496 /spl mu/s range, and 50 mW power consumption in 0.6 /spl mu/m CMOS uses a three-stage delay line interpolation and delay-generation principle that divides the 66 MHz clock period into 512 bins using only 45 delay elements.
{"title":"An integrated 9-channel time digitizer with 30 ps resolution","authors":"A. Mantyniemi, T. Rahkonen, J. Kostamovaara","doi":"10.1109/ISSCC.2002.993038","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993038","url":null,"abstract":"An integrated 9-channel time digitizer with 30 ps RMS resolution, 496 /spl mu/s range, and 50 mW power consumption in 0.6 /spl mu/m CMOS uses a three-stage delay line interpolation and delay-generation principle that divides the 66 MHz clock period into 512 bins using only 45 delay elements.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130689632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993068
R. Preston, R. Badeau, D. Bailey, Shane L. Bell, L. Biro, W. Bowhill, D. Dever, S. Felix, R. Gammack, V. Germini, M. Gowan, P. Gronowski, D. B. Jackson, S. Mehta, S. Morton, J. Pickholtz, M. Reilly, M. Smith
A 250M transistor microprocessor implements the Alpha instruction set and features 8-wide superscalar issue and simultaneous multithreading in a 0.125/spl mu/m SOI process. Performance is estimated at over three times that of the previous design.
{"title":"Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading","authors":"R. Preston, R. Badeau, D. Bailey, Shane L. Bell, L. Biro, W. Bowhill, D. Dever, S. Felix, R. Gammack, V. Germini, M. Gowan, P. Gronowski, D. B. Jackson, S. Mehta, S. Morton, J. Pickholtz, M. Reilly, M. Smith","doi":"10.1109/ISSCC.2002.993068","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993068","url":null,"abstract":"A 250M transistor microprocessor implements the Alpha instruction set and features 8-wide superscalar issue and simultaneous multithreading in a 0.125/spl mu/m SOI process. Performance is estimated at over three times that of the previous design.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130984444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993051
M. Tiebout, H. Wohlmuth, W. Simburger
A fully integrated 51 GHz VCO is implemented in 0.12 /spl mu/m standard CMOS with 6 metal levels. Core power consumption is 1 mW at 1V supply due to the optimized high-inductance tank. The tuning range is 1.4 GHz. Measured phase noise is -85 dBc/Hz at 1 MHz offset.
{"title":"A 1 V 51GHz fully-integrated VCO in 0.12 /spl mu/m CMOS","authors":"M. Tiebout, H. Wohlmuth, W. Simburger","doi":"10.1109/ISSCC.2002.993051","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993051","url":null,"abstract":"A fully integrated 51 GHz VCO is implemented in 0.12 /spl mu/m standard CMOS with 6 metal levels. Core power consumption is 1 mW at 1V supply due to the optimized high-inductance tank. The tuning range is 1.4 GHz. Measured phase noise is -85 dBc/Hz at 1 MHz offset.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131293510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992969
Leilei Song, Meng-Lin Yu, M. Shaffer
Two forward error-correcting devices for OC-48/192/768 are implemented in 1.5 V 0.6 /spl mu/m CMOS. A 10 Gb/s (or Quad 2.5 Gb/s) device with 424k-gate Reed-Solomon core consumes 343 mW. A 40 Gb/s device contains 364k-gates and consumes 361 mW.
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992103
F. Yang, J. O'Neill, P. Larsson, D. Inglis, J. Othmer
An 8-channel serial link transceiver realizes 20 Gb/s full duplex total I/O throughput with <700 mW dissipation from a 1.5 V supply and occupies 2 mm/sup 2/ in 0.16 /spl mu/m CMOS. An analog DLL allows tracking of frequency offset up to 400 ppm. The receiver, employing an integrate-and-dump front-end, achieves 30 mVpp sensitivity.
{"title":"A 1.5 V 86 mW/ch 8-channel 622-3125 Mb/s/ch CMOS SerDes macrocell with selectable mux/demux ratio","authors":"F. Yang, J. O'Neill, P. Larsson, D. Inglis, J. Othmer","doi":"10.1109/ISSCC.2002.992103","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992103","url":null,"abstract":"An 8-channel serial link transceiver realizes 20 Gb/s full duplex total I/O throughput with <700 mW dissipation from a 1.5 V supply and occupies 2 mm/sup 2/ in 0.16 /spl mu/m CMOS. An analog DLL allows tracking of frequency offset up to 400 ppm. The receiver, employing an integrate-and-dump front-end, achieves 30 mVpp sensitivity.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124676261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992101
D. Redmond, M. Fitzgibbon, A. Bannon, D. Hobbs, Chunhe Zhao, K. Kase, J. Chan, M. Priel, K. Traylor, K. Tilley
A dual-core baseband processor IC for GSM/GPRS cellular phone applications is built in a 0.13 /spl mu/m CMOS process with 5 levels of copper interconnect and contains a high level of mixed-signal integration which includes: 1 GHz CMOS synthesizer, 10 b general-purpose ADC, two 14 b ADCs, power amplifier controller, and 13 b voice codec.
用于GSM/GPRS蜂窝电话应用的双核基带处理器IC采用0.13 /spl mu/m CMOS工艺，5级铜互连，包含高水平的混合信号集成，包括:1 GHz CMOS合成器，10 b通用ADC，两个14 b ADC，功率放大器控制器和13 b语音编解码器。
{"title":"A GSM/GPRS mixed-signal baseband IC","authors":"D. Redmond, M. Fitzgibbon, A. Bannon, D. Hobbs, Chunhe Zhao, K. Kase, J. Chan, M. Priel, K. Traylor, K. Tilley","doi":"10.1109/ISSCC.2002.992101","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992101","url":null,"abstract":"A dual-core baseband processor IC for GSM/GPRS cellular phone applications is built in a 0.13 /spl mu/m CMOS process with 5 levels of copper interconnect and contains a high level of mixed-signal integration which includes: 1 GHz CMOS synthesizer, 10 b general-purpose ADC, two 14 b ADCs, power amplifier controller, and 13 b voice codec.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124745090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993007
S. Goldstein, D. Rosewater
A reconfigurable architecture is based on chemically-assembled electronic nanotechnology (CAEN). A molecular latch based on molecular RTDs provides I/O-isolation, voltage restoration, and fan-out using only 2-terminal devices.
{"title":"Digital logic using molecular electronics","authors":"S. Goldstein, D. Rosewater","doi":"10.1109/ISSCC.2002.993007","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993007","url":null,"abstract":"A reconfigurable architecture is based on chemically-assembled electronic nanotechnology (CAEN). A molecular latch based on molecular RTDs provides I/O-isolation, voltage restoration, and fan-out using only 2-terminal devices.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122798392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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