Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993080
M. Wu, D. Hah, P. Patterson, H. Toshiyoshi
The state-of-the-art of optical MEMS devices for optical networking applications is reviewed, and a scanning micromirror with angular vertical comb (AVC) actuators is introduced. The AVC scanner uses a single etching process and is completely self-aligned. It has 50% larger scan angle than conventional vertical comb devices. Resonant frequency is 630 Hz.
{"title":"Microelectromechanical scanning devices for optical networking applications","authors":"M. Wu, D. Hah, P. Patterson, H. Toshiyoshi","doi":"10.1109/ISSCC.2002.993080","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993080","url":null,"abstract":"The state-of-the-art of optical MEMS devices for optical networking applications is reviewed, and a scanning micromirror with angular vertical comb (AVC) actuators is introduced. The AVC scanner uses a single etching process and is completely self-aligned. It has 50% larger scan angle than conventional vertical comb devices. Resonant frequency is 630 Hz.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125288610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993099
M. Steyaert, P. Coppejans, W. De Cock, P. Leroux, P. Vancorenland
A 0.25 /spl mu/m CMOS quadrature complex bandpass low-IF GPS receiver includes an LNA, PLL, mixer and a continuous-time /spl Delta//spl Sigma/ ADC. The chip has -130 dBm input sensitivity, 62 dB DR, and -32 dB IMRR, while consuming 40 mW from 2 V supply. The chip is 9 mm/sup 2/.
一个0.25 /spl mu/m CMOS正交复杂带通低中频GPS接收机包括一个LNA、锁相环、混频器和一个连续时间/spl Delta//spl Sigma/ ADC。该芯片具有-130 dBm的输入灵敏度，62 dB DR和-32 dB IMRR，同时从2v电源消耗40 mW。芯片是9毫米/sup 2/。
{"title":"A fully-integrated GPS receiver front-end with 40 mW power consumption","authors":"M. Steyaert, P. Coppejans, W. De Cock, P. Leroux, P. Vancorenland","doi":"10.1109/ISSCC.2002.993099","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993099","url":null,"abstract":"A 0.25 /spl mu/m CMOS quadrature complex bandpass low-IF GPS receiver includes an LNA, PLL, mixer and a continuous-time /spl Delta//spl Sigma/ ADC. The chip has -130 dBm input sensitivity, 62 dB DR, and -32 dB IMRR, while consuming 40 mW from 2 V supply. The chip is 9 mm/sup 2/.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124551337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993065
W. De Wilde, N. Scantamburlo, M. Combe, J. Van Leeuwe, K. Doorakkers, Y. Mazoyer, C. Renous, R. Petigny, A. Bonin, B. Bayracki, B. Belhi, E. Moons, J. Sevenhans
A 12MHz 760mW analog front end for DMT-based VDSL integrates all active components except line driver in a single BiCMOS 0.35/spl mu/m ASIC. When fully active, the ASIC dissipates 480mW at 3.3V supply, providing resolution equivalent to 12b without trimming.
{"title":"Analog front end for DMT-based VDSL","authors":"W. De Wilde, N. Scantamburlo, M. Combe, J. Van Leeuwe, K. Doorakkers, Y. Mazoyer, C. Renous, R. Petigny, A. Bonin, B. Bayracki, B. Belhi, E. Moons, J. Sevenhans","doi":"10.1109/ISSCC.2002.993065","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993065","url":null,"abstract":"A 12MHz 760mW analog front end for DMT-based VDSL integrates all active components except line driver in a single BiCMOS 0.35/spl mu/m ASIC. When fully active, the ASIC dissipates 480mW at 3.3V supply, providing resolution equivalent to 12b without trimming.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134481339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993072
M. Nakajima, T. Yamamoto, S. Ozaki, I. Sezaki, T. Kanakogi, T. Furuzono, T. Sakamoto, T. Aruga, M. Sumita, M. Tsutsumi, A. Ueda, T. Ichinomiya
A 32b RISC microprocessor core for Digital TV SoC occupies 14.8mm/sup 2/ in 0.13/spl mu/m CMOS with six Cu layers. The core runs at 400MHz with 500mW average dissipation at 1.35V. The integrated 4.0GB/s 3/spl times/4 cross-bar bus switch improves sustained system performance efficiency by 1.75 times.
{"title":"A 400MHz 32b embedded microprocessor core AM34-1 with 4.0GB/s cross-bar bus switch for SoC","authors":"M. Nakajima, T. Yamamoto, S. Ozaki, I. Sezaki, T. Kanakogi, T. Furuzono, T. Sakamoto, T. Aruga, M. Sumita, M. Tsutsumi, A. Ueda, T. Ichinomiya","doi":"10.1109/ISSCC.2002.993072","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993072","url":null,"abstract":"A 32b RISC microprocessor core for Digital TV SoC occupies 14.8mm/sup 2/ in 0.13/spl mu/m CMOS with six Cu layers. The core runs at 400MHz with 500mW average dissipation at 1.35V. The integrated 4.0GB/s 3/spl times/4 cross-bar bus switch improves sustained system performance efficiency by 1.75 times.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134266006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992213
Jun Cao, A. Momtaz, K. Vakilian, M.M. Green, D. Chung, K. Jen, M. Caresosa, B. Tan, I. Fujimori, A. Hairapetian
A fully integrated OC-192 multi-rate (9.95Gb/s-10.71Gb/s) receiver uses standard 0.18/spl mu/m CMOS. The circuit consists of an input amplifier, CDR, 1:16 demux and 18 LVDS drivers. The chip exceeds SONET jitter tolerance spec by >100%. Recovered 10Gb/s clock jitter is <4mUl(rms). The input sensitivity is <50mV with 870mW at 1.8V.
{"title":"OC-192 receiver in standard 0.18/spl mu/m CMOS","authors":"Jun Cao, A. Momtaz, K. Vakilian, M.M. Green, D. Chung, K. Jen, M. Caresosa, B. Tan, I. Fujimori, A. Hairapetian","doi":"10.1109/ISSCC.2002.992213","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992213","url":null,"abstract":"A fully integrated OC-192 multi-rate (9.95Gb/s-10.71Gb/s) receiver uses standard 0.18/spl mu/m CMOS. The circuit consists of an input amplifier, CDR, 1:16 demux and 18 LVDS drivers. The chip exceeds SONET jitter tolerance spec by >100%. Recovered 10Gb/s clock jitter is <4mUl(rms). The input sensitivity is <50mV with 870mW at 1.8V.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129203376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992963
D. Bradley, P. Mahoney, B. Stackhouse
A 16 kB four-ported physically addressed cache to be placed on a 64 b Itanium microprocessor operates at 1.2 GHz with 19.2 GB/s peak bandwidth. Circuit and microarchitectural techniques are optimized to allow a single-cycle read access latency. The cache occupies 3.2×1.8 mm/sup 2/ in a 0.18 μm CMOS process.
{"title":"The 16 kB single-cycle read access cache on a next-generation 64 b Itanium microprocessor","authors":"D. Bradley, P. Mahoney, B. Stackhouse","doi":"10.1109/ISSCC.2002.992963","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992963","url":null,"abstract":"A 16 kB four-ported physically addressed cache to be placed on a 64 b Itanium microprocessor operates at 1.2 GHz with 19.2 GB/s peak bandwidth. Circuit and microarchitectural techniques are optimized to allow a single-cycle read access latency. The cache occupies 3.2×1.8 mm/sup 2/ in a 0.18 μm CMOS process.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129045018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993054
G. Gómez, B. Haroun
A 2/sup nd/ order multi-level /spl Sigma//spl Delta/ A/D converter for low-power multi-standard wireless receivers, in a single-poly 0.13 /spl mu/m digital CMOS process, has 79/50 dB dynamic range for GSM/WCDMA. The 0.2 mm/sup 2/ chip consumes 2.4/2.9 mW at 1.5 V.
{"title":"A 1.5 V 2.4/2.9 mW 79/50 dB DR /spl Sigma//spl Delta/ modulator for GSM/WCDMA in a 0.13 /spl mu/m digital process","authors":"G. Gómez, B. Haroun","doi":"10.1109/ISSCC.2002.993054","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993054","url":null,"abstract":"A 2/sup nd/ order multi-level /spl Sigma//spl Delta/ A/D converter for low-power multi-standard wireless receivers, in a single-poly 0.13 /spl mu/m digital CMOS process, has 79/50 dB dynamic range for GSM/WCDMA. The 0.2 mm/sup 2/ chip consumes 2.4/2.9 mW at 1.5 V.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130501280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993057
S. Kulhalli, V. Penkota, R. Asv
A 0.6/spl mu/m double-poly CMOS 12b ADC uses a number of different techniques to obtain low power. The ADC achieves 68dB SNR at 21 MSample/s, consuming 30mW at 2.7V. Die area is 2.56mm/sup 2/.
{"title":"A 30mW 12b 21MSample/s pipelined CMOS ADC","authors":"S. Kulhalli, V. Penkota, R. Asv","doi":"10.1109/ISSCC.2002.993057","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993057","url":null,"abstract":"A 0.6/spl mu/m double-poly CMOS 12b ADC uses a number of different techniques to obtain low power. The ADC achieves 68dB SNR at 21 MSample/s, consuming 30mW at 2.7V. Die area is 2.56mm/sup 2/.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117331803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993004
James E. Smith, Ashutosh S. Dhodapkar
Co-designed virtual machines provide hardware designers with a hidden layer of software that can be used to manage configurable hardware units. A reconfiguration algorithm based on a mechanism for identifying recurring program phases provides power savings in caches and predictors up to 60%, without significantly affecting performance.
{"title":"Dynamic microarchitecture adaptation via co-designed virtual machines","authors":"James E. Smith, Ashutosh S. Dhodapkar","doi":"10.1109/ISSCC.2002.993004","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993004","url":null,"abstract":"Co-designed virtual machines provide hardware designers with a hidden layer of software that can be used to manage configurable hardware units. A reconfiguration algorithm based on a mechanism for identifying recurring program phases provides power savings in caches and predictors up to 60%, without significantly affecting performance.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115989935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992217
T. Takeshita, T. Nishimura
An optical receiver IC for 622 Mb/s that integrates transimpedance amplifier, post amplifier, and clock recovery uses a BiCMOS process. The single-chip receiver achieves dynamic range sensitivity from -29.4 to 0 dBm. A PLL circuit without reference-clock tolerates input with duty-cycle distortion from 70 to 130%.
{"title":"A 622 Mb/s fully-integrated optical IC with a wide range input","authors":"T. Takeshita, T. Nishimura","doi":"10.1109/ISSCC.2002.992217","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992217","url":null,"abstract":"An optical receiver IC for 622 Mb/s that integrates transimpedance amplifier, post amplifier, and clock recovery uses a BiCMOS process. The single-chip receiver achieves dynamic range sensitivity from -29.4 to 0 dBm. A PLL circuit without reference-clock tolerates input with duty-cycle distortion from 70 to 130%.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116225019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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