Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993080
M. Wu, D. Hah, P. Patterson, H. Toshiyoshi
The state-of-the-art of optical MEMS devices for optical networking applications is reviewed, and a scanning micromirror with angular vertical comb (AVC) actuators is introduced. The AVC scanner uses a single etching process and is completely self-aligned. It has 50% larger scan angle than conventional vertical comb devices. Resonant frequency is 630 Hz.
{"title":"Microelectromechanical scanning devices for optical networking applications","authors":"M. Wu, D. Hah, P. Patterson, H. Toshiyoshi","doi":"10.1109/ISSCC.2002.993080","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993080","url":null,"abstract":"The state-of-the-art of optical MEMS devices for optical networking applications is reviewed, and a scanning micromirror with angular vertical comb (AVC) actuators is introduced. The AVC scanner uses a single etching process and is completely self-aligned. It has 50% larger scan angle than conventional vertical comb devices. Resonant frequency is 630 Hz.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125288610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993103
S. Levantino, C. Samori, M. Banu, Jack Glas, V. Boccuzzi
An IF-sampling technique rejects even-order alias channels. A 0.25 /spl mu/m CMOS test chip demonstrates 27 dB anti-aliasing rejection, 70 dB dynamic range, and -121 dBm/Hz noise floor, for a 377 MHz IF GSM signal, with 52 MHz sampling rate.
{"title":"A CMOS IF sampling circuit with reduced aliasing for wireless applications","authors":"S. Levantino, C. Samori, M. Banu, Jack Glas, V. Boccuzzi","doi":"10.1109/ISSCC.2002.993103","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993103","url":null,"abstract":"An IF-sampling technique rejects even-order alias channels. A 0.25 /spl mu/m CMOS test chip demonstrates 27 dB anti-aliasing rejection, 70 dB dynamic range, and -121 dBm/Hz noise floor, for a 377 MHz IF GSM signal, with 52 MHz sampling rate.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129923791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993108
R. Rogenmoser, L. O'Donnell, S. Nishimoto
A floating-point coprocessor, part of a MIPS64 dual-processor SOC, consists of a 32/spl times/64b register file and two pipes each with a multiplier, an adder, and a fast 3D approximation unit. It operates up to 1 GHz at 1.3 W, measures 4.74 mm/sup 2/ in 0.13 /spl mu/m CMOS, and has peak performance of 8 GFlops per CPU and 16 GFlops on the dual-processor SOC.
{"title":"A dual-issue floating-point coprocessor with SIMD architecture and fast 3D functions","authors":"R. Rogenmoser, L. O'Donnell, S. Nishimoto","doi":"10.1109/ISSCC.2002.993108","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993108","url":null,"abstract":"A floating-point coprocessor, part of a MIPS64 dual-processor SOC, consists of a 32/spl times/64b register file and two pipes each with a multiplier, an adder, and a fast 3D approximation unit. It operates up to 1 GHz at 1.3 W, measures 4.74 mm/sup 2/ in 0.13 /spl mu/m CMOS, and has peak performance of 8 GFlops per CPU and 16 GFlops on the dual-processor SOC.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130629436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993072
M. Nakajima, T. Yamamoto, S. Ozaki, I. Sezaki, T. Kanakogi, T. Furuzono, T. Sakamoto, T. Aruga, M. Sumita, M. Tsutsumi, A. Ueda, T. Ichinomiya
A 32b RISC microprocessor core for Digital TV SoC occupies 14.8mm/sup 2/ in 0.13/spl mu/m CMOS with six Cu layers. The core runs at 400MHz with 500mW average dissipation at 1.35V. The integrated 4.0GB/s 3/spl times/4 cross-bar bus switch improves sustained system performance efficiency by 1.75 times.
{"title":"A 400MHz 32b embedded microprocessor core AM34-1 with 4.0GB/s cross-bar bus switch for SoC","authors":"M. Nakajima, T. Yamamoto, S. Ozaki, I. Sezaki, T. Kanakogi, T. Furuzono, T. Sakamoto, T. Aruga, M. Sumita, M. Tsutsumi, A. Ueda, T. Ichinomiya","doi":"10.1109/ISSCC.2002.993072","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993072","url":null,"abstract":"A 32b RISC microprocessor core for Digital TV SoC occupies 14.8mm/sup 2/ in 0.13/spl mu/m CMOS with six Cu layers. The core runs at 400MHz with 500mW average dissipation at 1.35V. The integrated 4.0GB/s 3/spl times/4 cross-bar bus switch improves sustained system performance efficiency by 1.75 times.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134266006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993054
G. Gómez, B. Haroun
A 2/sup nd/ order multi-level /spl Sigma//spl Delta/ A/D converter for low-power multi-standard wireless receivers, in a single-poly 0.13 /spl mu/m digital CMOS process, has 79/50 dB dynamic range for GSM/WCDMA. The 0.2 mm/sup 2/ chip consumes 2.4/2.9 mW at 1.5 V.
{"title":"A 1.5 V 2.4/2.9 mW 79/50 dB DR /spl Sigma//spl Delta/ modulator for GSM/WCDMA in a 0.13 /spl mu/m digital process","authors":"G. Gómez, B. Haroun","doi":"10.1109/ISSCC.2002.993054","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993054","url":null,"abstract":"A 2/sup nd/ order multi-level /spl Sigma//spl Delta/ A/D converter for low-power multi-standard wireless receivers, in a single-poly 0.13 /spl mu/m digital CMOS process, has 79/50 dB dynamic range for GSM/WCDMA. The 0.2 mm/sup 2/ chip consumes 2.4/2.9 mW at 1.5 V.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130501280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993078
S. Shigematsu, K. Fujii, H. Morimura, T. Hatano, M. Nakanishi, T. Adachi, N. Ikeda, T. Shimamura, Katsuyuki Machida, Y. Okazaki, H. Kyuragi
A 500-dpi 224×256-pixel single-chip fingerprint identification LSI adapts the sensing circuit to a finger and performs pixel-parallel image processing and rotation in a pixel array. A test chip achieves 2 ms 10 mW sensing, 41 ms 19.2 mW identification, and practical identification accuracy at 2.5 V, 5 MHz.
500 dpi 224×256-pixel单芯片指纹识别LSI将传感电路适配到手指上，并在像素阵列中进行像素并行图像处理和旋转。测试芯片在2.5 V, 5 MHz下实现2 ms 10mw的传感，41 ms 19.2 mW的识别，具有实用的识别精度。
{"title":"A 500 dpi 224/spl times/256-pixel single-chip fingerprint identification LSI with pixel-parallel image enhancement and rotation schemes","authors":"S. Shigematsu, K. Fujii, H. Morimura, T. Hatano, M. Nakanishi, T. Adachi, N. Ikeda, T. Shimamura, Katsuyuki Machida, Y. Okazaki, H. Kyuragi","doi":"10.1109/ISSCC.2002.993078","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993078","url":null,"abstract":"A 500-dpi 224×256-pixel single-chip fingerprint identification LSI adapts the sensing circuit to a finger and performs pixel-parallel image processing and rotation in a pixel array. A test chip achieves 2 ms 10 mW sensing, 41 ms 19.2 mW identification, and practical identification accuracy at 2.5 V, 5 MHz.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115986639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993065
W. De Wilde, N. Scantamburlo, M. Combe, J. Van Leeuwe, K. Doorakkers, Y. Mazoyer, C. Renous, R. Petigny, A. Bonin, B. Bayracki, B. Belhi, E. Moons, J. Sevenhans
A 12MHz 760mW analog front end for DMT-based VDSL integrates all active components except line driver in a single BiCMOS 0.35/spl mu/m ASIC. When fully active, the ASIC dissipates 480mW at 3.3V supply, providing resolution equivalent to 12b without trimming.
{"title":"Analog front end for DMT-based VDSL","authors":"W. De Wilde, N. Scantamburlo, M. Combe, J. Van Leeuwe, K. Doorakkers, Y. Mazoyer, C. Renous, R. Petigny, A. Bonin, B. Bayracki, B. Belhi, E. Moons, J. Sevenhans","doi":"10.1109/ISSCC.2002.993065","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993065","url":null,"abstract":"A 12MHz 760mW analog front end for DMT-based VDSL integrates all active components except line driver in a single BiCMOS 0.35/spl mu/m ASIC. When fully active, the ASIC dissipates 480mW at 3.3V supply, providing resolution equivalent to 12b without trimming.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134481339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993015
Ruoxin Jiang, T. Fiez
A fifth-order single-stage ΔΣ modulator achieves 14 b resolution with 8× OSR and 4 MHz conversion bandwidth in a 1.8 V 0.18 μm CMOS process. The DC gain of the internal op amps is 43 dB. It occupies 1.3×2.2 mm/sup 2/ and consumes 102 mW analog power and 47 mW digital power.
{"title":"A 1.8 V 14 b /spl Delta//spl Sigma/ A/D converter with 4MSamples/s conversion","authors":"Ruoxin Jiang, T. Fiez","doi":"10.1109/ISSCC.2002.993015","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993015","url":null,"abstract":"A fifth-order single-stage ΔΣ modulator achieves 14 b resolution with 8× OSR and 4 MHz conversion bandwidth in a 1.8 V 0.18 μm CMOS process. The DC gain of the internal op amps is 43 dB. It occupies 1.3×2.2 mm/sup 2/ and consumes 102 mW analog power and 47 mW digital power.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114928923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992930
Chen Xu, Weiquan Zhang, M. Chan
A 128/spl times/128 complementary CMOS active-pixel sensor (CAPS) is fabricated in 0.25 /spl mu/m CMOS for low-voltage application. A single-slope with correlated double sampling (CDS) is used in the readout circuit. The chip operates at a V/sub DD/ as low as 0.8 V with 15 dB added dynamic range compared with conventional CMOS APS.
{"title":"A 1.0 V V/sub DD/ CMOS active pixel image sensor with complementary pixel architecture fabricated with a 0.25 /spl mu/m CMOS process","authors":"Chen Xu, Weiquan Zhang, M. Chan","doi":"10.1109/ISSCC.2002.992930","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992930","url":null,"abstract":"A 128/spl times/128 complementary CMOS active-pixel sensor (CAPS) is fabricated in 0.25 /spl mu/m CMOS for low-voltage application. A single-slope with correlated double sampling (CDS) is used in the readout circuit. The chip operates at a V/sub DD/ as low as 0.8 V with 15 dB added dynamic range compared with conventional CMOS APS.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130018437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992196
M. Igarashi, Takashi Mitsuhashi, Andy Le, Shardul Kazi, Yang-Trung Lin, Aki Fujimura, Steve Teig
Applying a design methodology based on an interconnect architecture characterized by pervasive use of diagonal wiring to a 128 b RISC processor core design results in 19.8 % path delay reduction and 10 % area reduction, compared to the conventional orthogonal interconnect architecture.
{"title":"A diagonal-interconnect architecture and its application to RISC core design","authors":"M. Igarashi, Takashi Mitsuhashi, Andy Le, Shardul Kazi, Yang-Trung Lin, Aki Fujimura, Steve Teig","doi":"10.1109/ISSCC.2002.992196","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992196","url":null,"abstract":"Applying a design methodology based on an interconnect architecture characterized by pervasive use of diagonal wiring to a 128 b RISC processor core design results in 19.8 % path delay reduction and 10 % area reduction, compared to the conventional orthogonal interconnect architecture.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129359148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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