Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992090
R. Etienne-Cummings, P. Pouliquen, M. A. Lewis
128(H)/spl times/64(V)/spl times/RGB CMOS imager is integrated with region-of-interest selection, RGB-to-HSI transformation, HSI-based pixel segmentation, 36-bins/spl times/12b HSI histogramming, and sum-of-absolute-difference template matching. 32 learned color templates are stored and compared to each frame. At 30 frames/s, it uses 1 mW.
{"title":"Single chip for imaging, color segmentation, histogramming and pattern matching","authors":"R. Etienne-Cummings, P. Pouliquen, M. A. Lewis","doi":"10.1109/ISSCC.2002.992090","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992090","url":null,"abstract":"128(H)/spl times/64(V)/spl times/RGB CMOS imager is integrated with region-of-interest selection, RGB-to-HSI transformation, HSI-based pixel segmentation, 36-bins/spl times/12b HSI histogramming, and sum-of-absolute-difference template matching. 32 learned color templates are stored and compared to each frame. At 30 frames/s, it uses 1 mW.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121876768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992104
Dong Zheng, Xuecheng Jin, E. Cheung, M. Rana, Gengyue Song, Yong Jiang, Y. Sutu, Bin Wu
A 0.18 /spl mu/m/sup 2/ CMOS quad transceiver provides 12.5 Gb/s full-duplex raw data throughput at 200 mW/channel consumption. An analog phase rotator in CDR (clock/data recovery) eliminates the quantization error of digital phase interpolation techniques, resulting in <17 ps peak-peak output jitter.
{"title":"A quad 3.125 Gb/s/channel transceiver with analog phase rotators","authors":"Dong Zheng, Xuecheng Jin, E. Cheung, M. Rana, Gengyue Song, Yong Jiang, Y. Sutu, Bin Wu","doi":"10.1109/ISSCC.2002.992104","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992104","url":null,"abstract":"A 0.18 /spl mu/m/sup 2/ CMOS quad transceiver provides 12.5 Gb/s full-duplex raw data throughput at 200 mW/channel consumption. An analog phase rotator in CDR (clock/data recovery) eliminates the quantization error of digital phase interpolation techniques, resulting in <17 ps peak-peak output jitter.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122620724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992948
Jaeseo Lee, Seong-Jun Song, Sung Min Park, Choong-Mo Nam, Young-Se Kwon, H. Yoo
A 1.0 Gb/s 80 dB/spl Omega/ fully-differential TIA uses 0.25 /spl mu/m CMOS and multichip-on-oxide (MCO) process. MCO enables integration of PD, TIA, and planar inductors of Q=21.1 for shunt peaking on an oxidized silicon substrate. Interchannel crosstalk and power dissipation are <-40 dB and 27 mW, respectively. MCO and TIA chips are 5/spl times/5 mm/sup 2/ and 0.7/spl times/1 mm/sup 2/, respectively.
{"title":"A multichip on oxide of 1 Gb/s 80 dB fully-differential CMOS transimpedance amplifier for optical interconnect applications","authors":"Jaeseo Lee, Seong-Jun Song, Sung Min Park, Choong-Mo Nam, Young-Se Kwon, H. Yoo","doi":"10.1109/ISSCC.2002.992948","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992948","url":null,"abstract":"A 1.0 Gb/s 80 dB/spl Omega/ fully-differential TIA uses 0.25 /spl mu/m CMOS and multichip-on-oxide (MCO) process. MCO enables integration of PD, TIA, and planar inductors of Q=21.1 for shunt peaking on an oxidized silicon substrate. Interchannel crosstalk and power dissipation are <-40 dB and 27 mW, respectively. MCO and TIA chips are 5/spl times/5 mm/sup 2/ and 0.7/spl times/1 mm/sup 2/, respectively.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125493558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992265
H. Okano, A. Suga, T. Shiota, Y. Takebe, Yasuki Nakamura, N. Higaki, Haruo Kimura, H. Miyake, T. Satoh, K. Kawasaki, R. Sasagawa, W. Shibamoto, Mitsuru Sasaki, Naruyoshi Ando, Tomohiro Yamana, I. Fukushi, S. Tago, F. Hayakawa, Teruhiko Kamigata, S. Imai, Atsushi Satoh, Yasuaki Hatta, Noboru Nishimura, Y. Asada, Taizo Satoh, Takao Sukemura, S. Ando, Hiromasa Takahashi
A 533 MHz 2.5 W 2132 MIPS 12.8 GOPS 2.1 GFLOPS 8-way VLIW embedded multimedia processor occupies a 7.8/spl times/7.8 mm/sup 2/ die in a 7-layer metal 0.11 /spl mu/m CMOS at 1.2 V. VLIW, SIMD, dynamic branch prediction, non-aligned dual load/store mechanism and a crosstalk-aware design flow contribute to performance.
{"title":"An 8-way VLIW embedded multimedia processor built in 7-layer metal 0.11 /spl mu/m CMOS technology","authors":"H. Okano, A. Suga, T. Shiota, Y. Takebe, Yasuki Nakamura, N. Higaki, Haruo Kimura, H. Miyake, T. Satoh, K. Kawasaki, R. Sasagawa, W. Shibamoto, Mitsuru Sasaki, Naruyoshi Ando, Tomohiro Yamana, I. Fukushi, S. Tago, F. Hayakawa, Teruhiko Kamigata, S. Imai, Atsushi Satoh, Yasuaki Hatta, Noboru Nishimura, Y. Asada, Taizo Satoh, Takao Sukemura, S. Ando, Hiromasa Takahashi","doi":"10.1109/ISSCC.2002.992265","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992265","url":null,"abstract":"A 533 MHz 2.5 W 2132 MIPS 12.8 GOPS 2.1 GFLOPS 8-way VLIW embedded multimedia processor occupies a 7.8/spl times/7.8 mm/sup 2/ die in a 7-layer metal 0.11 /spl mu/m CMOS at 1.2 V. VLIW, SIMD, dynamic branch prediction, non-aligned dual load/store mechanism and a crosstalk-aware design flow contribute to performance.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132718308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992928
D. Stoppa, A. Simoni, L. Gonzo, M. Gottardi, G. Dalla Betta
A 128/spl times/64 pixel image sensor in 0.35 /spl mu/m 3.3V CMOS technology achieves 138 dB dynamic range by adapting single-pixel integration time to the local illumination conditions. Video frame rate is achieved with 0.2% rms temporal noise and 14 mW power in a test chip.
{"title":"A 138 dB dynamic range CMOS image sensor with new pixel architecture","authors":"D. Stoppa, A. Simoni, L. Gonzo, M. Gottardi, G. Dalla Betta","doi":"10.1109/ISSCC.2002.992928","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992928","url":null,"abstract":"A 128/spl times/64 pixel image sensor in 0.35 /spl mu/m 3.3V CMOS technology achieves 138 dB dynamic range by adapting single-pixel integration time to the local illumination conditions. Video frame rate is achieved with 0.2% rms temporal noise and 14 mW power in a test chip.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132890474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992288
J. Geen, S. Sherman, J. F. Chang, S. R. Lewis
A MEMS surface-micromachined gyroscope integrated on a single 3/spl times/3 mm/sup 2/ chip with a 3 /spl mu/m BiCMOS process has 4 /spl mu/m-thick polysilicon structure, 5V 6 mA power supply, 0.05/spl deg///spl radic/s spot noise, 12.5 mV//spl deg//s, >30,000 g shock survival, and -55 to 85/spl deg/C operating range.
{"title":"Single-chip surface-micromachined integrated gyroscope with 50/spl deg//hour root Allan variance","authors":"J. Geen, S. Sherman, J. F. Chang, S. R. Lewis","doi":"10.1109/ISSCC.2002.992288","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992288","url":null,"abstract":"A MEMS surface-micromachined gyroscope integrated on a single 3/spl times/3 mm/sup 2/ chip with a 3 /spl mu/m BiCMOS process has 4 /spl mu/m-thick polysilicon structure, 5V 6 mA power supply, 0.05/spl deg///spl radic/s spot noise, 12.5 mV//spl deg//s, >30,000 g shock survival, and -55 to 85/spl deg/C operating range.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132317297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993116
C. Hagleitner, D. Lange, N. Kerness, A. Hierlemann, O. Brand, H. Baltes
A single-chip chemical microsensor system fabricated in industrial 0.8 /spl mu/m CMOS technology includes three different polymer-coated micromachined transducers. The chip forms an integral part of a handheld unit to detect volatile organics. On-chip circuitry includes signal conditioning, A/D-converters, filters, digital controller, and serial bus interface (I/sup 2/C).
采用工业0.8 /spl μ m CMOS技术制造的单芯片化学微传感器系统包括三种不同的聚合物包覆微机械传感器。该芯片构成用于检测挥发性有机物的手持装置的组成部分。片上电路包括信号调理，A/ d转换器，滤波器，数字控制器和串行总线接口(I/sup 2/C)。
{"title":"A gas detection system on a single CMOS chip comprising capacitive, calorimetric, and mass-sensitive microsensors","authors":"C. Hagleitner, D. Lange, N. Kerness, A. Hierlemann, O. Brand, H. Baltes","doi":"10.1109/ISSCC.2002.993116","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993116","url":null,"abstract":"A single-chip chemical microsensor system fabricated in industrial 0.8 /spl mu/m CMOS technology includes three different polymer-coated micromachined transducers. The chip forms an integral part of a handheld unit to detect volatile organics. On-chip circuitry includes signal conditioning, A/D-converters, filters, digital controller, and serial bus interface (I/sup 2/C).","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114848458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992171
J. Barth, D. Anand, J. Dreibelbis, E. Nelson
A 0.12 /spl mu/m growable eDRAM macro has GND sense, bit-line twisting, direct reference cell write, a flexible multi-banking protocol, and column redundancy to support multi-banking. The protocol supports simultaneous activate, read/write and pre-charge to three different banks. Hardware measurements verify 300 MHz operation, 6.6 ns tacc, and 10 ns trc.
{"title":"A 300 MHz multi-banked eDRAM macro featuring GND sense, bit-line twisting and direct reference cell write","authors":"J. Barth, D. Anand, J. Dreibelbis, E. Nelson","doi":"10.1109/ISSCC.2002.992171","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992171","url":null,"abstract":"A 0.12 /spl mu/m growable eDRAM macro has GND sense, bit-line twisting, direct reference cell write, a flexible multi-banking protocol, and column redundancy to support multi-banking. The protocol supports simultaneous activate, read/write and pre-charge to three different banks. Hardware measurements verify 300 MHz operation, 6.6 ns tacc, and 10 ns trc.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116328454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992178
K. Sushihara, A. Matsuzawa
A 7b 450MSample/s CMOS ADC in 0.18/spl mu/m technology is used for the embedded digital read channel system in DVD SOC. A dynamic comparator and an interpolation circuit composed of gate-width-weighted transistors consumes 50mW and occupies 0.3mm/sup 2/.
{"title":"A 7b 450MSample/s 50mW CMOS ADC in 0.3mm/sup 2/","authors":"K. Sushihara, A. Matsuzawa","doi":"10.1109/ISSCC.2002.992178","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992178","url":null,"abstract":"A 7b 450MSample/s CMOS ADC in 0.18/spl mu/m technology is used for the embedded digital read channel system in DVD SOC. A dynamic comparator and an interpolation circuit composed of gate-width-weighted transistors consumes 50mW and occupies 0.3mm/sup 2/.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114647078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993081
P. Dainesi, A. Ionescu, L. Thévenaz, K. Banerjee, M. Declercq, P. Robert, P. Renaud, P. Fluckiger, C. Hibert, G. Racine
3-D integrable SOI optoelectronic devices include telecommunication optical switches with 5 MHz bandwidth and unbalanced Mach Zehnder interferometers for filtering. Thermal compensation provides efficient modulation over 100 kHz -1 MHz and addresses 3-D IC thermal issues.
{"title":"3-D integrable optoelectronic devices for telecommunications ICs","authors":"P. Dainesi, A. Ionescu, L. Thévenaz, K. Banerjee, M. Declercq, P. Robert, P. Renaud, P. Fluckiger, C. Hibert, G. Racine","doi":"10.1109/ISSCC.2002.993081","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993081","url":null,"abstract":"3-D integrable SOI optoelectronic devices include telecommunication optical switches with 5 MHz bandwidth and unbalanced Mach Zehnder interferometers for filtering. Thermal compensation provides efficient modulation over 100 kHz -1 MHz and addresses 3-D IC thermal issues.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124690937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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