Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993026
D. Pfaff, Q. Huang
A demodulator has been designed which consists of a 3.6 GHz VCO, a 3.8 mA current-mode divider for the I/Q generation, and two single-ended input double-balanced mixers. The IC consumes 10 mA at 1.8 V, and has -114 dBc phase noise at 100 kHz offset, 40 dB image rejection, 14 dB DSB noise figure and 8.5 dBm IIP3.
{"title":"An 18 mW 1800 MHz quadrature demodulator in 0.18 /spl mu/m CMOS","authors":"D. Pfaff, Q. Huang","doi":"10.1109/ISSCC.2002.993026","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993026","url":null,"abstract":"A demodulator has been designed which consists of a 3.6 GHz VCO, a 3.8 mA current-mode divider for the I/Q generation, and two single-ended input double-balanced mixers. The IC consumes 10 mA at 1.8 V, and has -114 dBc phase noise at 100 kHz offset, 40 dB image rejection, 14 dB DSB noise figure and 8.5 dBm IIP3.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126884003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992189
G. Almási, G. Almási, D. Beece, Ralph Bellofatto, G. Bhanot, R. Bickford, M. Blumrich, Arthur A. Bright, J. Brunheroto, Calin Cascaval, J. Castaños, Luis Ceze, P. Cateus, Siddhartha Chatterjee, D. Chen, G. Chiu, T. Cipolla, P. Crumley, A. Deutsch, M. B. Dombrowa, W. Donath, M. Eleftheriou, B. Fitch, J. Gagliano, A. Gara, R. Germain, M. Giampapa, M. Gupta, F. Gustavson, S. Hall, R. Haring, D. Heidel, P. Heidelberger, L. Herger, D. Hoenicke, R. D. Jackson, T. Jamal-Eddine, G. Kopcsay, A. P. Lanzetta, D. Lieber, M. Lu, M. Mendell, L. Mok, J. Moreira, B. J. Nathanson, M. Newton, M. Ohmacht, R. Rand, R. Regan, R. Sahoo, A. Sanomiya, E. Schenfeld, Suryabhan Singh, Peilin Song, B. Steinmacher-Burow, K. Strauss, R. Swetz, T. Takken, P. Vranas, T. Ward, J. Brown, T. Liebsch, A. Schram, G. Ulsh
System-on-a-chip technology allows a level of integration that can be leveraged to develop inexpensive high-performance, low-power computing nodes. When used in aggregate, this approach promises to challenge conventional supercomputer architectures in the high-performance computing arena. Systems under consideration reach into the hundreds of thousand nodes per machine. Architecture for these systems are described.
{"title":"Cellular supercomputing with system-on-a-chip","authors":"G. Almási, G. Almási, D. Beece, Ralph Bellofatto, G. Bhanot, R. Bickford, M. Blumrich, Arthur A. Bright, J. Brunheroto, Calin Cascaval, J. Castaños, Luis Ceze, P. Cateus, Siddhartha Chatterjee, D. Chen, G. Chiu, T. Cipolla, P. Crumley, A. Deutsch, M. B. Dombrowa, W. Donath, M. Eleftheriou, B. Fitch, J. Gagliano, A. Gara, R. Germain, M. Giampapa, M. Gupta, F. Gustavson, S. Hall, R. Haring, D. Heidel, P. Heidelberger, L. Herger, D. Hoenicke, R. D. Jackson, T. Jamal-Eddine, G. Kopcsay, A. P. Lanzetta, D. Lieber, M. Lu, M. Mendell, L. Mok, J. Moreira, B. J. Nathanson, M. Newton, M. Ohmacht, R. Rand, R. Regan, R. Sahoo, A. Sanomiya, E. Schenfeld, Suryabhan Singh, Peilin Song, B. Steinmacher-Burow, K. Strauss, R. Swetz, T. Takken, P. Vranas, T. Ward, J. Brown, T. Liebsch, A. Schram, G. Ulsh","doi":"10.1109/ISSCC.2002.992189","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992189","url":null,"abstract":"System-on-a-chip technology allows a level of integration that can be leveraged to develop inexpensive high-performance, low-power computing nodes. When used in aggregate, this approach promises to challenge conventional supercomputer architectures in the high-performance computing arena. Systems under consideration reach into the hundreds of thousand nodes per machine. Architecture for these systems are described.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125936339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992123
H. Nakamura, K. Imamiya, T. Himeno, T. Yamamura, T. Ikehashi, K. Takeuchi, K. Kanda, K. Hosono, T. Futatsuyama, K. Kawai, R. Shirota, N. Arai, F. Arai, K. Hatakeyama, H. Hazama, M. Saito, H. Meguro, K. Conley, K. Quader, Jing Chen
A 125 mm/sup 2/ 1Gb NAND flash uses 0.13 /spl mu/m CMOS. The cell is 0.077 /spl mu/m/sup 2/. Chip architecture is changed to reduce chip size and to realize 10.6 MB/s throughput for program and 20 MB/s for read. An on-chip page copy function provides 9.4 MB/s throughput for garbage collection.
{"title":"A 125 mm/sup 2/ 1Gb NAND flash memory with 10 MB/s program throughput","authors":"H. Nakamura, K. Imamiya, T. Himeno, T. Yamamura, T. Ikehashi, K. Takeuchi, K. Kanda, K. Hosono, T. Futatsuyama, K. Kawai, R. Shirota, N. Arai, F. Arai, K. Hatakeyama, H. Hazama, M. Saito, H. Meguro, K. Conley, K. Quader, Jing Chen","doi":"10.1109/ISSCC.2002.992123","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992123","url":null,"abstract":"A 125 mm/sup 2/ 1Gb NAND flash uses 0.13 /spl mu/m CMOS. The cell is 0.077 /spl mu/m/sup 2/. Chip architecture is changed to reduce chip size and to realize 10.6 MB/s throughput for program and 20 MB/s for read. An on-chip page copy function provides 9.4 MB/s throughput for garbage collection.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127044765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993120
B. Ahuja, E. Hoffman, R. L. Gower, C. Rogers, J. Salcedo
A highly integrated 30 MSample/s video analog front end for >2M pixels camera with 36 dB of programmable pixel-by-pixel gain achieves 73 dB SNR. Dynamic bias in a 12b pipeline ADC results in 48 mW power with 0.4 LSB DNL. The die is 7.6 mm/sup 2/ in 0.35 /spl mu/m CMOS with 110 mW power at 2.7 V.
{"title":"A 30 Msample/s 12b 110 mW video analog front end for digital camera","authors":"B. Ahuja, E. Hoffman, R. L. Gower, C. Rogers, J. Salcedo","doi":"10.1109/ISSCC.2002.993120","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993120","url":null,"abstract":"A highly integrated 30 MSample/s video analog front end for >2M pixels camera with 36 dB of programmable pixel-by-pixel gain achieves 73 dB SNR. Dynamic bias in a 12b pipeline ADC results in 48 mW power with 0.4 LSB DNL. The die is 7.6 mm/sup 2/ in 0.35 /spl mu/m CMOS with 110 mW power at 2.7 V.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133603186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993017
S.K. Gupta, T. Brooks, V. Fong
The authors present a ΣΔ ADC with 105 dB distortion up to 1.5 MHz signal bandwidth, which uses a linear sampling network in a single-bit feedback 2-1-1 mash cascade modulator architecture. Operating at 64 MHz clock frequency, the measured SNR in a 1.1 MHz bandwidth is 88 dB. The area, including bypass capacitors, is 2.6 mm/sup 2/, in a 0.18 μm 1.8 V/3.3 V SP5M digital CMOS process. The power consumed is 230 mW, including references and decimation filter.
{"title":"A 64 MHz /spl Sigma//spl Delta/ ADC with 105 dB IM3 distortion using a linearized replica sampling network","authors":"S.K. Gupta, T. Brooks, V. Fong","doi":"10.1109/ISSCC.2002.993017","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993017","url":null,"abstract":"The authors present a ΣΔ ADC with 105 dB distortion up to 1.5 MHz signal bandwidth, which uses a linear sampling network in a single-bit feedback 2-1-1 mash cascade modulator architecture. Operating at 64 MHz clock frequency, the measured SNR in a 1.1 MHz bandwidth is 88 dB. The area, including bypass capacitors, is 2.6 mm/sup 2/, in a 0.18 μm 1.8 V/3.3 V SP5M digital CMOS process. The power consumed is 230 mW, including references and decimation filter.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129351203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992931
T. Goji Etoh, D. Poggemann, A. Ruckelshausen, A. Theuwissen, G. Kreider, H. Folkerts, H. Mutoh, Y. Kondo, H. Maruno, K. Takubo, H. Soya, K. Takehara, T. Okinaka, Y. Takano, T. Reisinger, C. Lohmann
A single-chip CCD image sensor captures >100 successive images at >1 Mframes/s. The pixel count of the test chip is 312/spl times/260 (=81,120) pixels. Charge handling capacity is 40 k electrons. Grey levels are 10 b. Fill factor is 13%. An on-chip overwriting mechanism makes possible continuous recording of the latest image signals, draining the old ones to the substrate.
{"title":"A CCD image sensor of 1 Mframes/s for continuous image capturing 103 frames","authors":"T. Goji Etoh, D. Poggemann, A. Ruckelshausen, A. Theuwissen, G. Kreider, H. Folkerts, H. Mutoh, Y. Kondo, H. Maruno, K. Takubo, H. Soya, K. Takehara, T. Okinaka, Y. Takano, T. Reisinger, C. Lohmann","doi":"10.1109/ISSCC.2002.992931","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992931","url":null,"abstract":"A single-chip CCD image sensor captures >100 successive images at >1 Mframes/s. The pixel count of the test chip is 312/spl times/260 (=81,120) pixels. Charge handling capacity is 40 k electrons. Grey levels are 10 b. Fill factor is 13%. An on-chip overwriting mechanism makes possible continuous recording of the latest image signals, draining the old ones to the substrate.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115207038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993009
T. Hanyu, H. Kimura, M. Kameyama, Y. Fujimori, T. Nakamura, H. Takasu
The state-transition scheme of remnant polarization in a ferroelectric capacitor performs storage and switching functions simultaneously with a functional pass-gate. As an example of fine-grain pipelined VLSI computation, a 250 MHz 54/spl times/54 b pipelined multiplier has 2.5 W estimated power dissipation in a 0.6 /spl mu/m ferroelectric/CMOS technology.
{"title":"Ferroelectric-based functional pass-gate for fine-grain pipelined VLSI computation","authors":"T. Hanyu, H. Kimura, M. Kameyama, Y. Fujimori, T. Nakamura, H. Takasu","doi":"10.1109/ISSCC.2002.993009","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993009","url":null,"abstract":"The state-transition scheme of remnant polarization in a ferroelectric capacitor performs storage and switching functions simultaneously with a functional pass-gate. As an example of fine-grain pipelined VLSI computation, a 250 MHz 54/spl times/54 b pipelined multiplier has 2.5 W estimated power dissipation in a 0.6 /spl mu/m ferroelectric/CMOS technology.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"3 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124298877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992998
Yeonwoo Ku, Y. Eo, K. Lee
This presentation shows the feasibility of integrating a reference oscillator on CMOS circuits, using digitally temperature-compensated SAW oscillator and Polylithic IC technology on a quartz-on-silicon wafer. The oscillator shows -115 dBc/Hz phase noise at 10 kHz offset, 7.5 mW power consumption, and 4.5 ppm frequency stability.
{"title":"Polylithic integration of a reference SAW quartz-on-silicon oscillator for single-chip radio","authors":"Yeonwoo Ku, Y. Eo, K. Lee","doi":"10.1109/ISSCC.2002.992998","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992998","url":null,"abstract":"This presentation shows the feasibility of integrating a reference oscillator on CMOS circuits, using digitally temperature-compensated SAW oscillator and Polylithic IC technology on a quartz-on-silicon wafer. The oscillator shows -115 dBc/Hz phase noise at 10 kHz offset, 7.5 mW power consumption, and 4.5 ppm frequency stability.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"47 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123268848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992149
D. Caro, E. Napoli, A. Strollo
Two 80 MHz 0.35 /spl mu/m 3.3V CMOS ROM-less DDFS using polynomial approximation are compared with Cordic-based circuits. A 60 dBc SFDR DDFS uses 2nd-order polynomials and 0.18 mm/sup 2/, with 15 mW dissipation. An 80 dBc SFDR DDFS uses 3rd-order polynomials and 0.44 mm/sup 2/, with 35 mW dissipation.
{"title":"Direct digital frequency synthesizers using high-order polynomial approximation","authors":"D. Caro, E. Napoli, A. Strollo","doi":"10.1109/ISSCC.2002.992149","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992149","url":null,"abstract":"Two 80 MHz 0.35 /spl mu/m 3.3V CMOS ROM-less DDFS using polynomial approximation are compared with Cordic-based circuits. A 60 dBc SFDR DDFS uses 2nd-order polynomials and 0.18 mm/sup 2/, with 15 mW dissipation. An 80 dBc SFDR DDFS uses 3rd-order polynomials and 0.44 mm/sup 2/, with 35 mW dissipation.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122818035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993040
Siva G. Narendra, Matthew Haycock, V. Govindarajulu, V. Erraguntla, H. Wilson, S. Vangal, Amaresh Pangal, Erik Seligman, Raj Nair, Ali Keshavarzi, B. Bloechel, G. Dermer, Randy Mooney, N. Borkar, S. Borkar, Vivek De Microprocessor
A router chip, that incorporates on-chip forward body biasing capability with 2% area overhead, achieves 1 GHz operation at 1.1 V supply in a 150 nm logic technology, compared to 1.25 V required for the original design having no body bias. Switching power is 23% less and chip leakage is reduced by 3.5/spl times/ in standby mode by withdrawing forward bias.
{"title":"1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS","authors":"Siva G. Narendra, Matthew Haycock, V. Govindarajulu, V. Erraguntla, H. Wilson, S. Vangal, Amaresh Pangal, Erik Seligman, Raj Nair, Ali Keshavarzi, B. Bloechel, G. Dermer, Randy Mooney, N. Borkar, S. Borkar, Vivek De Microprocessor","doi":"10.1109/ISSCC.2002.993040","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993040","url":null,"abstract":"A router chip, that incorporates on-chip forward body biasing capability with 2% area overhead, achieves 1 GHz operation at 1.1 V supply in a 150 nm logic technology, compared to 1.25 V required for the original design having no body bias. Switching power is 23% less and chip leakage is reduced by 3.5/spl times/ in standby mode by withdrawing forward bias.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"54 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123421803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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