Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993084
M. Ohashi, T. Hashimoto, S. Kuromaru, M. Matsuo, T. Mori-iwa, M. Hamada, Y. Sugisawa, M. Arita, H. Tomita, M. Hoshino, H. Miyajima, T. Nakamura, K. Ishida, T. Kimura, Y. Kohashi, T. Kondo, A. Inoue, H. Fujimoto, K. Watada, T. Fukunaga, T. Nishi, H. Ito, J. Michiyama
A single-chip MPEG-4 video decoder LSI with integrated 896 kb embedded SRAM frame buffer and embedded video display engine consumes 11.1 mW at 27 MHz operation. The chip achieves QCIF 15 Hz H.263 and Simple@L1 decoding capability on a 37.26 mm/sup 2/ die using 0.18 μm 1.5 V quad-metal CMOS technology.
{"title":"A 27 MHz 11.1 mW MPEG-4 video decoder LSI for mobile application","authors":"M. Ohashi, T. Hashimoto, S. Kuromaru, M. Matsuo, T. Mori-iwa, M. Hamada, Y. Sugisawa, M. Arita, H. Tomita, M. Hoshino, H. Miyajima, T. Nakamura, K. Ishida, T. Kimura, Y. Kohashi, T. Kondo, A. Inoue, H. Fujimoto, K. Watada, T. Fukunaga, T. Nishi, H. Ito, J. Michiyama","doi":"10.1109/ISSCC.2002.993084","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993084","url":null,"abstract":"A single-chip MPEG-4 video decoder LSI with integrated 896 kb embedded SRAM frame buffer and embedded video display engine consumes 11.1 mW at 27 MHz operation. The chip achieves QCIF 15 Hz H.263 and Simple@L1 decoding capability on a 37.26 mm/sup 2/ die using 0.18 μm 1.5 V quad-metal CMOS technology.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121228201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993050
K. Ohata, K. Maruhashi, M. Ito, S. Kishimoto, K. Ikuina, T. Hashiguchi, N. Takahashi, S. Iwanaga
A 1.25 Gb/s 60 GHz-band compact transceiver module uses ASK modulation. CPW MMICs and planar filters are flip-chip mounted in TX and RX LTCC MCMs. The transmitter exhibits 9.6 dBm output power. The receiver shows -50 dBm minimum received power for 1.25 Gb/s error-free transmission. The transceiver module is 82/spl times/53/spl times/7 mm/sup 3/ (30 cc).
{"title":"Wireless 1.25 Gb/s transceiver module at 60 GHz-band","authors":"K. Ohata, K. Maruhashi, M. Ito, S. Kishimoto, K. Ikuina, T. Hashiguchi, N. Takahashi, S. Iwanaga","doi":"10.1109/ISSCC.2002.993050","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993050","url":null,"abstract":"A 1.25 Gb/s 60 GHz-band compact transceiver module uses ASK modulation. CPW MMICs and planar filters are flip-chip mounted in TX and RX LTCC MCMs. The transmitter exhibits 9.6 dBm output power. The receiver shows -50 dBm minimum received power for 1.25 Gb/s error-free transmission. The transceiver module is 82/spl times/53/spl times/7 mm/sup 3/ (30 cc).","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121245229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993020
S. Dow, B. Ballweber, L. Chou, D. Eickbusch, J. Irwin, G. Kurtzman, P. Manapragada, D. Moeller, J. Paramesh, G. Black, R. Wollscheid, K. Johnson
This transceiver IC, fabricated in SiGe:C BiCMOS, contains dual LNAs, dual quadrature mixers, baseband filtering, RX and TX VCOs, and transmit buffers. The IC has GSM band performance of 67.5 dB gain, 2.3 dB NF, +49 dBm IIP2, -9 dBm IIP3 50 dB image rejection, and TX noise <-162 dBc/Hz at 20 MHz. This IC is part of a highly integrated low cost, GSM/GPRS platform that consists of five separate ICs.
{"title":"A dual-band direct-conversion/VLIF transceiver for 50GSM/GSM/DCS/PCS","authors":"S. Dow, B. Ballweber, L. Chou, D. Eickbusch, J. Irwin, G. Kurtzman, P. Manapragada, D. Moeller, J. Paramesh, G. Black, R. Wollscheid, K. Johnson","doi":"10.1109/ISSCC.2002.993020","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993020","url":null,"abstract":"This transceiver IC, fabricated in SiGe:C BiCMOS, contains dual LNAs, dual quadrature mixers, baseband filtering, RX and TX VCOs, and transmit buffers. The IC has GSM band performance of 67.5 dB gain, 2.3 dB NF, +49 dBm IIP2, -9 dBm IIP3 50 dB image rejection, and TX noise <-162 dBc/Hz at 20 MHz. This IC is part of a highly integrated low cost, GSM/GPRS platform that consists of five separate ICs.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126780008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992940
Zhiliang Zheng, S. Lam, S. Sutardja
A low-noise Gb fully differential preamp in 0.25 /spl mu/m CMOS has a variable gain with constant 850 MHz bandwidth, and has a variable bandwidth with constant gain. Noise is <0.55 nV//spl radic/(Hz). The power consumption is 600 mW. The die of a 4-channel IC is <4.2 mm/sup 2/.
{"title":"A 0.55 nV//spl radic/(Hz) gigabit fully-differential CMOS preamplifier for MR/GMR read application","authors":"Zhiliang Zheng, S. Lam, S. Sutardja","doi":"10.1109/ISSCC.2002.992940","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992940","url":null,"abstract":"A low-noise Gb fully differential preamp in 0.25 /spl mu/m CMOS has a variable gain with constant 850 MHz bandwidth, and has a variable bandwidth with constant gain. Noise is <0.55 nV//spl radic/(Hz). The power consumption is 600 mW. The die of a 4-channel IC is <4.2 mm/sup 2/.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114612286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993106
M. Anders, S. Mathew, B. Bloechel, S. Thompson, R. Krishnamurthy, K. Soumyanath, S. Borkar
32b Han-Carlson ALU and 8-entry /spl times/ 2-ALU instruction scheduler loop for 6.5 GHz single-cycle integer execution at 1.2 V and 25/spl deg/C uses dual-Vt CMOS technology. A single-ended, leakage-tolerant dynamic scheme enables up to 9-wide ORs with 23% critical path speed improvement, 40% active leakage power reduction compared to Koggie-Stone implementation, dense layout occupying 44, 100 /spl mu/m/sup 2/, and performance scalable to 8 GHz at 1.5 V, 25/spl deg/C.
{"title":"A 6.5 GHz 130 nm single-ended dynamic ALU and instruction-scheduler loop","authors":"M. Anders, S. Mathew, B. Bloechel, S. Thompson, R. Krishnamurthy, K. Soumyanath, S. Borkar","doi":"10.1109/ISSCC.2002.993106","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993106","url":null,"abstract":"32b Han-Carlson ALU and 8-entry /spl times/ 2-ALU instruction scheduler loop for 6.5 GHz single-cycle integer execution at 1.2 V and 25/spl deg/C uses dual-Vt CMOS technology. A single-ended, leakage-tolerant dynamic scheme enables up to 9-wide ORs with 23% critical path speed improvement, 40% active leakage power reduction compared to Koggie-Stone implementation, dense layout occupying 44, 100 /spl mu/m/sup 2/, and performance scalable to 8 GHz at 1.5 V, 25/spl deg/C.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"541 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124265700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993052
H. Knapp, H. Wohlmuth, M. Wurzer, M. Rest
A static 2:1 frequency divider operating up to 25.4 GHz at 41 mA and a 25 Gb/s 2:1 multiplexer at 29 mA implemented in current-mode logic have differential 50 /spl Omega/ inputs and outputs. They are fabricated in a 0.12 /spl mu/m CMOS process and operate from a 1.5 V supply.
{"title":"25 GHz static frequency divider and 25 Gb/s multiplexer in 0.12 /spl mu/m CMOS","authors":"H. Knapp, H. Wohlmuth, M. Wurzer, M. Rest","doi":"10.1109/ISSCC.2002.993052","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993052","url":null,"abstract":"A static 2:1 frequency divider operating up to 25.4 GHz at 41 mA and a 25 Gb/s 2:1 multiplexer at 29 mA implemented in current-mode logic have differential 50 /spl Omega/ inputs and outputs. They are fabricated in a 0.12 /spl mu/m CMOS process and operate from a 1.5 V supply.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127756628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993045
R. Aparicio, A. Hajimiri
A 0.35 /spl mu/m VCO uses current switching to increase voltage swing, lower phase noise by cyclostationary noise alignment, and improve startup reliability. A CMOS VCO in a 3-metal, 0.35 /spl mu/m process has -139 dBc/Hz phase noise at 3 MHz offset from a 1.8 GHz carrier and 30% of continuous tuning using inductors with Q of 6 and 4 mA dc current.
{"title":"A CMOS differential noise-shifting Colpitts VCO","authors":"R. Aparicio, A. Hajimiri","doi":"10.1109/ISSCC.2002.993045","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993045","url":null,"abstract":"A 0.35 /spl mu/m VCO uses current switching to increase voltage swing, lower phase noise by cyclostationary noise alignment, and improve startup reliability. A CMOS VCO in a 3-metal, 0.35 /spl mu/m process has -139 dBc/Hz phase noise at 3 MHz offset from a 1.8 GHz carrier and 30% of continuous tuning using inductors with Q of 6 and 4 mA dc current.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127863592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992121
J. Lee, Heung-Soo Im, D. Byeon, Kyeong-Han Lee, Dong-Hyuk Chae, Kyongjoo Lee, Y. Lim, Jungdal Choi, Young-Il Seo, Jong-Sik Lee, K. Suh
A 1.8 V 1 Gb flash memory uses a 0.12 /spl mu/m STI process technology. A charge pump operates at <1.8 V. A center-placed row decoder is digitized in one block pitch by applying a 32-cell NAND structure. A page buffer, containing two latches, supports a cache-program to improve program speed to 7 MB/s.
1.8 V 1gb闪存采用0.12 /spl mu/m STI工艺技术。电荷泵工作在<1.8 V。通过应用32单元NAND结构，在一个块间距内数字化放置在中心的行解码器。包含两个锁存器的页缓冲区支持一个缓存程序，可将程序速度提高到7 MB/s。
{"title":"A 1.8 V 1 Gb NAND flash memory with 0.12 /spl mu/m STI process technology","authors":"J. Lee, Heung-Soo Im, D. Byeon, Kyeong-Han Lee, Dong-Hyuk Chae, Kyongjoo Lee, Y. Lim, Jungdal Choi, Young-Il Seo, Jong-Sik Lee, K. Suh","doi":"10.1109/ISSCC.2002.992121","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992121","url":null,"abstract":"A 1.8 V 1 Gb flash memory uses a 0.12 /spl mu/m STI process technology. A charge pump operates at <1.8 V. A center-placed row decoder is digitized in one block pitch by applying a 32-cell NAND structure. A page buffer, containing two latches, supports a cache-program to improve program speed to 7 MB/s.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117235835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993001
Toshihide Suzuki, Y. Nakasha, Tsuyoshi Takahashi, K. Makiyama, Kenji Imanishi, Tatsuya Hirose, Yuu Watanabe
A 90Gb/s 2:1 multiplexer IC uses 0.13/spl mu/m-gate InP-based HEMT technology. Parallel 2-ch input data are serialized. The differential outputs are 0.7V/sub pp/. The 1.9/spl times/1.8mm/sup 2/ die consumes 1.3W from a -5.2V supply.
{"title":"A 90Gb/s 2:1 multiplexer IC in InP-based HEMT technology","authors":"Toshihide Suzuki, Y. Nakasha, Tsuyoshi Takahashi, K. Makiyama, Kenji Imanishi, Tatsuya Hirose, Yuu Watanabe","doi":"10.1109/ISSCC.2002.993001","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993001","url":null,"abstract":"A 90Gb/s 2:1 multiplexer IC uses 0.13/spl mu/m-gate InP-based HEMT technology. Parallel 2-ch input data are serialized. The differential outputs are 0.7V/sub pp/. The 1.9/spl times/1.8mm/sup 2/ die consumes 1.3W from a -5.2V supply.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116158677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992194
K. Uchida, J. Koga, R. Ohba, A. Toriumi
Room-temperature-operating single-electron devices work not only as single-electron transistors (SETs) but also as nonvolatile single-electron memories. It is demonstrated that the combination of Coulomb oscillations with the nonvolatile memory functions offers high programmability for LSIs. The power and delay of a programmable SET logic are estimated.
{"title":"Programmable single-electron transistor logic for low-power intelligent Si LSI","authors":"K. Uchida, J. Koga, R. Ohba, A. Toriumi","doi":"10.1109/ISSCC.2002.992194","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992194","url":null,"abstract":"Room-temperature-operating single-electron devices work not only as single-electron transistors (SETs) but also as nonvolatile single-electron memories. It is demonstrated that the combination of Coulomb oscillations with the nonvolatile memory functions offers high programmability for LSIs. The power and delay of a programmable SET logic are estimated.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116131198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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