Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496433
B. Zhou, Zhiming Chen, Shoujue Wang
A new model is proposed to make a more precise simulation of a power MOSFET using PSPICE. The application results for all types of HEXFET devices have a good agreement with the corresponding curves in the IR databook. A method of parameter extraction and some simulation results are presented for a demonstration HEXFET device.
{"title":"An improved simulation model for power MOSFET","authors":"B. Zhou, Zhiming Chen, Shoujue Wang","doi":"10.1109/TENCON.1995.496433","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496433","url":null,"abstract":"A new model is proposed to make a more precise simulation of a power MOSFET using PSPICE. The application results for all types of HEXFET devices have a good agreement with the corresponding curves in the IR databook. A method of parameter extraction and some simulation results are presented for a demonstration HEXFET device.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116568006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496350
K. Horio, K. Usami
2-D simulation of backgating effect in GaAs MESFETs is made in which impact ionization of carriers and deep donors "EL2" in the substrate are considered. The kink-related backgating is reproduced, which is qualitatively consistent with recent experiments. The mechanism is attributed to the change of EL2's nature by capturing holes which are generated by impact ionization and flow into the substrate.
{"title":"Two-dimensional simulation of kink-related backgating effect in GaAs MESFETs","authors":"K. Horio, K. Usami","doi":"10.1109/TENCON.1995.496350","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496350","url":null,"abstract":"2-D simulation of backgating effect in GaAs MESFETs is made in which impact ionization of carriers and deep donors \"EL2\" in the substrate are considered. The kink-related backgating is reproduced, which is qualitatively consistent with recent experiments. The mechanism is attributed to the change of EL2's nature by capturing holes which are generated by impact ionization and flow into the substrate.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129864135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496448
S. Sonh, Hoonmo Yang, M. Lee
Efficient executions of branch instructions are one of the most important issues in implementing high performance microprocessors. Branching instructions are above 20% of total instruction in most programs. BTB (Branch Target Buffer) enhances the speed of branch instruction execution by predicting the branch path, including currently executed branch instruction address, prediction information, and target address. The BTB is designed as a 4-way set associative organization with 256 branch entries. Pseudo-LRU algorithm is used for replacement of lines instead of ordinary LRU algorithm. Also IP(Instruction Pointer) chain is designed for verifying the BTB.
{"title":"An implementation of branch target buffer for high performance applications","authors":"S. Sonh, Hoonmo Yang, M. Lee","doi":"10.1109/TENCON.1995.496448","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496448","url":null,"abstract":"Efficient executions of branch instructions are one of the most important issues in implementing high performance microprocessors. Branching instructions are above 20% of total instruction in most programs. BTB (Branch Target Buffer) enhances the speed of branch instruction execution by predicting the branch path, including currently executed branch instruction address, prediction information, and target address. The BTB is designed as a 4-way set associative organization with 256 branch entries. Pseudo-LRU algorithm is used for replacement of lines instead of ordinary LRU algorithm. Also IP(Instruction Pointer) chain is designed for verifying the BTB.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124282378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496402
T. Cheung, K. Asada, K. Yip, H. Wong, Y. Cheng
In this paper, two techniques on low power circuit design, namely, clock separated logic and sub-V/sub dd/ voltage-swing interfacing, are introduced. In the former method, reduced voltage-swing at internal nodes is used to achieve relatively low power dissipation as compared to circuits with full voltage-swing. In the latter method, pass-transistor logic with suppressed internal voltage-swing is used to reduce power dissipation in the pass-transistor chain. Basic techniques on design of these circuits are investigated and analyzed.
{"title":"Low power CMOS digital circuit design methodologies with reduced voltage swing","authors":"T. Cheung, K. Asada, K. Yip, H. Wong, Y. Cheng","doi":"10.1109/TENCON.1995.496402","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496402","url":null,"abstract":"In this paper, two techniques on low power circuit design, namely, clock separated logic and sub-V/sub dd/ voltage-swing interfacing, are introduced. In the former method, reduced voltage-swing at internal nodes is used to achieve relatively low power dissipation as compared to circuits with full voltage-swing. In the latter method, pass-transistor logic with suppressed internal voltage-swing is used to reduce power dissipation in the pass-transistor chain. Basic techniques on design of these circuits are investigated and analyzed.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121429357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496392
E. Jelenkovic, K. Tong
It is shown that nitridation of sputtered oxide by reactive sputtering can give a hardened oxide-silicon interface with reduced interface states generation after stress. SIMS analysis has confirmed the existence of SiN peak close to the oxide/silicon interface. A stacked SiO/sub 2//SiO/sub x/N/sub y/ structure is discussed relative to charge trapping, leakage current and mid-gap voltage shift.
{"title":"Nitridation of sputtered silicon dioxide films","authors":"E. Jelenkovic, K. Tong","doi":"10.1109/TENCON.1995.496392","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496392","url":null,"abstract":"It is shown that nitridation of sputtered oxide by reactive sputtering can give a hardened oxide-silicon interface with reduced interface states generation after stress. SIMS analysis has confirmed the existence of SiN peak close to the oxide/silicon interface. A stacked SiO/sub 2//SiO/sub x/N/sub y/ structure is discussed relative to charge trapping, leakage current and mid-gap voltage shift.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"19 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123361631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496343
W. Choy, S.F. Ip, E. Li
This is a first report to use diffused quantum well (DFQW) as the active cavity of the Fabry-Perot reflection modulator. Apart from the simple fabrication process of the DFQW, this material system provides a wavelength tuning range and improves the modulation properties of the device which thus is competitive with the same kind of modulator.
{"title":"Diffused-quantum-well vertical cavity Fabry-Perot reflection modulator","authors":"W. Choy, S.F. Ip, E. Li","doi":"10.1109/TENCON.1995.496343","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496343","url":null,"abstract":"This is a first report to use diffused quantum well (DFQW) as the active cavity of the Fabry-Perot reflection modulator. Apart from the simple fabrication process of the DFQW, this material system provides a wavelength tuning range and improves the modulation properties of the device which thus is competitive with the same kind of modulator.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126284989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496372
N. Schneeberger, S. Deteindre, O. Paul, H. Baltes
We fabricated and characterized four different CMOS thermoelectric infrared radiation sensor microsystems. The performance of these systems was modelled with the finite element simulation package SOLIDIS, based on measured materials properties. The agreement with experiment was better than 7.5%. Based on this validation we optimized the design parameters of such microsystems.
{"title":"Optimized CMOS infrared detector microsystems","authors":"N. Schneeberger, S. Deteindre, O. Paul, H. Baltes","doi":"10.1109/TENCON.1995.496372","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496372","url":null,"abstract":"We fabricated and characterized four different CMOS thermoelectric infrared radiation sensor microsystems. The performance of these systems was modelled with the finite element simulation package SOLIDIS, based on measured materials properties. The agreement with experiment was better than 7.5%. Based on this validation we optimized the design parameters of such microsystems.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133652919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496346
G. Park, Jin Lee, H. Chung, W. Jeong, Jae-cheol Cho, Y. Jeong, Y. Yoo
CuInS/sub 2//CdS heterojunction has been fabricated by depositing CdS thin film with dopant In on ternary compound CuInS/sub 2/ thin film. Its best conversion efficiency was 5.66% under the illumination of 100 mW/cm/sup 2/, and its series resistance and lattice mismatch was 5.1 /spl Omega/ and 3.2% respectively. Besides, 4-layer structure heterojunction of low /spl rho/-CuInS/sub 2//high /spl rho/-CuInS/sub 2//high /spl rho/-CdS/low /spl rho/-CdS has been fabricated. Its bast conversion efficiency was 8.25% under the illumination of 100 mW/cm/sup 2/, and its series resistance and lattice mismatch was 4.3 /spl Omega/ and 2.8% respectively.
{"title":"Photovoltaic characteristics of CuInS/sub 2//CdS heterojunction","authors":"G. Park, Jin Lee, H. Chung, W. Jeong, Jae-cheol Cho, Y. Jeong, Y. Yoo","doi":"10.1109/TENCON.1995.496346","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496346","url":null,"abstract":"CuInS/sub 2//CdS heterojunction has been fabricated by depositing CdS thin film with dopant In on ternary compound CuInS/sub 2/ thin film. Its best conversion efficiency was 5.66% under the illumination of 100 mW/cm/sup 2/, and its series resistance and lattice mismatch was 5.1 /spl Omega/ and 3.2% respectively. Besides, 4-layer structure heterojunction of low /spl rho/-CuInS/sub 2//high /spl rho/-CuInS/sub 2//high /spl rho/-CdS/low /spl rho/-CdS has been fabricated. Its bast conversion efficiency was 8.25% under the illumination of 100 mW/cm/sup 2/, and its series resistance and lattice mismatch was 4.3 /spl Omega/ and 2.8% respectively.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134221219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496395
Hui Lin, Rong Liu, Bingsen Chen, Hongfa Luan
The technology and equipment of the infrared rapid thermal annealing for VLSI is reported. The equipment used for rapid thermal annealing has been made with an radio frequency (RF)-induced graphite heater in a quartz housing as an infrared heating source. By using this technology and equipment the fabrication of shallow junction, the formation of silicide, the effect of BPSG reflow and annihilating the micro defects and thermal donor in CZ Si single crystal are discussed.
{"title":"Technology of infrared rapid thermal annealing and its application in VLSI","authors":"Hui Lin, Rong Liu, Bingsen Chen, Hongfa Luan","doi":"10.1109/TENCON.1995.496395","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496395","url":null,"abstract":"The technology and equipment of the infrared rapid thermal annealing for VLSI is reported. The equipment used for rapid thermal annealing has been made with an radio frequency (RF)-induced graphite heater in a quartz housing as an infrared heating source. By using this technology and equipment the fabrication of shallow junction, the formation of silicide, the effect of BPSG reflow and annihilating the micro defects and thermal donor in CZ Si single crystal are discussed.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129217249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496333
K.P. Anish Kumar, J. Sin
This paper reports the leakage current characteristics of Conductivity Modulated Thin Film Transistor (CMTFT) fabricated using polycrystalline silicon. The transistor uses the idea of conductivity modulation in the offset region to obtain a significant reduction in on-state resistance. Experimental on-state and off-state current-voltage characteristics of the CMTFT have been compared with those of the conventional offset drain device. The devices were fabricated using a low temperature process (620/spl deg/C) which is highly desirable for large area electronic applications.
{"title":"Off-current characteristics of conductivity modulated TFT","authors":"K.P. Anish Kumar, J. Sin","doi":"10.1109/TENCON.1995.496333","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496333","url":null,"abstract":"This paper reports the leakage current characteristics of Conductivity Modulated Thin Film Transistor (CMTFT) fabricated using polycrystalline silicon. The transistor uses the idea of conductivity modulation in the offset region to obtain a significant reduction in on-state resistance. Experimental on-state and off-state current-voltage characteristics of the CMTFT have been compared with those of the conventional offset drain device. The devices were fabricated using a low temperature process (620/spl deg/C) which is highly desirable for large area electronic applications.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"20 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133169921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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