Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496329
T. Lo, P. Chan, Zhenan Tang
Silicon piezoresistive stress sensors are used to measure stress on a plastic-encapsulated silicon die. These sensors are conventionally fabricated onto the surface of silicon integrated circuit die as part of the normal processing procedure. Since they can also be used over a wide temperature range after calibration, thermally-induced stresses can be measured. A four-point bending (4PB) stress fixture was used in calibration experiments. The results between the four-point resistance measurement and two-point resistance measurement of the strain gauges were compared. The problem in the calibration process was discussed.
{"title":"Design and characterization of a micro strain gauge","authors":"T. Lo, P. Chan, Zhenan Tang","doi":"10.1109/TENCON.1995.496329","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496329","url":null,"abstract":"Silicon piezoresistive stress sensors are used to measure stress on a plastic-encapsulated silicon die. These sensors are conventionally fabricated onto the surface of silicon integrated circuit die as part of the normal processing procedure. Since they can also be used over a wide temperature range after calibration, thermally-induced stresses can be measured. A four-point bending (4PB) stress fixture was used in calibration experiments. The results between the four-point resistance measurement and two-point resistance measurement of the strain gauges were compared. The problem in the calibration process was discussed.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130736380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496363
S.C. Wong, Y.S. Lee, C. Tse, M. Chow
A simple simulation method that evaluates the stability of analog circuits in the presence of reactive parasitic elements is proposed. This method also gives the range of values and the exact locations of the parasitic elements for which a given stable circuit will be rendered oscillatory.
{"title":"A simulation technique for evaluating analog circuits stability in the presence of reactive parasitic elements","authors":"S.C. Wong, Y.S. Lee, C. Tse, M. Chow","doi":"10.1109/TENCON.1995.496363","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496363","url":null,"abstract":"A simple simulation method that evaluates the stability of analog circuits in the presence of reactive parasitic elements is proposed. This method also gives the range of values and the exact locations of the parasitic elements for which a given stable circuit will be rendered oscillatory.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130428738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496388
P. Samanta, C. K. Sarkar
A theoretical analysis of metal-oxide-silicon (MOS) device degradation due to trapping of positive charges in thin (27, 33 nm) SiO/sub 2/ gate oxides is presented. n/sup +/-polySi-gate (MOS) capacitors are stressed at a low electron injection fluence (<0.01 C/cm/sup 2/) by Fowler-Nordheim (FN) electron tunneling from the quantized accumulation layer of <100> n-Si substrate, at constant current and constant applied gate voltage. The present analysis assumes tunneling electron initiated band-to-band impact ionization (BTBII) in SiO/sub 2/, as the possible source of trapped holes during stress. The validity of the present analysis has been examined by comparing the theoretical values with the experimental data of FN threshold voltage shift /spl Delta/V/sub FN/ of Fazan et al.
{"title":"Influence of neutral hole traps in thin gate oxides on MOS device degradation during Fowler-Nordheim stress","authors":"P. Samanta, C. K. Sarkar","doi":"10.1109/TENCON.1995.496388","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496388","url":null,"abstract":"A theoretical analysis of metal-oxide-silicon (MOS) device degradation due to trapping of positive charges in thin (27, 33 nm) SiO/sub 2/ gate oxides is presented. n/sup +/-polySi-gate (MOS) capacitors are stressed at a low electron injection fluence (<0.01 C/cm/sup 2/) by Fowler-Nordheim (FN) electron tunneling from the quantized accumulation layer of <100> n-Si substrate, at constant current and constant applied gate voltage. The present analysis assumes tunneling electron initiated band-to-band impact ionization (BTBII) in SiO/sub 2/, as the possible source of trapped holes during stress. The validity of the present analysis has been examined by comparing the theoretical values with the experimental data of FN threshold voltage shift /spl Delta/V/sub FN/ of Fazan et al.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131273448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496430
Cai Jun, J. Sin, W. Ng, P. Lai
In this paper, a new conductivity modulated power transistor, called the Lateral Trench-Gate Bipolar Transistor (LTGBT), is presented. The current at which the latch-up occurs in the structure is estimated in comparison with that of the LIGBT. The latch-up current density for the LTGBT exhibits more than 7.7 times improvement over the LIGBT. The dependence of the latch-up current density on the design of the n/sup +/ and p/sup +/ cathode regions of the structure is also examined. The maximum controllable latch-up current density is found to increase with decreasing the space between the trench gate and the p/sup +/ cathode.
{"title":"Latch-up characteristics of a trench-gate conductivity modulated power transistor","authors":"Cai Jun, J. Sin, W. Ng, P. Lai","doi":"10.1109/TENCON.1995.496430","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496430","url":null,"abstract":"In this paper, a new conductivity modulated power transistor, called the Lateral Trench-Gate Bipolar Transistor (LTGBT), is presented. The current at which the latch-up occurs in the structure is estimated in comparison with that of the LIGBT. The latch-up current density for the LTGBT exhibits more than 7.7 times improvement over the LIGBT. The dependence of the latch-up current density on the design of the n/sup +/ and p/sup +/ cathode regions of the structure is also examined. The maximum controllable latch-up current density is found to increase with decreasing the space between the trench gate and the p/sup +/ cathode.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134117745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496391
Z. Yao, H. B. Harrison, S. Dimitrijev, Y. Yeow
In this paper, stress induced leakage current (SILC) has been investigate in 3.0-nm nitric oxide (NO) grown gate dielectric films. MOS capacitors with 3.0-nm NO-grown films have much lower SILC compared to those reported results with N/sub 2/O oxides or pure oxides under high field stresses.
{"title":"High field stress induced leakage current in 3.0-nm NO-grown gate dielectric films","authors":"Z. Yao, H. B. Harrison, S. Dimitrijev, Y. Yeow","doi":"10.1109/TENCON.1995.496391","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496391","url":null,"abstract":"In this paper, stress induced leakage current (SILC) has been investigate in 3.0-nm nitric oxide (NO) grown gate dielectric films. MOS capacitors with 3.0-nm NO-grown films have much lower SILC compared to those reported results with N/sub 2/O oxides or pure oxides under high field stresses.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134535118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496397
KwangMyoung Rho, Y. Koh, C. Park, S. Hwang, Ha Poong Chung, M. J. Chung, Dai-Hoon Lee
With the MOSES (Mask Oxide Sidewall Etch Scheme) process which uses a conventional i-line stepper and isotropic wet etching, CMOSFETs with fine gate patterns of 0.1 /spl mu/m or less are fabricated and characterized successfully. To improve the short channel effect of 0.1 /spl mu/m CMOS devices, the screening oxide is deposited before the low energy ion implantation for source/drain extensions and a two step sidewall scheme is adopted. Through the characterization of 0.1 /spl mu/m CMOS devices, it is found that the screening oxide deposition scheme has a larger capability of suppressing the short channel effects than the two step sidewall scheme. In the case of 200 /spl Aring/-thick screening oxide deposition, both NMOS and PMOS devices maintain good subthreshold characteristics down to 0.1 /spl mu/m effective channel lengths, and show affordable drain saturation current reduction and low impact ionization rates.
{"title":"Dependence of deep submicron CMOSFET characteristics on shallow source/drain junction depth","authors":"KwangMyoung Rho, Y. Koh, C. Park, S. Hwang, Ha Poong Chung, M. J. Chung, Dai-Hoon Lee","doi":"10.1109/TENCON.1995.496397","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496397","url":null,"abstract":"With the MOSES (Mask Oxide Sidewall Etch Scheme) process which uses a conventional i-line stepper and isotropic wet etching, CMOSFETs with fine gate patterns of 0.1 /spl mu/m or less are fabricated and characterized successfully. To improve the short channel effect of 0.1 /spl mu/m CMOS devices, the screening oxide is deposited before the low energy ion implantation for source/drain extensions and a two step sidewall scheme is adopted. Through the characterization of 0.1 /spl mu/m CMOS devices, it is found that the screening oxide deposition scheme has a larger capability of suppressing the short channel effects than the two step sidewall scheme. In the case of 200 /spl Aring/-thick screening oxide deposition, both NMOS and PMOS devices maintain good subthreshold characteristics down to 0.1 /spl mu/m effective channel lengths, and show affordable drain saturation current reduction and low impact ionization rates.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134432589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496428
G. Niu, G. Ruan
This paper describes an analytical model of hole confinement gate voltage range (V/sub hc/) for SiGe-channel p-MOSFETs. The model shows that V/sub hc/ depends on threshold voltage, gate oxide to Si cap thickness ratio, Ge mole fraction at the top of SiGe channel, work function of gate material, and substrate doping. With device scaling and power supply reduction, the Si cap should be thinned by the same magnitude as the gate oxide to realize full bias range SiGe-channel operation. Various bulk and SOI SiGe p-MOSFETs are clarified to have the same hole confinement capability with threshold voltage adjusted to the value required by circuit application.
{"title":"An analytical model of hole confinement gate voltage range for SiGe-channel p-MOSFETs","authors":"G. Niu, G. Ruan","doi":"10.1109/TENCON.1995.496428","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496428","url":null,"abstract":"This paper describes an analytical model of hole confinement gate voltage range (V/sub hc/) for SiGe-channel p-MOSFETs. The model shows that V/sub hc/ depends on threshold voltage, gate oxide to Si cap thickness ratio, Ge mole fraction at the top of SiGe channel, work function of gate material, and substrate doping. With device scaling and power supply reduction, the Si cap should be thinned by the same magnitude as the gate oxide to realize full bias range SiGe-channel operation. Various bulk and SOI SiGe p-MOSFETs are clarified to have the same hole confinement capability with threshold voltage adjusted to the value required by circuit application.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129339871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496414
M.W.T. Wong, Yingquan Zhou, Y. Min
An algorithm proposed by Yingquan Zhou et al. (1995) for effectively reducing hardware overhead of the checking circuitry in the continuous checksums based concurrent error detection (CED) scheme in linear analog circuits is discussed. Without changing the original circuit, the algorithm generates such an appropriate coding matrix that makes the resulting checking circuitry have optimal hardware overhead.
{"title":"Hardware reduction in concurrent error detection checkers in linear analog circuits using continuous checksums","authors":"M.W.T. Wong, Yingquan Zhou, Y. Min","doi":"10.1109/TENCON.1995.496414","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496414","url":null,"abstract":"An algorithm proposed by Yingquan Zhou et al. (1995) for effectively reducing hardware overhead of the checking circuitry in the continuous checksums based concurrent error detection (CED) scheme in linear analog circuits is discussed. Without changing the original circuit, the algorithm generates such an appropriate coding matrix that makes the resulting checking circuitry have optimal hardware overhead.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122360571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496332
Kee-Jong Kim, Seong-Gyun Kim, W. Park, O. Kim
A charge pumping model considering bulk states in polysilicon thin film transistors has been developed. Here, we define the threshold voltage as a minimum voltage to fill the untrapped states within an applied pulse width. And the threshold voltage including the emission energy level was obtained as a function of depth. It shows that the calculated current of this model is more consistent with the measured one rather than the current or interface state model.
{"title":"A new charge pumping model for polysilicon thin film transistors","authors":"Kee-Jong Kim, Seong-Gyun Kim, W. Park, O. Kim","doi":"10.1109/TENCON.1995.496332","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496332","url":null,"abstract":"A charge pumping model considering bulk states in polysilicon thin film transistors has been developed. Here, we define the threshold voltage as a minimum voltage to fill the untrapped states within an applied pulse width. And the threshold voltage including the emission energy level was obtained as a function of depth. It shows that the calculated current of this model is more consistent with the measured one rather than the current or interface state model.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131324150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496401
T. Cheung, H. Wong, Y. Cheng
Internal signal propagation with voltage swing less than the supply voltage have been proposed through various architecture or structures. Reduced supply voltage in digital and analog circuits is considered to be one of the best methods for achieving real low power dissipation circuits. In this paper, pass-transistor logic with suppressed internal voltage-swing is investigated and analyzed. A proposal on a reduced swing 14-bit parity generator and carry generation blocks of a parallel full adder are also given. In addition, optimization on propagation delay can be achieved by proper tapering of the dimension of the transistors.
{"title":"Pass-transistor logic and its sub-Vdd voltage-swing behaviours in low-voltage circuit design","authors":"T. Cheung, H. Wong, Y. Cheng","doi":"10.1109/TENCON.1995.496401","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496401","url":null,"abstract":"Internal signal propagation with voltage swing less than the supply voltage have been proposed through various architecture or structures. Reduced supply voltage in digital and analog circuits is considered to be one of the best methods for achieving real low power dissipation circuits. In this paper, pass-transistor logic with suppressed internal voltage-swing is investigated and analyzed. A proposal on a reduced swing 14-bit parity generator and carry generation blocks of a parallel full adder are also given. In addition, optimization on propagation delay can be achieved by proper tapering of the dimension of the transistors.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124196066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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