A novel structure with sharp roll-off, wide stopband, and very compact size is presented in this paper. By combining a capacitor-embedded transmission line ring and two shunt open stubs, this structure exhibits a high-performance three-pole low-pass filter (LPF) response with four generated transmission zeros. With the help of these four transmission zeros, the proposed LPF achieves improved roll-off rate, extended stopband, and significantly very compact size. To verify the feasibility of the proposed structure, a prototype LPF having the cut-off frequency at 0.63 GHz is designed, fabricated, and measured as an illustrative example. Final result shows that a roll-off rate of 109.3 dB/GHz along with a relative stopband bandwidth of 114.6% can be obtained. Moreover, the filter dimensions are as small as 15.7 mm × 26.9 mm, that is, , where is the guided wavelength at the cut-off frequency. The filter structure is simple and easy to fabricate as well.
本文提出了一种新颖的结构，具有急剧滚转、宽阻带和非常紧凑的尺寸。通过结合电容嵌入式传输线环和两个并联开路存根，该结构具有高性能的三极低通滤波器(LPF)响应，并产生四个传输零。在这四个传输零的帮助下，所提出的LPF实现了改进的滚转率，延长了阻带，并且显着非常紧凑的尺寸。为了验证所提出结构的可行性，设计、制作了截止频率为0.63 GHz的LPF原型，并进行了测量。最终结果表明，该电路的滚降率为109.3 dB/GHz，相对阻带带宽为114.6%。滤波器尺寸小至15.7 mm × 26.9 mm，即，其中为截止频率处的导光波长。该滤波器结构简单，易于制造。
{"title":"A Very Compact and Sharp Roll-Off Low-Pass Filter with Four Transmission Zeros","authors":"Yang Xiao, Lin Li","doi":"10.1155/2015/806276","DOIUrl":"https://doi.org/10.1155/2015/806276","url":null,"abstract":"A novel structure with sharp roll-off, wide stopband, and very compact size is presented in this paper. By combining a capacitor-embedded transmission line ring and two shunt open stubs, this structure exhibits a high-performance three-pole low-pass filter (LPF) response with four generated transmission zeros. With the help of these four transmission zeros, the proposed LPF achieves improved roll-off rate, extended stopband, and significantly very compact size. To verify the feasibility of the proposed structure, a prototype LPF having the cut-off frequency at 0.63 GHz is designed, fabricated, and measured as an illustrative example. Final result shows that a roll-off rate of 109.3 dB/GHz along with a relative stopband bandwidth of 114.6% can be obtained. Moreover, the filter dimensions are as small as 15.7 mm × 26.9 mm, that is, , where is the guided wavelength at the cut-off frequency. The filter structure is simple and easy to fabricate as well.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2015-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2015/806276","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"65157401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The analytical model of random variation in drain current of the Floating Gate MOSFET (FGMOSFET) has been proposed in this research. The model is composed of two parts for triode and saturation region of operation where the process induced device level random variations of each region and their statistical correlations have been taken into account. The nonlinearity of floating gate voltage and dependency on drain voltage of the coupling factors of FGMOSFET have also been considered. The model has been found to be very accurate since it can accurately fit the SPICE BSIM3v3 based reference obtained by using Monte-Carlo SPICE simulation and FGMOSFET simulation technique with SPICE. It can fit the BSIM4 based reference if desired by using the optimally extracted parameters. By using the proposed model, the variability analysis of FGMOSFET and the analytical modeling of the variation in the circuit level parameter of any FGMOSFET based circuit can be performed. So, this model has been found to be an efficient tool for the variability aware analysis and design of FGMOSFET based circuit.
{"title":"Analytical Model of Random Variation in Drain Current of FGMOSFET","authors":"R. Banchuin","doi":"10.1155/2015/315105","DOIUrl":"https://doi.org/10.1155/2015/315105","url":null,"abstract":"The analytical model of random variation in drain current of the Floating Gate MOSFET (FGMOSFET) has been proposed in this research. The model is composed of two parts for triode and saturation region of operation where the process induced device level random variations of each region and their statistical correlations have been taken into account. The nonlinearity of floating gate voltage and dependency on drain voltage of the coupling factors of FGMOSFET have also been considered. The model has been found to be very accurate since it can accurately fit the SPICE BSIM3v3 based reference obtained by using Monte-Carlo SPICE simulation and FGMOSFET simulation technique with SPICE. It can fit the BSIM4 based reference if desired by using the optimally extracted parameters. By using the proposed model, the variability analysis of FGMOSFET and the analytical modeling of the variation in the circuit level parameter of any FGMOSFET based circuit can be performed. So, this model has been found to be an efficient tool for the variability aware analysis and design of FGMOSFET based circuit.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2015-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2015/315105","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64899795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A design of a V-band Helix-Folded Waveguide (H-FWG) cascaded traveling wave tube (TWT) is presented. In this cascaded structure, a digitized nonlinear theory model is put forward first to simulate these two types of the tubes by common process. Then, an initial design principle is proposed, which can design these two different kinds of tubes universally. Using this principle, a high-gain helix TWT is carefully designed as a first stage amplifier followed by a FWG TWT to obtain high power. Simulations predict that a peak power of 800 W with saturated gain of 60 dB from 55 GHz to 60 GHz can be achieved.
{"title":"Design of a Novel High Power V-Band Helix-Folded Waveguide Cascaded Traveling Wave Tube Amplifier","authors":"T. Zhuge, Yu-Lu Hu","doi":"10.1155/2015/846425","DOIUrl":"https://doi.org/10.1155/2015/846425","url":null,"abstract":"A design of a V-band Helix-Folded Waveguide (H-FWG) cascaded traveling wave tube (TWT) is presented. In this cascaded structure, a digitized nonlinear theory model is put forward first to simulate these two types of the tubes by common process. Then, an initial design principle is proposed, which can design these two different kinds of tubes universally. Using this principle, a high-gain helix TWT is carefully designed as a first stage amplifier followed by a FWG TWT to obtain high power. Simulations predict that a peak power of 800 W with saturated gain of 60 dB from 55 GHz to 60 GHz can be achieved.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2015-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2015/846425","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"65181403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
TCAD tools have been largely improved in the last decades in order to support both process and device complementary simulations which are usually based on continuously developed models following the technology progress. In this paper, we compare between experimental and TCAD simulated results of two kinds of nanoscale devices: ultrathin body (UTB) and nanoscale Body (NSB) SOI-MOSFET devices, sharing the same W/L ratio but having a channel thickness ratio of 10 : 1 (46 nm and 4.6 nm, resp.). The experimental transfer I-V characteristics were found to be surprisingly different by several orders of magnitude. We analyzed this result by considering the severe mobility degradation and the influence of a large gate voltage dependent series resistance (). TCAD tools do not usually consider to be either channel thickness or gate voltage dependent. After observing a clear discrepancy between the mobility values extracted from our measurements and those modeled by the available TCAD models, we propose a new semiempirical approach to model the transfer characteristics.
{"title":"Usage and Limitation of Standard Mobility Models for TCAD Simulation of Nanoscaled FD-SOI MOSFETs","authors":"A. Ciprut, A. Chelly, A. Karsenty","doi":"10.1155/2015/460416","DOIUrl":"https://doi.org/10.1155/2015/460416","url":null,"abstract":"TCAD tools have been largely improved in the last decades in order to support both process and device complementary simulations which are usually based on continuously developed models following the technology progress. In this paper, we compare between experimental and TCAD simulated results of two kinds of nanoscale devices: ultrathin body (UTB) and nanoscale Body (NSB) SOI-MOSFET devices, sharing the same W/L ratio but having a channel thickness ratio of 10 : 1 (46 nm and 4.6 nm, resp.). The experimental transfer I-V characteristics were found to be surprisingly different by several orders of magnitude. We analyzed this result by considering the severe mobility degradation and the influence of a large gate voltage dependent series resistance (). TCAD tools do not usually consider to be either channel thickness or gate voltage dependent. After observing a clear discrepancy between the mobility values extracted from our measurements and those modeled by the available TCAD models, we propose a new semiempirical approach to model the transfer characteristics.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2015-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2015/460416","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64975390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel control method is proposed for the three-phase four-wire four-leg active power filter (APF) to realize the accurate and real-time compensation of harmonic of power system, which combines space vector pulse width modulation (SVPWM) with triangle modulation strategy. Firstly, the basic principle of the APF is briefly described. Then the harmonic and reactive currents are derived by the instantaneous reactive power theory. Finally simulation and experiment are built to verify the validity and effectiveness of the proposed method. The simulation results show that the response time for compensation is about 0.025 sec and the total harmonic distortion (THD) of the source current of phase is reduced from 33.38% before compensation to 3.05% with APF.
{"title":"Control for the Three-Phase Four-Wire Four-Leg APF Based on SVPWM and Average Current Method","authors":"Xiangshun Li, Jiang-hua Lu","doi":"10.1155/2015/528360","DOIUrl":"https://doi.org/10.1155/2015/528360","url":null,"abstract":"A novel control method is proposed for the three-phase four-wire four-leg active power filter (APF) to realize the accurate and real-time compensation of harmonic of power system, which combines space vector pulse width modulation (SVPWM) with triangle modulation strategy. Firstly, the basic principle of the APF is briefly described. Then the harmonic and reactive currents are derived by the instantaneous reactive power theory. Finally simulation and experiment are built to verify the validity and effectiveness of the proposed method. The simulation results show that the response time for compensation is about 0.025 sec and the total harmonic distortion (THD) of the source current of phase is reduced from 33.38% before compensation to 3.05% with APF.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2015-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2015/528360","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"65016553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Amit Krishna Dwivedi, Kumar Abhijeet Urma, A. Islam
This paper proposes a circuit capable of incorporating buffered delays in the order of picoseconds. To study our proposed circuit in the profound way, we have also explored our proposed circuit using emerging technologies such as FinFET and CNFET. Comparisons between these technologies have been made in terms of different parameters such as duration of incorporated delays (pulse width) and its variability with supply voltages. Further, this paper also proposes a trigger pulse generator by utilizing proposed buffered delay circuit as its basic element. Parametric results obtained for the proposed trigger pulse generator match different application specific requirements. These applications are also mentioned in this paper. The proposed trigger pulse generator requires very low supply voltage (700 mV) and also proves its effectiveness in terms of tunability of pulse width of the generated pulses. The modeling of the circuit has been done using Verilog and the simulation results are extensively verified using SPICE.
{"title":"Trigger Pulse Generator Using Proposed Buffered Delay Model and Its Application","authors":"Amit Krishna Dwivedi, Kumar Abhijeet Urma, A. Islam","doi":"10.1155/2015/920508","DOIUrl":"https://doi.org/10.1155/2015/920508","url":null,"abstract":"This paper proposes a circuit capable of incorporating buffered delays in the order of picoseconds. To study our proposed circuit in the profound way, we have also explored our proposed circuit using emerging technologies such as FinFET and CNFET. Comparisons between these technologies have been made in terms of different parameters such as duration of incorporated delays (pulse width) and its variability with supply voltages. Further, this paper also proposes a trigger pulse generator by utilizing proposed buffered delay circuit as its basic element. Parametric results obtained for the proposed trigger pulse generator match different application specific requirements. These applications are also mentioned in this paper. The proposed trigger pulse generator requires very low supply voltage (700 mV) and also proves its effectiveness in terms of tunability of pulse width of the generated pulses. The modeling of the circuit has been done using Verilog and the simulation results are extensively verified using SPICE.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2015-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2015/920508","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64162487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work deals with the assessment of gate dielectric for 4H-SiC MOSFETs using technology based two-dimensional numerical computer simulations. Results are studied for variety of gate dielectric candidates with varying thicknesses using well-known Fowler-Nordheim tunneling model. Compared to conventional SiO2 as a gate dielectric for 4H-SiC MOSFETs, high- gate dielectric such as HfO2 reduces significantly the amount of electric field in the gate dielectric with equal gate dielectric thickness and hence the overall gate current density. High- gate dielectric further reduces the shift in the threshold voltage with varying dielectric thicknesses, thus leading to better process margin and stable device operating behavior. For fixed dielectric thickness, a total shift in the threshold voltage of about 2.5 V has been observed with increasing dielectric constant from SiO2 () to HfO2 (). This further results in higher transconductance of the device with the increase of the dielectric constant from SiO2 to HfO2. Furthermore, 4H-SiC MOSFETs are found to be more sensitive to the shift in the threshold voltage with conventional SiO2 as gate dielectric than high-k dielectric with the presence of interface state charge density that is typically observed at the interface of dielectric and 4H-SiC MOS surface.
{"title":"On the Evaluation of Gate Dielectrics for 4H-SiC Based Power MOSFETs","authors":"M. Nawaz","doi":"10.1155/2015/651527","DOIUrl":"https://doi.org/10.1155/2015/651527","url":null,"abstract":"This work deals with the assessment of gate dielectric for 4H-SiC MOSFETs using technology based two-dimensional numerical computer simulations. Results are studied for variety of gate dielectric candidates with varying thicknesses using well-known Fowler-Nordheim tunneling model. Compared to conventional SiO2 as a gate dielectric for 4H-SiC MOSFETs, high- gate dielectric such as HfO2 reduces significantly the amount of electric field in the gate dielectric with equal gate dielectric thickness and hence the overall gate current density. High- gate dielectric further reduces the shift in the threshold voltage with varying dielectric thicknesses, thus leading to better process margin and stable device operating behavior. For fixed dielectric thickness, a total shift in the threshold voltage of about 2.5 V has been observed with increasing dielectric constant from SiO2 () to HfO2 (). This further results in higher transconductance of the device with the increase of the dielectric constant from SiO2 to HfO2. Furthermore, 4H-SiC MOSFETs are found to be more sensitive to the shift in the threshold voltage with conventional SiO2 as gate dielectric than high-k dielectric with the presence of interface state charge density that is typically observed at the interface of dielectric and 4H-SiC MOS surface.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2015-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2015/651527","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"65082246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The saturation regime of two types of fully depleted (FD) SOI MOSFET devices was studied. Ultrathin body (UTB) and gate recessed channel (GRC) devices were fabricated simultaneously on the same silicon wafer through a selective “gate recessed” process. They share the same W/L ratio but have a channel film thickness of 46 nm and 2.2 nm, respectively. Their standard characteristics ( and ) of the devices were measured at room temperature before cooling down to 77 K. Surprisingly, their respective temperature dependence is found to be opposite. In this paper, we focus our comparative analysis on the devices' conduction using a Y-function applied to the saturation domain. The influence of the temperature in this domain is presented for the first time. We point out the limits of the Y-function analysis and show that a new function called Z can be used to extract the series resistance in the saturation regime.
{"title":"Investigation of the Low-Temperature Behavior of FD-SOI MOSFETs in the Saturation Regime Using and Functions","authors":"A. Karsenty, A. Chelly","doi":"10.1155/2014/782417","DOIUrl":"https://doi.org/10.1155/2014/782417","url":null,"abstract":"The saturation regime of two types of fully depleted (FD) SOI MOSFET devices was studied. Ultrathin body (UTB) and gate recessed channel (GRC) devices were fabricated simultaneously on the same silicon wafer through a selective “gate recessed” process. They share the same W/L ratio but have a channel film thickness of 46 nm and 2.2 nm, respectively. Their standard characteristics ( and ) of the devices were measured at room temperature before cooling down to 77 K. Surprisingly, their respective temperature dependence is found to be opposite. In this paper, we focus our comparative analysis on the devices' conduction using a Y-function applied to the saturation domain. The influence of the temperature in this domain is presented for the first time. We point out the limits of the Y-function analysis and show that a new function called Z can be used to extract the series resistance in the saturation regime.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2014-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2014/782417","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64667577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The purpose of this paper is to study high voltage interactions in polymer thick film resistors, namely, polyvinyl chloride- (PVC-) graphite thick film resistors, and their applications in universal trimming of these resistors. High voltages in the form of impulses for various pulse durations and with different amplitudes have been applied to polymer thick film resistors and we observed the variation of resistance of these resistors with high voltages. It has been found that the resistance of polymer thick film resistors decreases in the case of higher resistivity materials and the resistance of polymer thick film resistor increases in the case of lower resistivity materials when high voltage impulses are applied to them. It has been also found that multiple high voltage pulse (MHVP) stressing can be used to trim the polymer thick film resistors either upwards or downwards.
{"title":"Multiple High Voltage Pulse Stressing of Polymer Thick Film Resistors","authors":"B. Rambabu, Y. Rao","doi":"10.1155/2014/319213","DOIUrl":"https://doi.org/10.1155/2014/319213","url":null,"abstract":"The purpose of this paper is to study high voltage interactions in polymer thick film resistors, namely, polyvinyl chloride- (PVC-) graphite thick film resistors, and their applications in universal trimming of these resistors. High voltages in the form of impulses for various pulse durations and with different amplitudes have been applied to polymer thick film resistors and we observed the variation of resistance of these resistors with high voltages. It has been found that the resistance of polymer thick film resistors decreases in the case of higher resistivity materials and the resistance of polymer thick film resistor increases in the case of lower resistivity materials when high voltage impulses are applied to them. It has been also found that multiple high voltage pulse (MHVP) stressing can be used to trim the polymer thick film resistors either upwards or downwards.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2014-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2014/319213","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64438970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A Differential Voltage Current Conveyor Transconductance Amplifier (DVCCTA) based versatile modulator is proposed which can work as an amplitude modulator, frequency modulator, delta modulator, and sigma delta modulator. The modulator operational scheme uses pulse generator as a core and its output is used as carrier signal. A DVCCTA based pulse generator is proposed first and subsequently configured as different modulators. Compact realization is the key feature of the proposed circuit as it uses two DVCCTA; a grounded resistor and a grounded capacitor hence are appropriate for IC realization. The functionality of the proposed circuit is verified through SPICE simulations using TSMC 0.25 μm CMOS process model parameters. The performance parameters such as power dissipation and noise for various modulator schemes are also obtained.
{"title":"Realization of DVCCTA Based Versatile Modulator","authors":"N. Pandey, R. Pandey, Aseem Sayal, M. Tripathi","doi":"10.1155/2014/342785","DOIUrl":"https://doi.org/10.1155/2014/342785","url":null,"abstract":"A Differential Voltage Current Conveyor Transconductance Amplifier (DVCCTA) based versatile modulator is proposed which can work as an amplitude modulator, frequency modulator, delta modulator, and sigma delta modulator. The modulator operational scheme uses pulse generator as a core and its output is used as carrier signal. A DVCCTA based pulse generator is proposed first and subsequently configured as different modulators. Compact realization is the key feature of the proposed circuit as it uses two DVCCTA; a grounded resistor and a grounded capacitor hence are appropriate for IC realization. The functionality of the proposed circuit is verified through SPICE simulations using TSMC 0.25 μm CMOS process model parameters. The performance parameters such as power dissipation and noise for various modulator schemes are also obtained.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2014-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2014/342785","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64447290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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