Transformerless photovoltaic (PV) power system is very promising due to its low cost, small size, and high efficiency. One of its most important issues is how to prevent the common mode leakage current. In order to solve the problem, a new inverter is proposed in this paper. The system common mode model is established, and the four operation modes of the inverter are analyzed. It reveals that the common mode voltage can be kept constant, and consequently the leakage current can be suppressed. Finally, the experimental tests are conducted. The experimental results verify the effectiveness of the proposed solution.
{"title":"A Novel Inverter Topology for Single-Phase Transformerless PV System","authors":"H. Cao","doi":"10.1155/2016/1962438","DOIUrl":"https://doi.org/10.1155/2016/1962438","url":null,"abstract":"Transformerless photovoltaic (PV) power system is very promising due to its low cost, small size, and high efficiency. One of its most important issues is how to prevent the common mode leakage current. In order to solve the problem, a new inverter is proposed in this paper. The system common mode model is established, and the four operation modes of the inverter are analyzed. It reveals that the common mode voltage can be kept constant, and consequently the leakage current can be suppressed. Finally, the experimental tests are conducted. The experimental results verify the effectiveness of the proposed solution.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2016-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2016/1962438","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64253627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The accurate prediction of the SiC MOSFET withstanding time for single fault events greatly influences the requirements for device protection circuits for these devices in power converter applications, like voltage source inverters or power electronic transformers. For this reason, a thermal model, based on the structural design and the physical dimensions of the chip as well as material properties of 4H-SiC, is proposed. This article gives a general description of the thermal behaviour of vertical SiC MOSFET under various driving and boundary conditions in case of a short-circuit event. The thermal model substitutes destructive tests of a device for an individual set of boundary conditions of an occurring fault event. The validity of the analytically parametrised thermal model is verified by experimental short-circuit tests of state-of-the-art vertical SiC MOSFETs for a set of various boundary conditions. The investigated thermal model can furthermore be used to standardise different gate-oxide degradation values from the literature for means of lifetime prediction of the gate oxide for an individual application under repetitive occurring fault or overload conditions. These manufacturer specific reported values measured with no standardised testing procedures can be translated into a maximum junction temperature, which is repeatedly reached. The thermal model therefore provides a unifying parameter for the gate-oxide lifetime calculation for an individual chip and application.
SiC MOSFET对单次故障事件耐受时间的准确预测，极大地影响了电压源逆变器或电力电子变压器等功率变换器应用中对这些器件的器件保护电路的要求。因此，基于芯片的结构设计和物理尺寸以及4H-SiC的材料特性，提出了一种热模型。本文对垂直SiC MOSFET在各种驱动和边界条件下发生短路时的热行为进行了一般描述。热模型用一个装置的破坏性试验来代替一个正在发生的故障事件的一组单独的边界条件。通过在不同边界条件下对最先进的垂直SiC mosfet进行短路实验，验证了解析参数化热模型的有效性。所研究的热模型还可以用于标准化文献中不同的栅极氧化物降解值，以便在重复发生故障或过载条件下对单个应用的栅极氧化物进行寿命预测。这些制造商特定的报告值测量没有标准化的测试程序可以转化为最大结温，这是反复达到。因此，热模型为单个芯片和应用的栅极氧化寿命计算提供了统一的参数。
{"title":"A Structural Based Thermal Model Description for Vertical SiC Power MOSFETs under Fault Conditions","authors":"A. Maerz, Teresa Bertelshofer, M. Bakran","doi":"10.1155/2016/9414901","DOIUrl":"https://doi.org/10.1155/2016/9414901","url":null,"abstract":"The accurate prediction of the SiC MOSFET withstanding time for single fault events greatly influences the requirements for device protection circuits for these devices in power converter applications, like voltage source inverters or power electronic transformers. For this reason, a thermal model, based on the structural design and the physical dimensions of the chip as well as material properties of 4H-SiC, is proposed. This article gives a general description of the thermal behaviour of vertical SiC MOSFET under various driving and boundary conditions in case of a short-circuit event. The thermal model substitutes destructive tests of a device for an individual set of boundary conditions of an occurring fault event. The validity of the analytically parametrised thermal model is verified by experimental short-circuit tests of state-of-the-art vertical SiC MOSFETs for a set of various boundary conditions. The investigated thermal model can furthermore be used to standardise different gate-oxide degradation values from the literature for means of lifetime prediction of the gate oxide for an individual application under repetitive occurring fault or overload conditions. These manufacturer specific reported values measured with no standardised testing procedures can be translated into a maximum junction temperature, which is repeatedly reached. The thermal model therefore provides a unifying parameter for the gate-oxide lifetime calculation for an individual chip and application.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2016-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2016/9414901","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64613646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper reconsiders the mathematical formulation of the conventional nonparabolic band model and proposes a model of the effective mass of conduction band electrons including the nonparabolicity of the conduction band. It is demonstrated that this model produces realistic results for a sub-10-nm-thick Si layer surrounded by an SiO2 layer. The major part of the discussion is focused on the low-dimensional electron system confined with insulator barriers. To examine the feasibility of our consideration, the model is applied to the threshold voltage of nanoscale SOI FinFETs and compared to prior experimental results. This paper also addresses a model of the effective mass of valence band holes assuming the nonparabolic condition.
{"title":"Impact of Band Nonparabolicity on Threshold Voltage of Nanoscale SOI MOSFET","authors":"Y. Omura","doi":"10.1155/2016/6068171","DOIUrl":"https://doi.org/10.1155/2016/6068171","url":null,"abstract":"This paper reconsiders the mathematical formulation of the conventional nonparabolic band model and proposes a model of the effective mass of conduction band electrons including the nonparabolicity of the conduction band. It is demonstrated that this model produces realistic results for a sub-10-nm-thick Si layer surrounded by an SiO2 layer. The major part of the discussion is focused on the low-dimensional electron system confined with insulator barriers. To examine the feasibility of our consideration, the model is applied to the threshold voltage of nanoscale SOI FinFETs and compared to prior experimental results. This paper also addresses a model of the effective mass of valence band holes assuming the nonparabolic condition.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2016-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2016/6068171","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64456737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Chaoui, O. Aghzout, Mounia Chakkour, M. E. Yakhloufi
A novel optimized apodization of Fiber Bragg Grating Sensor (FBGS) for quasi-distributed strain sensing applications is developed and introduced in this paper. The main objective of the proposed optimization is to obtain a reflectivity level higher than 90% and a side lobe level around −40 dB, which is suitable for use in quasi-distributed strain sensing application. For this purpose, different design parameters as apodization profile, grating length, and refractive index have been investigated to enhance and optimize the FBGS design. The performance of the proposed apodization has then been compared in terms of reflectivity, side lobe level (SLL), and full width at half maximum (FWHM) with apodization profiles proposed by other authors. The optimized sensor is integrated on quasi-distributed sensing system of 8 sensors demonstrating high reliability. Wide strain sensitivity range for each channel has also been achieved in the quasi-distributed system. Results prove the efficiency of the proposed optimization which can be further implemented for any quasi-distributed sensing application.
{"title":"Apodization Optimization of FBG Strain Sensor for Quasi-Distributed Sensing Measurement Applications","authors":"F. Chaoui, O. Aghzout, Mounia Chakkour, M. E. Yakhloufi","doi":"10.1155/2016/6523046","DOIUrl":"https://doi.org/10.1155/2016/6523046","url":null,"abstract":"A novel optimized apodization of Fiber Bragg Grating Sensor (FBGS) for quasi-distributed strain sensing applications is developed and introduced in this paper. The main objective of the proposed optimization is to obtain a reflectivity level higher than 90% and a side lobe level around −40 dB, which is suitable for use in quasi-distributed strain sensing application. For this purpose, different design parameters as apodization profile, grating length, and refractive index have been investigated to enhance and optimize the FBGS design. The performance of the proposed apodization has then been compared in terms of reflectivity, side lobe level (SLL), and full width at half maximum (FWHM) with apodization profiles proposed by other authors. The optimized sensor is integrated on quasi-distributed sensing system of 8 sensors demonstrating high reliability. Wide strain sensitivity range for each channel has also been achieved in the quasi-distributed system. Results prove the efficiency of the proposed optimization which can be further implemented for any quasi-distributed sensing application.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2016-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2016/6523046","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64482457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, a compact narrow-bandpass filter with high selectivity and improved rejection level is presented. For miniaturization, a pair of double negative (DNG) cells consisting of quasi-planar chiral resonators are cascaded and electrically loaded to a microstrip transmission line; short ended stubs are introduced to expand upper rejection band. The structure is analyzed using equivalent circuit models and simulated based on EM simulation software. For validation, the proposed filter is fabricated and measured. The measured results are in good agreement with the simulated ones. By comparing to other filters in the references, it is shown that the proposed filter has the advantage of skirt selectivity and compact size, so it can be integrated more conveniently in modern wireless communication systems and microwave planar circuits.
{"title":"Design of a Narrow Bandwidth Bandpass Filter Using Compact Spiral Resonator with Chirality","authors":"Weiping Li, Z. Tang, Xin Cao","doi":"10.1155/2016/7074392","DOIUrl":"https://doi.org/10.1155/2016/7074392","url":null,"abstract":"In this article, a compact narrow-bandpass filter with high selectivity and improved rejection level is presented. For miniaturization, a pair of double negative (DNG) cells consisting of quasi-planar chiral resonators are cascaded and electrically loaded to a microstrip transmission line; short ended stubs are introduced to expand upper rejection band. The structure is analyzed using equivalent circuit models and simulated based on EM simulation software. For validation, the proposed filter is fabricated and measured. The measured results are in good agreement with the simulated ones. By comparing to other filters in the references, it is shown that the proposed filter has the advantage of skirt selectivity and compact size, so it can be integrated more conveniently in modern wireless communication systems and microwave planar circuits.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2016-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2016/7074392","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64504323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Akinori Hariya, K. Matsuura, H. Yanagi, S. Tomioka, Y. Ishizuka, T. Ninomiya
Recently, high power-density, high power-efficiency, and wide regulation range isolated DC-DC converters have been required. This paper presents considerations of physical design and implementation for wide regulation range MHz-level LLC resonant DC-DC converters. The circuit parameters are designed with 3–5 MHz-level switching frequency. Also, the physical parameters and the size of the planar transformer are optimized by using derived equations and finite element method (FEM) with Maxwell 3D. Some experiments are done with prototype LLC resonant DC-DC converter using gallium nitride high electron mobility transistors (GaN-HEMTs); the input voltage is 42–53 V, the reference output voltage is 12 V, the load current is 8 A, the maximum switching frequency is about 5 MHz, the total volume of the circuit is 4.1 cm3, and the power density of the prototype converter is 24.4 W/cc.
{"title":"Considerations of Physical Design and Implementation for 5 MHz-100 W LLC Resonant DC-DC Converters","authors":"Akinori Hariya, K. Matsuura, H. Yanagi, S. Tomioka, Y. Ishizuka, T. Ninomiya","doi":"10.1155/2016/4027406","DOIUrl":"https://doi.org/10.1155/2016/4027406","url":null,"abstract":"Recently, high power-density, high power-efficiency, and wide regulation range isolated DC-DC converters have been required. This paper presents considerations of physical design and implementation for wide regulation range MHz-level LLC resonant DC-DC converters. The circuit parameters are designed with 3–5 MHz-level switching frequency. Also, the physical parameters and the size of the planar transformer are optimized by using derived equations and finite element method (FEM) with Maxwell 3D. Some experiments are done with prototype LLC resonant DC-DC converter using gallium nitride high electron mobility transistors (GaN-HEMTs); the input voltage is 42–53 V, the reference output voltage is 12 V, the load current is 8 A, the maximum switching frequency is about 5 MHz, the total volume of the circuit is 4.1 cm3, and the power density of the prototype converter is 24.4 W/cc.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2016-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2016/4027406","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64362220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jiangwei Liu, Hong Zhao, Jinlong Liu, A. Maréchal, Wei Wang
1Research Center for Functional Materials, National Institute for Materials Science, 1-1 Namiki, Tsukuba, Ibaraki 3050044, Japan 2Department of Materials Science and Engineering, Wuhan Institute of Technology, Wuhan 430073, China 3School of Materials Science and Engineering, University of Science and Technology Beijing, Beijing 100083, China 4School of Electronic and Information Engineering, Xi’an Jiaotong University, Xi’an, Shaanxi 710049, China
{"title":"Semiconductors: Materials, Physics, and Devices","authors":"Jiangwei Liu, Hong Zhao, Jinlong Liu, A. Maréchal, Wei Wang","doi":"10.1155/2016/4523960","DOIUrl":"https://doi.org/10.1155/2016/4523960","url":null,"abstract":"1Research Center for Functional Materials, National Institute for Materials Science, 1-1 Namiki, Tsukuba, Ibaraki 3050044, Japan 2Department of Materials Science and Engineering, Wuhan Institute of Technology, Wuhan 430073, China 3School of Materials Science and Engineering, University of Science and Technology Beijing, Beijing 100083, China 4School of Electronic and Information Engineering, Xi’an Jiaotong University, Xi’an, Shaanxi 710049, China","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2016-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2016/4523960","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64386009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nanoscale Gate-Recessed Channel (GRC) Fully Depleted- (FD-) SOI MOSFET device with a silicon channel thickness () as low as 2.2 nm was first tested at room temperature for functionality check and then tested at low temperature (77 K) for characterizations. In spite of its FD-SOI nanoscale thickness and long channel feature, the device has surprisingly exhibited a Drain-Induced Barrier Lowering (DIBL) effect at RT. However, this effect was suppressed at 77 K. If the apparition of such anomalous effect can be explained by a parasitic short channel transistor located at the edges of the channel, its suppression is explained by the decrease of the potential barrier between the drain and the channel when lowering the temperature.
首先在室温下测试了硅沟道厚度()低至2.2 nm的纳米栅极凹槽(GRC)完全耗尽- (FD-) SOI MOSFET器件的功能检查，然后在低温(77 K)下进行了表征测试。尽管其FD-SOI具有纳米级厚度和长沟道特性，但该器件在室温下令人惊讶地表现出漏极诱导势垒降低(DIBL)效应。然而，这种效应在77 K时被抑制。如果这种异常效应的出现可以用位于沟道边缘的寄生短沟道晶体管来解释，那么它的抑制可以用降低温度时漏极和沟道之间的势垒降低来解释。
{"title":"Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process","authors":"A. Karsenty, A. Chelly","doi":"10.1155/2015/609828","DOIUrl":"https://doi.org/10.1155/2015/609828","url":null,"abstract":"Nanoscale Gate-Recessed Channel (GRC) Fully Depleted- (FD-) SOI MOSFET device with a silicon channel thickness () as low as 2.2 nm was first tested at room temperature for functionality check and then tested at low temperature (77 K) for characterizations. In spite of its FD-SOI nanoscale thickness and long channel feature, the device has surprisingly exhibited a Drain-Induced Barrier Lowering (DIBL) effect at RT. However, this effect was suppressed at 77 K. If the apparition of such anomalous effect can be explained by a parasitic short channel transistor located at the edges of the channel, its suppression is explained by the decrease of the potential barrier between the drain and the channel when lowering the temperature.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2015-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2015/609828","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"65056623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a high efficiency Li-ion battery LDO-based charger IC which adopted a three-mode control: trickle constant current, fast constant current, and constant voltage modes. The criteria of the proposed Li-ion battery charger, including high accuracy, high efficiency, and low size area, are of high importance. The simulation results provide the trickle current of 116 mA, maximum charging current of 448 mA, and charging voltage of 4.21 V at the power supply of 4.8–5 V, using 0.18 μm CMOS technology.
{"title":"A High Efficiency Li-Ion Battery LDO-Based Charger for Portable Application","authors":"Youssef Ziadi, H. Qjidaa","doi":"10.1155/2015/591986","DOIUrl":"https://doi.org/10.1155/2015/591986","url":null,"abstract":"This paper presents a high efficiency Li-ion battery LDO-based charger IC which adopted a three-mode control: trickle constant current, fast constant current, and constant voltage modes. The criteria of the proposed Li-ion battery charger, including high accuracy, high efficiency, and low size area, are of high importance. The simulation results provide the trickle current of 116 mA, maximum charging current of 448 mA, and charging voltage of 4.21 V at the power supply of 4.8–5 V, using 0.18 μm CMOS technology.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2015-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2015/591986","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"65048196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The speckle interferometry technique has been used in this work in order to determine the thermomechanical behaviour of Printed Wiring Board (PWB) (circuits) of a radio integrated with tape player and speakers. A preliminary experiment of such technique has been carried out on a single electronic component (silicon transistor), during the thermal transient and at the steady state. The thermal deformation and stresses on PWB have been obtained through related experimental analyses on both cases. The results showed a very good applicability of speckle technique on the irregular object surface as PWB.
{"title":"Thermomechanical Behaviour of a PWB by Speckle Interferometry Technique","authors":"B. Trentadue, Giuseppe Illuzzi","doi":"10.1155/2015/141583","DOIUrl":"https://doi.org/10.1155/2015/141583","url":null,"abstract":"The speckle interferometry technique has been used in this work in order to determine the thermomechanical behaviour of Printed Wiring Board (PWB) (circuits) of a radio integrated with tape player and speakers. A preliminary experiment of such technique has been carried out on a single electronic component (silicon transistor), during the thermal transient and at the steady state. The thermal deformation and stresses on PWB have been obtained through related experimental analyses on both cases. The results showed a very good applicability of speckle technique on the irregular object surface as PWB.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2015-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2015/141583","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64804043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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