Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579829
O. Paker, K. van Berkel, K. Moerman
Communication over a MIMO (multiple-input-multiple-output) channel promises several advantages: increase in channel capacity, reduced transmit power, greater coverage, and improved link robustness. The minimum mean squared error equalizer (MMSE) is a potential algorithm in addressing the MIMO detection challenge. This paper presents four implementations for the computation of the MMSE equalizer coefficients. The studied options are: (1) a general-purpose microprocessor (ARM926EJ-S); (2) a traditional general purpose DSP (RD16024); (3) an embedded vector processor (EVP/sub 16/); and (4) a dedicated hardware solution. We show that, the equalizer requires acceleration for real-time processing. In order to obtain a low cost, flexible multi-standard WLAN baseband implementation, EVP/sub 16/ is the only feasible solution among the four studied.
{"title":"Hardware and software implementations of an MMSE equalizer for MIMO-OFDM based WLAN","authors":"O. Paker, K. van Berkel, K. Moerman","doi":"10.1109/SIPS.2005.1579829","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579829","url":null,"abstract":"Communication over a MIMO (multiple-input-multiple-output) channel promises several advantages: increase in channel capacity, reduced transmit power, greater coverage, and improved link robustness. The minimum mean squared error equalizer (MMSE) is a potential algorithm in addressing the MIMO detection challenge. This paper presents four implementations for the computation of the MMSE equalizer coefficients. The studied options are: (1) a general-purpose microprocessor (ARM926EJ-S); (2) a traditional general purpose DSP (RD16024); (3) an embedded vector processor (EVP/sub 16/); and (4) a dedicated hardware solution. We show that, the equalizer requires acceleration for real-time processing. In order to obtain a low cost, flexible multi-standard WLAN baseband implementation, EVP/sub 16/ is the only feasible solution among the four studied.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127260739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579842
A. Hermanek, J. Schier, P. Šůcha, Z. Hanzálek
The paper deals with optimization of an FPGA implementation of iterative algorithms with nested loops, using integer linear programming. The scheduling is demonstrated on an example of the FI-CMA blind equalization algorithm, with implementation using limited (and small) number of arithmetic units with non-zero latency. The optimization is based on cyclic scheduling with precedence delays for distinct dedicated processors. The approach is based on construction of an optimally scheduled abstract model, modeling imperfectly nested loops.
{"title":"Optimization of finite interval CMA implementation for FPGA","authors":"A. Hermanek, J. Schier, P. Šůcha, Z. Hanzálek","doi":"10.1109/SIPS.2005.1579842","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579842","url":null,"abstract":"The paper deals with optimization of an FPGA implementation of iterative algorithms with nested loops, using integer linear programming. The scheduling is demonstrated on an example of the FI-CMA blind equalization algorithm, with implementation using limited (and small) number of arithmetic units with non-zero latency. The optimization is based on cyclic scheduling with precedence delays for distinct dedicated processors. The approach is based on construction of an optimally scheduled abstract model, modeling imperfectly nested loops.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129115296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579949
T. Migita, V. Moshnyaga
This paper presents a simple yet efficient technique to reduce computations of bidirectional block-matching motion estimation. Unlike existing formulations, we reuse motion vectors obtained for P-frame to omit unnecessary motion vector calculations for bi directionally predicted B-frame. Experimental results show that such an enhancement lowers complexity of bidirectional motion estimation as much as 1/3 without visible impact on subjective picture quality.
{"title":"An algorithmic enhancement for reducing computations of bidirectional motion estimation","authors":"T. Migita, V. Moshnyaga","doi":"10.1109/SIPS.2005.1579949","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579949","url":null,"abstract":"This paper presents a simple yet efficient technique to reduce computations of bidirectional block-matching motion estimation. Unlike existing formulations, we reuse motion vectors obtained for P-frame to omit unnecessary motion vector calculations for bi directionally predicted B-frame. Experimental results show that such an enhancement lowers complexity of bidirectional motion estimation as much as 1/3 without visible impact on subjective picture quality.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129740805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579854
M. Halima, M. Fakhfakh, M. Loulou
In this paper we present a switched current based macrocell block dedicated for field programmable analogue arrays. The macrocell uses a combination of class A switched current cells performing programmable basic analogue signal processing multifunction. In fact, by means of a set of static switches it allows us to configure basic linear discrete time functions such as lossless and damped integrators and differentiators. The proposed macrocell gets profit from the flexibility of switched current techniques implementing programmable filters, oscillators, control systems, and both ADC and DAC blocks. The present work highlights the main idea and a validation of the planned functions. Simulation results are presented showing the functionality of some examples.
{"title":"A switched current based FPAA macrocell for mixed mode signal processing systems","authors":"M. Halima, M. Fakhfakh, M. Loulou","doi":"10.1109/SIPS.2005.1579854","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579854","url":null,"abstract":"In this paper we present a switched current based macrocell block dedicated for field programmable analogue arrays. The macrocell uses a combination of class A switched current cells performing programmable basic analogue signal processing multifunction. In fact, by means of a set of static switches it allows us to configure basic linear discrete time functions such as lossless and damped integrators and differentiators. The proposed macrocell gets profit from the flexibility of switched current techniques implementing programmable filters, oscillators, control systems, and both ADC and DAC blocks. The present work highlights the main idea and a validation of the planned functions. Simulation results are presented showing the functionality of some examples.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130763161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579942
Yan Zhang, A. Mammela
Look-up table (LUT) is one of the most popular methods for simulating the nonlinear characteristics of radio frequency (RF) power amplifiers. In this paper two practical methods for minimizing the LUT size are assessed for fast and flexible simulations using field programmable gate array (FPGA) circuits. They are cubic-spline interpolation and segmented nonuniform table indexing methods. The implementation architectures for these two approaches were developed and implemented. In addition, a suitable evaluation criterion for this kind of new applications is proposed in this paper. Implementation complexity and goodness of curve reconstruction were both considered so that the evaluation process could be more accurate and complete. The numerical comparisons show that the reconstruction performance of the cubic-spline interpolation method outperforms the nonuniform table indexing method dramatically by the sacrifice of a number of multipliers and double memory resources. The results also show that different segmentation schemes can considerably affect the performance of the segmented nonuniform indexing method.
{"title":"Comparison of look-up table minimization methods for real-time power amplifier simulation","authors":"Yan Zhang, A. Mammela","doi":"10.1109/SIPS.2005.1579942","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579942","url":null,"abstract":"Look-up table (LUT) is one of the most popular methods for simulating the nonlinear characteristics of radio frequency (RF) power amplifiers. In this paper two practical methods for minimizing the LUT size are assessed for fast and flexible simulations using field programmable gate array (FPGA) circuits. They are cubic-spline interpolation and segmented nonuniform table indexing methods. The implementation architectures for these two approaches were developed and implemented. In addition, a suitable evaluation criterion for this kind of new applications is proposed in this paper. Implementation complexity and goodness of curve reconstruction were both considered so that the evaluation process could be more accurate and complete. The numerical comparisons show that the reconstruction performance of the cubic-spline interpolation method outperforms the nonuniform table indexing method dramatically by the sacrifice of a number of multipliers and double memory resources. The results also show that different segmentation schemes can considerably affect the performance of the segmented nonuniform indexing method.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130908901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579857
E. Castillo, L. Parrilla, A. García, A. Lloris, U. Meyer-Baese
This paper present a new procedure for intellectual property protection (IPP) of circuits based on the residue number system (RNS). The aim is to protect the author rights of reusable IP cores by means of an electronic digital signature that uniquely identifies both the original design and the design recipient. The signature embedding stores the digital signature in non-used positions of look-up tables of RNS-based designs. This embedding does not increase the area of the system. A procedure for signature extraction is also included, so it is possible to detect the ownership right without interfering the normal operation of the system. This signature extraction requires some extra hardware, basically additional logic and some multiplexers. As an example, a 160-bit signature is introduced into a FIR filter. The presented IPP design examples are implemented over FPL devices and cell-based ASICs with negligible performance penalties.
{"title":"Watermarking strategies for RNS-based system intellectual property protection","authors":"E. Castillo, L. Parrilla, A. García, A. Lloris, U. Meyer-Baese","doi":"10.1109/SIPS.2005.1579857","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579857","url":null,"abstract":"This paper present a new procedure for intellectual property protection (IPP) of circuits based on the residue number system (RNS). The aim is to protect the author rights of reusable IP cores by means of an electronic digital signature that uniquely identifies both the original design and the design recipient. The signature embedding stores the digital signature in non-used positions of look-up tables of RNS-based designs. This embedding does not increase the area of the system. A procedure for signature extraction is also included, so it is possible to detect the ownership right without interfering the normal operation of the system. This signature extraction requires some extra hardware, basically additional logic and some multiplexers. As an example, a 160-bit signature is introduced into a FIR filter. The presented IPP design examples are implemented over FPL devices and cell-based ASICs with negligible performance penalties.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131383549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579831
M. Crepaldi, M. Casu, M. Graziano
Ultra wide band (UWB) impulse radio systems are appealing for location-aware applications. There is a growing interest in the design of UWB transceivers with reduced complexity and power consumption. Non-coherent approaches for the design of the receiver based on energy detection schemes seem suitable to this aim and have been adopted in the project the preliminary results of which are reported in this paper. The objective is the design of a UWB receiver with a top-down methodology, starting from Matlab-like models and refining the description down to the final transistor level. This goal will be achieved with an integrated use of VHDL for the digital blocks and VHDL-AMS for the mixed-signal and analog circuits. Coherent results are obtained using VHDL-AMS and Matlab. However, the CPU time cost strongly depends on the description used in the VHDL-AMS models. In order to show the functionality of the UWB architecture, the receiver most critical functions are simulated showing results in good agreement with the expectations.
{"title":"Energy detection UWB receiver design using a multi-resolution VHDL-AMS description","authors":"M. Crepaldi, M. Casu, M. Graziano","doi":"10.1109/SIPS.2005.1579831","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579831","url":null,"abstract":"Ultra wide band (UWB) impulse radio systems are appealing for location-aware applications. There is a growing interest in the design of UWB transceivers with reduced complexity and power consumption. Non-coherent approaches for the design of the receiver based on energy detection schemes seem suitable to this aim and have been adopted in the project the preliminary results of which are reported in this paper. The objective is the design of a UWB receiver with a top-down methodology, starting from Matlab-like models and refining the description down to the final transistor level. This goal will be achieved with an integrated use of VHDL for the digital blocks and VHDL-AMS for the mixed-signal and analog circuits. Coherent results are obtained using VHDL-AMS and Matlab. However, the CPU time cost strongly depends on the description used in the VHDL-AMS models. In order to show the functionality of the UWB architecture, the receiver most critical functions are simulated showing results in good agreement with the expectations.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131267877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579871
F. Pisoni, Marco Bonaventura
Echo cancellation in DMT modems is a means to improve transmission performance. It consists in extending the downstream (DS) and upstream (UP) frequency bands so that they become adjacent or even overlap, and relaxing at the same time the existing filters. Modern cancellers make use of FIR filters that emulate the echo-path, and adaptive algorithms that estimate the correspondent coefficients. In this article, we start from the circulant decomposition canceller (CDC), an efficient algorithm recently developed for ADSL, and explore new kinds of decomposition, based on the diagonalization properties of the discrete cosine and sine transforms (DCT, DST).
{"title":"A multi-carrier echo canceller based on symmetric decomposition","authors":"F. Pisoni, Marco Bonaventura","doi":"10.1109/SIPS.2005.1579871","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579871","url":null,"abstract":"Echo cancellation in DMT modems is a means to improve transmission performance. It consists in extending the downstream (DS) and upstream (UP) frequency bands so that they become adjacent or even overlap, and relaxing at the same time the existing filters. Modern cancellers make use of FIR filters that emulate the echo-path, and adaptive algorithms that estimate the correspondent coefficients. In this article, we start from the circulant decomposition canceller (CDC), an efficient algorithm recently developed for ADSL, and explore new kinds of decomposition, based on the diagonalization properties of the discrete cosine and sine transforms (DCT, DST).","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131167003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579955
I. Krikidis
Parallel interference cancellation (PIC) refers to a family of low-complexity multi-user detection methods for the uplink of direct-sequence code-division multiple-access (DS/CDMA) systems. Recently, it has been viable for the downlink and terminal implementations. The PIC schemes using as "infected" signal the correlation input have a simpler structure, but perform poorly when the spreading factor (SF) is low. In this paper we propose a new PIC scheme which, besides multiple access interference (MAI) suppression to the correlation input performs also inter-path interference (IPI) mitigation to the correlation output. Numerical results for a downlink DS/CDMA system show that the proposed multistage detector optimizes jointly performance and computational power. It approximates the performance of a conventional PIC, suppressing the interference to the correlation output, but it has lower computational complexity. In the same time, the computational similarities and the iterative nature of the different sub-algorithms of the proposed PIC scheme make possible the design of a simple reconfigurable architecture which minimizes the area overhead and the power consumption. These properties are suitable for terminal implementations where the computational power is more critical than for the base stations (BSs).
{"title":"Parallel interference cancellation for DS/CDMA downlink with low spreading factors","authors":"I. Krikidis","doi":"10.1109/SIPS.2005.1579955","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579955","url":null,"abstract":"Parallel interference cancellation (PIC) refers to a family of low-complexity multi-user detection methods for the uplink of direct-sequence code-division multiple-access (DS/CDMA) systems. Recently, it has been viable for the downlink and terminal implementations. The PIC schemes using as \"infected\" signal the correlation input have a simpler structure, but perform poorly when the spreading factor (SF) is low. In this paper we propose a new PIC scheme which, besides multiple access interference (MAI) suppression to the correlation input performs also inter-path interference (IPI) mitigation to the correlation output. Numerical results for a downlink DS/CDMA system show that the proposed multistage detector optimizes jointly performance and computational power. It approximates the performance of a conventional PIC, suppressing the interference to the correlation output, but it has lower computational complexity. In the same time, the computational similarities and the iterative nature of the different sub-algorithms of the proposed PIC scheme make possible the design of a simple reconfigurable architecture which minimizes the area overhead and the power consumption. These properties are suitable for terminal implementations where the computational power is more critical than for the base stations (BSs).","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125295359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579840
M. O. Sanu, E. Swartzlander
In this paper, we describe a novel algorithm for modular exponentiation of large integers and present its hardware implementation. This algorithm combines elements from Montgomery's modular multiplication technique, carry-save and carry-delayed number representations. The major advantage of this algorithm over previously reported algorithms is that it does not require the result of each modular multiplication in the exponentiation process to be converted from the redundant representation back to a nonredundant form. In our algorithm, the conversion is only necessary at the end of all the modular multiplications. Avoiding the conversion speeds up the modular exponentiation process. In addition, the algorithm allows for a fast, modular, and scalable hardware implementation.
{"title":"Hardware design for end-to-end modular exponentiation in redundant number representation","authors":"M. O. Sanu, E. Swartzlander","doi":"10.1109/SIPS.2005.1579840","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579840","url":null,"abstract":"In this paper, we describe a novel algorithm for modular exponentiation of large integers and present its hardware implementation. This algorithm combines elements from Montgomery's modular multiplication technique, carry-save and carry-delayed number representations. The major advantage of this algorithm over previously reported algorithms is that it does not require the result of each modular multiplication in the exponentiation process to be converted from the redundant representation back to a nonredundant form. In our algorithm, the conversion is only necessary at the end of all the modular multiplications. Avoiding the conversion speeds up the modular exponentiation process. In addition, the algorithm allows for a fast, modular, and scalable hardware implementation.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124630697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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