Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951669
R. Bhagavathula, Pritish Chittoor, R. Pendse
Recent advances in VLSI technology have spurred a tremendous increase in the performance of processors. Due to the slower main memory, there exists a bottleneck in the performance of computer systems. Caching is an effective way to reduce these bottlenecks. With increasing cache sizes, the performance of the processor could be enhanced by using advanced block replacement algorithms like LRU etc. However, due to the presence of the cache in the critical timing path, many processors do not employ these advanced replacement policies. In this paper, the authors present an alternative implementation of block replacement algorithms in CPU caches by modifying the processor pipeline to hide the latency involved in the replacement scheme.
{"title":"Pipeline LRU block replacement algorithm","authors":"R. Bhagavathula, Pritish Chittoor, R. Pendse","doi":"10.1109/MWSCAS.2000.951669","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951669","url":null,"abstract":"Recent advances in VLSI technology have spurred a tremendous increase in the performance of processors. Due to the slower main memory, there exists a bottleneck in the performance of computer systems. Caching is an effective way to reduce these bottlenecks. With increasing cache sizes, the performance of the processor could be enhanced by using advanced block replacement algorithms like LRU etc. However, due to the presence of the cache in the critical timing path, many processors do not employ these advanced replacement policies. In this paper, the authors present an alternative implementation of block replacement algorithms in CPU caches by modifying the processor pipeline to hide the latency involved in the replacement scheme.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132883776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.952890
A. Azam, D. Sasidaran, K. Nelson, G. Ford, L. Johnson, M. Soderstrand
Two single-chip designs implement in FPGA's a high-order tunable IIR notch filter using a new digital heterodyne technique. The notch center frequency can be tuned from DC to the Nyquist frequency and the characteristics of the IIR generated notch filter can be re-programmed for specific applications. The first chip is a single-chip version of a filter previously designed using three Xilinx FPGA's. Through Multiplexing and Pipelining it is possible to implement all three chips on one FPGA. The second chip makes use of a reduction in the sin-cos look-up tables to reduce the hardware even more. Both chips offer very flexible adaptive notch filters with the ability to design, a very complex notch without complicating the tuning process. These new single-chip versions offer considerable power and cost advantages over the earlier three-chip version.
{"title":"Single-chip tunable heterodyne notch filters implemented in FPGA's","authors":"A. Azam, D. Sasidaran, K. Nelson, G. Ford, L. Johnson, M. Soderstrand","doi":"10.1109/MWSCAS.2000.952890","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952890","url":null,"abstract":"Two single-chip designs implement in FPGA's a high-order tunable IIR notch filter using a new digital heterodyne technique. The notch center frequency can be tuned from DC to the Nyquist frequency and the characteristics of the IIR generated notch filter can be re-programmed for specific applications. The first chip is a single-chip version of a filter previously designed using three Xilinx FPGA's. Through Multiplexing and Pipelining it is possible to implement all three chips on one FPGA. The second chip makes use of a reduction in the sin-cos look-up tables to reduce the hardware even more. Both chips offer very flexible adaptive notch filters with the ability to design, a very complex notch without complicating the tuning process. These new single-chip versions offer considerable power and cost advantages over the earlier three-chip version.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"982 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134193957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.952900
Wen Wang, M. Swamy, M. Ahmad
In this paper, a new residue-to-binary conversion algorithm, that reduces the size of modulo operation required by the Chinese remainder theorem, is introduced. Based on this algorithm, an efficient residue-to-binary converter is proposed for a general residue number system. The proposed converter achieves a significantly better performance in terms of area, time, and power consumption than existing devices. For the case of the 28-bit dynamic range, the proposed converter is about 20% faster while requiring only 70% of the area, compared to the best existing converter (Srikanthan et al, IEE Proc. Comput. Digit. Tech., vol. 145, no. 3, pp. 229-235, 1998). Also, the power consumption is reduced by 16% in high speed situations and 50% in low voltage situations.
本文提出了一种新的残数到二值的转换算法，该算法减小了中国剩余定理所要求的模运算量。在此基础上，提出了一种适用于一般残数系统的有效残数-二进制转换器。所提出的变换器在面积、时间和功耗方面都比现有器件有显著的提高。对于28位动态范围的情况，与现有最佳转换器(Srikanthan等人，ieee Proc. Comput)相比，所提出的转换器的速度约为20%，而占地面积仅为70%。数字。技术，第145卷，第145号。3，页229-235,1998)。此外，在高速情况下功耗降低16%，在低压情况下功耗降低50%。
{"title":"An area-time-efficient residue-to-binary converter","authors":"Wen Wang, M. Swamy, M. Ahmad","doi":"10.1109/MWSCAS.2000.952900","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952900","url":null,"abstract":"In this paper, a new residue-to-binary conversion algorithm, that reduces the size of modulo operation required by the Chinese remainder theorem, is introduced. Based on this algorithm, an efficient residue-to-binary converter is proposed for a general residue number system. The proposed converter achieves a significantly better performance in terms of area, time, and power consumption than existing devices. For the case of the 28-bit dynamic range, the proposed converter is about 20% faster while requiring only 70% of the area, compared to the best existing converter (Srikanthan et al, IEE Proc. Comput. Digit. Tech., vol. 145, no. 3, pp. 229-235, 1998). Also, the power consumption is reduced by 16% in high speed situations and 50% in low voltage situations.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134220140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951470
D. Kaur, P. Dhanda, M. Mirchandani
This paper describes the implementation of an intelligent chat group based on fuzzy logic. The chat group is based on client server model. The expert system based on fuzzy logic is developed in Java and monitors parameters, like number of clients, the idle time of each client etc., and then determines the priority of each client.
{"title":"Development of a real time chat application on intelligent network based on fuzzy logic","authors":"D. Kaur, P. Dhanda, M. Mirchandani","doi":"10.1109/MWSCAS.2000.951470","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951470","url":null,"abstract":"This paper describes the implementation of an intelligent chat group based on fuzzy logic. The chat group is based on client server model. The expert system based on fuzzy logic is developed in Java and monitors parameters, like number of clients, the idle time of each client etc., and then determines the priority of each client.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134473478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.952814
N. A. Abbasi, C. Zukowski
We simulate a 64Mbps (16Mbaud, 16-PSK) digital communication link operating in a multipath channel. An adaptive equalizer using Least Mean Square algorithm for coefficient update is used to cancel Intersymbol Interference in the receiver. It is shown through computer simulations that system performance can be traded for energy use more intelligently if information about data temporal characteristics is available to the receiver. A simple transversal filter architecture is also presented in which the number of filter taps, and various word sizes can be dynamically adjusted based on temporal characteristics of data.
{"title":"Trading system performance for energy use in a VLSI implementation of an adaptive equalizer","authors":"N. A. Abbasi, C. Zukowski","doi":"10.1109/MWSCAS.2000.952814","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952814","url":null,"abstract":"We simulate a 64Mbps (16Mbaud, 16-PSK) digital communication link operating in a multipath channel. An adaptive equalizer using Least Mean Square algorithm for coefficient update is used to cancel Intersymbol Interference in the receiver. It is shown through computer simulations that system performance can be traded for energy use more intelligently if information about data temporal characteristics is available to the receiver. A simple transversal filter architecture is also presented in which the number of filter taps, and various word sizes can be dynamically adjusted based on temporal characteristics of data.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"139-140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134534398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951696
Huiyan Li, B. Gwee, J.S. Chang, M. T. Tan
A PWM sampling process for low-power digital Class D amplifiers with low harmonic distortion is proposed. By means of a novel algorithm, the Natural Sampling Process is emulated through a Delta-Compensation Uniform Sampling Process. This algorithm features a simple circuit implementation (small IC area), low power operation (low sampling rate) and a highly desirable low harmonic distortion.
{"title":"A novel pulse width modulation sampling process for low power, low distortion digital Class D amplifiers","authors":"Huiyan Li, B. Gwee, J.S. Chang, M. T. Tan","doi":"10.1109/MWSCAS.2000.951696","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951696","url":null,"abstract":"A PWM sampling process for low-power digital Class D amplifiers with low harmonic distortion is proposed. By means of a novel algorithm, the Natural Sampling Process is emulated through a Delta-Compensation Uniform Sampling Process. This algorithm features a simple circuit implementation (small IC area), low power operation (low sampling rate) and a highly desirable low harmonic distortion.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133232928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.952886
H. Abdel-Aty-Zohdy, R. Ewing
Intelligent information processing (IIP) or the smart processing of signals in communication systems and data measurements from multi-sensor systems are needed for advanced microautonomous applications. A balanced combination of efficient algorithms, fast networks, and collaboration of the different technologies are required for smaller, faster, and more efficient system-on-a-chip applications. In this paper we present guidelines/approach for intelligent information processing using neural networks (NNs) and genetic algorithms (GAs) which are capable of learning through discovery and/or reinforcement with features optimization through chromosome mutations of GAs. Specific details about a special application for electronic-nose (EN) implementation to discriminate among four chemicals, using reinforcement NN implemented tiny-chip and a GA system implementation is presented with test results.
{"title":"Intelligent information processing using neural networks and genetic algorithms","authors":"H. Abdel-Aty-Zohdy, R. Ewing","doi":"10.1109/MWSCAS.2000.952886","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952886","url":null,"abstract":"Intelligent information processing (IIP) or the smart processing of signals in communication systems and data measurements from multi-sensor systems are needed for advanced microautonomous applications. A balanced combination of efficient algorithms, fast networks, and collaboration of the different technologies are required for smaller, faster, and more efficient system-on-a-chip applications. In this paper we present guidelines/approach for intelligent information processing using neural networks (NNs) and genetic algorithms (GAs) which are capable of learning through discovery and/or reinforcement with features optimization through chromosome mutations of GAs. Specific details about a special application for electronic-nose (EN) implementation to discriminate among four chemicals, using reinforcement NN implemented tiny-chip and a GA system implementation is presented with test results.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132188512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.952915
S. Pallipatti, K. Ramabadran, S. Ayathu
Timing closure flow for digital designs is referred to as links-to-layout (LTL) flow. The bottlenecks with this flow leads to non-optimal designs. Timing closure becomes totally unpredictable for complex designs and leads to significant increase in overall cost, in terms of die-area and time-to-market. Commercial tools to solve this problem are not yet fully proven and are also very expensive. An optimized LTL flow that addresses the timing and area problems was defined, implemented and verified. Significant improvements in design cycle time (60%-70%) coupled with excellent area gains (7-10%) were obtained using the optimized LTL flow.
{"title":"An optimized links-to-layout flow for timing critical designs","authors":"S. Pallipatti, K. Ramabadran, S. Ayathu","doi":"10.1109/MWSCAS.2000.952915","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952915","url":null,"abstract":"Timing closure flow for digital designs is referred to as links-to-layout (LTL) flow. The bottlenecks with this flow leads to non-optimal designs. Timing closure becomes totally unpredictable for complex designs and leads to significant increase in overall cost, in terms of die-area and time-to-market. Commercial tools to solve this problem are not yet fully proven and are also very expensive. An optimized LTL flow that addresses the timing and area problems was defined, implemented and verified. Significant improvements in design cycle time (60%-70%) coupled with excellent area gains (7-10%) were obtained using the optimized LTL flow.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"2 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114011922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951461
K. Suzuki, A. Nishio, A. Kamo, T. Watanabe, H. Asai
This paper describes an application of the Verilog-A, which is a hardware description language for analog applications, to the modeling of neural networks. We attempt to simulate neural networks having a learning algorithm, which has not been designed with electronic circuits. The learning algorithm is modeled with Verilog-A and the suitable synaptic weights are solved by Verilog-A simulation.
{"title":"An application of Verilog-A to modeling of back propagation algorithm in neural networks","authors":"K. Suzuki, A. Nishio, A. Kamo, T. Watanabe, H. Asai","doi":"10.1109/MWSCAS.2000.951461","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951461","url":null,"abstract":"This paper describes an application of the Verilog-A, which is a hardware description language for analog applications, to the modeling of neural networks. We attempt to simulate neural networks having a learning algorithm, which has not been designed with electronic circuits. The learning algorithm is modeled with Verilog-A and the suitable synaptic weights are solved by Verilog-A simulation.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"87 3-4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114034616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.952901
Jing Wang, E. Sánchez-Sinencio, F. Maloberti
Two very linear ramp-generator designs are presented. The circuits are to be used in high-resolution ADC built-in-self-test (BIST) and on-chip calibration. The first design is used to charge a capacitor by a small current, which is linear enough to test 14-bit ADCs. The second design is in a relaxation oscillator architecture. It is linear enough to test up to 12-bit ADCs. The two designs have been fabricated in CMOS 2 /spl mu/m and 1.2 /spl mu/m processes separately.
{"title":"Very linear ramp-generators for high resolution ADC BIST and calibration","authors":"Jing Wang, E. Sánchez-Sinencio, F. Maloberti","doi":"10.1109/MWSCAS.2000.952901","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952901","url":null,"abstract":"Two very linear ramp-generator designs are presented. The circuits are to be used in high-resolution ADC built-in-self-test (BIST) and on-chip calibration. The first design is used to charge a capacitor by a small current, which is linear enough to test 14-bit ADCs. The second design is in a relaxation oscillator architecture. It is linear enough to test up to 12-bit ADCs. The two designs have been fabricated in CMOS 2 /spl mu/m and 1.2 /spl mu/m processes separately.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124495893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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