Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951615
A. Díaz-Sánchez, J. Ramírez-Angulo
The implementation of CMOS VLSI weighted median filters for image and signal processing analysis using analog circuits is presented. The presented weighted median filter uses a transconductance comparator as a basic cell. The output saturation current characteristic of the transconductance comparator allows modification of the saturation current to be used in weighted order filters. Experimental results of the transconductance comparator are shown. Simulation results of an 249 /spl times/ 209 image corrupted with 15% salt and pepper noise, was used to test the weighted median filter. All the simulations were made using SPICE BSIM3 level 49 model and 1.2 /spl mu/m MOSIS parameters.
{"title":"Analog VLSI weighted median filters","authors":"A. Díaz-Sánchez, J. Ramírez-Angulo","doi":"10.1109/MWSCAS.2000.951615","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951615","url":null,"abstract":"The implementation of CMOS VLSI weighted median filters for image and signal processing analysis using analog circuits is presented. The presented weighted median filter uses a transconductance comparator as a basic cell. The output saturation current characteristic of the transconductance comparator allows modification of the saturation current to be used in weighted order filters. Experimental results of the transconductance comparator are shown. Simulation results of an 249 /spl times/ 209 image corrupted with 15% salt and pepper noise, was used to test the weighted median filter. All the simulations were made using SPICE BSIM3 level 49 model and 1.2 /spl mu/m MOSIS parameters.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127099262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.952875
E. Raisanen-Ruotsalainen, K. Lasanen, J. Kostamovaara
A micropower 1.2 V op amp has been integrated in a 0.35 /spl mu/m CMOS process. Floating-gate input transistors are used to increase the input common mode voltage range of the op amp. Measured dc gain of the op amp is 65 dB. With a 9 pF load unity gain bandwidth is 230 kHz and phase margin is 62/spl deg/. Input referred noise is 0.5 /spl mu/V//spl radic/(Hz) at 10 Hz and 0.15 /spl mu/V/(Hz) at 10 kHz. Current consumption of the op amp is 4.3 /spl mu/A and active area is 0.11 mm/sup 2/.
{"title":"A 1.2 V micropower CMOS op amp with floating-gate input transistors","authors":"E. Raisanen-Ruotsalainen, K. Lasanen, J. Kostamovaara","doi":"10.1109/MWSCAS.2000.952875","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952875","url":null,"abstract":"A micropower 1.2 V op amp has been integrated in a 0.35 /spl mu/m CMOS process. Floating-gate input transistors are used to increase the input common mode voltage range of the op amp. Measured dc gain of the op amp is 65 dB. With a 9 pF load unity gain bandwidth is 230 kHz and phase margin is 62/spl deg/. Input referred noise is 0.5 /spl mu/V//spl radic/(Hz) at 10 Hz and 0.15 /spl mu/V/(Hz) at 10 kHz. Current consumption of the op amp is 4.3 /spl mu/A and active area is 0.11 mm/sup 2/.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126151786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951595
H. Chiueh, J. Choma, J. Draper
A Temperature Monitoring Interface Circuit for PowerPC systems has been designed, implemented, and tested. This design yields a suitable balance of hardware and software components in the Integrated Thermal Management (ITEM) System. Powerview and Lager tools were used to design this chip in one man-month. This circuit was fabricated in an HP 0.5 /spl mu/m single-poly 3-metal process through MOSIS. Laboratory testing agreed with simulation results in verifying the functionality and performance of this circuit to 50 MHz, which is the targeted system speed of the ITEM multi-node computer system.
{"title":"Implementation of a Temperature Monitoring Interface Circuit for PowerPC systems","authors":"H. Chiueh, J. Choma, J. Draper","doi":"10.1109/MWSCAS.2000.951595","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951595","url":null,"abstract":"A Temperature Monitoring Interface Circuit for PowerPC systems has been designed, implemented, and tested. This design yields a suitable balance of hardware and software components in the Integrated Thermal Management (ITEM) System. Powerview and Lager tools were used to design this chip in one man-month. This circuit was fabricated in an HP 0.5 /spl mu/m single-poly 3-metal process through MOSIS. Laboratory testing agreed with simulation results in verifying the functionality and performance of this circuit to 50 MHz, which is the targeted system speed of the ITEM multi-node computer system.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126820166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951396
A. Low, P. Hasler
This paper presents an overview of series voltage regulators, beginning with single-transistor designs and exploring the various design issues and concepts. The regulating characteristics of nFET and pFET single-transistor regulators are compared analytically and experimentally to determine an optimal starting topology. The design of these simple regulators is taken a step further by applying floating-gate techniques to improve the flexibility of the existing design and the ability to customize the regulator bias points.
{"title":"Basics of floating-gate low-dropout voltage regulators","authors":"A. Low, P. Hasler","doi":"10.1109/MWSCAS.2000.951396","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951396","url":null,"abstract":"This paper presents an overview of series voltage regulators, beginning with single-transistor designs and exploring the various design issues and concepts. The regulating characteristics of nFET and pFET single-transistor regulators are compared analytically and experimentally to determine an optimal starting topology. The design of these simple regulators is taken a step further by applying floating-gate techniques to improve the flexibility of the existing design and the ability to customize the regulator bias points.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127705214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951592
Shaoyi Wang, C. Zukowski
Selective precharge is a low-power circuit technique that can significantly reduce the average energy use in large fan-in logic arrays. In this paper, we investigate application of this technique to two specific real examples; a content addressable memory (CAM) used in a routing table and a programmable logic array (PLA) used for table-lookup function evaluation. We show that significant energy savings is possible, and we discuss the impact of various array characteristics.
{"title":"Energy reduction from using selective precharge in two different logic arrays","authors":"Shaoyi Wang, C. Zukowski","doi":"10.1109/MWSCAS.2000.951592","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951592","url":null,"abstract":"Selective precharge is a low-power circuit technique that can significantly reduce the average energy use in large fan-in logic arrays. In this paper, we investigate application of this technique to two specific real examples; a content addressable memory (CAM) used in a routing table and a programmable logic array (PLA) used for table-lookup function evaluation. We show that significant energy savings is possible, and we discuss the impact of various array characteristics.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129206943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951392
S. Ozcan, H. Kuntman, O. Cicekoglu
A new biquadratic universal filter configuration realizing second-order low-pass, band-pass, and high-pass filters using a single current conveyor is proposed. Using this configuration high-pass, low-pass and band-pass filters can be realized with little modifications. The circuit employs a second-generation current conveyor (CCII+), and only four passive components. Since the current conveyor is a high performance active element, the circuit proposed is suitable for wide band applications. The derived filters can be easily cascaded and use reduced number of passive components compared to previously reported counterparts. To illustrate the design possibilities provided by the introduced circuit, current mode multifunction filters are constructed and tested.
{"title":"A novel multi-input single-output filter with reduced number of passive elements using single current conveyor","authors":"S. Ozcan, H. Kuntman, O. Cicekoglu","doi":"10.1109/MWSCAS.2000.951392","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951392","url":null,"abstract":"A new biquadratic universal filter configuration realizing second-order low-pass, band-pass, and high-pass filters using a single current conveyor is proposed. Using this configuration high-pass, low-pass and band-pass filters can be realized with little modifications. The circuit employs a second-generation current conveyor (CCII+), and only four passive components. Since the current conveyor is a high performance active element, the circuit proposed is suitable for wide band applications. The derived filters can be easily cascaded and use reduced number of passive components compared to previously reported counterparts. To illustrate the design possibilities provided by the introduced circuit, current mode multifunction filters are constructed and tested.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"18 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131435269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951669
R. Bhagavathula, Pritish Chittoor, R. Pendse
Recent advances in VLSI technology have spurred a tremendous increase in the performance of processors. Due to the slower main memory, there exists a bottleneck in the performance of computer systems. Caching is an effective way to reduce these bottlenecks. With increasing cache sizes, the performance of the processor could be enhanced by using advanced block replacement algorithms like LRU etc. However, due to the presence of the cache in the critical timing path, many processors do not employ these advanced replacement policies. In this paper, the authors present an alternative implementation of block replacement algorithms in CPU caches by modifying the processor pipeline to hide the latency involved in the replacement scheme.
{"title":"Pipeline LRU block replacement algorithm","authors":"R. Bhagavathula, Pritish Chittoor, R. Pendse","doi":"10.1109/MWSCAS.2000.951669","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951669","url":null,"abstract":"Recent advances in VLSI technology have spurred a tremendous increase in the performance of processors. Due to the slower main memory, there exists a bottleneck in the performance of computer systems. Caching is an effective way to reduce these bottlenecks. With increasing cache sizes, the performance of the processor could be enhanced by using advanced block replacement algorithms like LRU etc. However, due to the presence of the cache in the critical timing path, many processors do not employ these advanced replacement policies. In this paper, the authors present an alternative implementation of block replacement algorithms in CPU caches by modifying the processor pipeline to hide the latency involved in the replacement scheme.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132883776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.952915
S. Pallipatti, K. Ramabadran, S. Ayathu
Timing closure flow for digital designs is referred to as links-to-layout (LTL) flow. The bottlenecks with this flow leads to non-optimal designs. Timing closure becomes totally unpredictable for complex designs and leads to significant increase in overall cost, in terms of die-area and time-to-market. Commercial tools to solve this problem are not yet fully proven and are also very expensive. An optimized LTL flow that addresses the timing and area problems was defined, implemented and verified. Significant improvements in design cycle time (60%-70%) coupled with excellent area gains (7-10%) were obtained using the optimized LTL flow.
{"title":"An optimized links-to-layout flow for timing critical designs","authors":"S. Pallipatti, K. Ramabadran, S. Ayathu","doi":"10.1109/MWSCAS.2000.952915","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952915","url":null,"abstract":"Timing closure flow for digital designs is referred to as links-to-layout (LTL) flow. The bottlenecks with this flow leads to non-optimal designs. Timing closure becomes totally unpredictable for complex designs and leads to significant increase in overall cost, in terms of die-area and time-to-market. Commercial tools to solve this problem are not yet fully proven and are also very expensive. An optimized LTL flow that addresses the timing and area problems was defined, implemented and verified. Significant improvements in design cycle time (60%-70%) coupled with excellent area gains (7-10%) were obtained using the optimized LTL flow.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"2 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114011922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951461
K. Suzuki, A. Nishio, A. Kamo, T. Watanabe, H. Asai
This paper describes an application of the Verilog-A, which is a hardware description language for analog applications, to the modeling of neural networks. We attempt to simulate neural networks having a learning algorithm, which has not been designed with electronic circuits. The learning algorithm is modeled with Verilog-A and the suitable synaptic weights are solved by Verilog-A simulation.
{"title":"An application of Verilog-A to modeling of back propagation algorithm in neural networks","authors":"K. Suzuki, A. Nishio, A. Kamo, T. Watanabe, H. Asai","doi":"10.1109/MWSCAS.2000.951461","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951461","url":null,"abstract":"This paper describes an application of the Verilog-A, which is a hardware description language for analog applications, to the modeling of neural networks. We attempt to simulate neural networks having a learning algorithm, which has not been designed with electronic circuits. The learning algorithm is modeled with Verilog-A and the suitable synaptic weights are solved by Verilog-A simulation.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"87 3-4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114034616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.952901
Jing Wang, E. Sánchez-Sinencio, F. Maloberti
Two very linear ramp-generator designs are presented. The circuits are to be used in high-resolution ADC built-in-self-test (BIST) and on-chip calibration. The first design is used to charge a capacitor by a small current, which is linear enough to test 14-bit ADCs. The second design is in a relaxation oscillator architecture. It is linear enough to test up to 12-bit ADCs. The two designs have been fabricated in CMOS 2 /spl mu/m and 1.2 /spl mu/m processes separately.
{"title":"Very linear ramp-generators for high resolution ADC BIST and calibration","authors":"Jing Wang, E. Sánchez-Sinencio, F. Maloberti","doi":"10.1109/MWSCAS.2000.952901","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952901","url":null,"abstract":"Two very linear ramp-generator designs are presented. The circuits are to be used in high-resolution ADC built-in-self-test (BIST) and on-chip calibration. The first design is used to charge a capacitor by a small current, which is linear enough to test 14-bit ADCs. The second design is in a relaxation oscillator architecture. It is linear enough to test up to 12-bit ADCs. The two designs have been fabricated in CMOS 2 /spl mu/m and 1.2 /spl mu/m processes separately.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124495893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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