Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058890
Kwang-Seong Choi, Y. Eom, Seok-Hwan Moon, Jiho Joo, Kwangjoo Lee, Jung Hak Kim, Ju Hyeon Kim
Laser-Assisted Bonding with Compression (LABC) technology with NCF was proposed to accomplish the productivity and process reliability at the same time. A quartz block as a header was used to deliver a pressure to the devices because of its extremely low absorption of the laser during the bonding process. Newly developed NCF for LABC was designed to have stability on a hot stage and to show solder wetting and fast curing with no void and optimal fillet during the LABC bonding process. As the laser is used as a heat source, the uniform heat should be provided on each interconnection without any damages on chip or a substrate. 780μ-thick daisy chain top and bottom chips with the minimum pitch of 30^m and bump number of about 27,000 were successfully bonded using the LABC and NCF film.
{"title":"Development of Laser-Assisted Bonding with Compression (LABC) Process for 3D IC Integration","authors":"Kwang-Seong Choi, Y. Eom, Seok-Hwan Moon, Jiho Joo, Kwangjoo Lee, Jung Hak Kim, Ju Hyeon Kim","doi":"10.1109/3DIC48104.2019.9058890","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058890","url":null,"abstract":"Laser-Assisted Bonding with Compression (LABC) technology with NCF was proposed to accomplish the productivity and process reliability at the same time. A quartz block as a header was used to deliver a pressure to the devices because of its extremely low absorption of the laser during the bonding process. Newly developed NCF for LABC was designed to have stability on a hot stage and to show solder wetting and fast curing with no void and optimal fillet during the LABC bonding process. As the laser is used as a heat source, the uniform heat should be provided on each interconnection without any damages on chip or a substrate. 780μ-thick daisy chain top and bottom chips with the minimum pitch of 30^m and bump number of about 27,000 were successfully bonded using the LABC and NCF film.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122399577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058903
Alit Apriyana Anak Agung, P. Zhao, C. S. Tan
This paper presents the design of TiN guard ring structure that is built around the through silicon via (TSV) to improve the signal integrity (SI) performance of parallel networking lines by suppressing the crosstalk from adjacent TSV. The guard ring enhances the insertion loss by up to 1.6 dB and the crosstalk isolation by 20-26 dB across a range of 0-40 GHz. The attainable data rate is higher than 50 Gbps under 50 Ohm load and higher than 10 Gbps under 1 pF capacitive loading. The obtained signal-to-noise ratio (SNR) is greater than 15.
{"title":"TiN Guard Ring Around TSV for Cross-Talk Suppression of Parallel Networking of Data Center","authors":"Alit Apriyana Anak Agung, P. Zhao, C. S. Tan","doi":"10.1109/3DIC48104.2019.9058903","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058903","url":null,"abstract":"This paper presents the design of TiN guard ring structure that is built around the through silicon via (TSV) to improve the signal integrity (SI) performance of parallel networking lines by suppressing the crosstalk from adjacent TSV. The guard ring enhances the insertion loss by up to 1.6 dB and the crosstalk isolation by 20-26 dB across a range of 0-40 GHz. The attainable data rate is higher than 50 Gbps under 50 Ohm load and higher than 10 Gbps under 1 pF capacitive loading. The obtained signal-to-noise ratio (SNR) is greater than 15.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131352346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058844
M. Nomura
Heat transfer in Si nanostructure is not only an interesting topic in fundamental physics, but also an important practical study for efficient heat dissipation in electronic devices. In this paper, we discuss characteristic thermal phonon transport property in nanostructured Si membranes, where the dimension is smaller than phonon mean free path. We mainly focus on heat flux control technique in Si membranes using ballisticity and wave nature of phonons, which may be useful for deeper understanding of thermal dissipation in electronic devices with nanostructures.
{"title":"Heat Transfer in Nanostructured Si and Heat Flux Control Technique","authors":"M. Nomura","doi":"10.1109/3DIC48104.2019.9058844","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058844","url":null,"abstract":"Heat transfer in Si nanostructure is not only an interesting topic in fundamental physics, but also an important practical study for efficient heat dissipation in electronic devices. In this paper, we discuss characteristic thermal phonon transport property in nanostructured Si membranes, where the dimension is smaller than phonon mean free path. We mainly focus on heat flux control technique in Si membranes using ballisticity and wave nature of phonons, which may be useful for deeper understanding of thermal dissipation in electronic devices with nanostructures.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129902348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this research, Au is proposed as a new passivation material for Cu-Cu direct bonding. According to the TEM result, Cu could diffuse through the Au passivation layer to the bonding interface during the thermocompression bonding (TCB) process. In addition, the Au passivation layer can lower the bonding temperature (150 °C) and improve electrical properties, comparing to the conventional Cu-Cu bonding. Furthermore, the electrical measurement results after reliability tests show that the Au passivation method is a reliable way to reduce the bonding temperature of Cu-Cu direct bonding.
{"title":"Low Temperature Cu to Cu Direct Bonding below 150 °C with Au Passivation Layer","authors":"Demin Liu, Po-Chih Chen, Yi-Chieh Tsai, Kuan-Neng Chen","doi":"10.1109/3DIC48104.2019.9058873","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058873","url":null,"abstract":"In this research, Au is proposed as a new passivation material for Cu-Cu direct bonding. According to the TEM result, Cu could diffuse through the Au passivation layer to the bonding interface during the thermocompression bonding (TCB) process. In addition, the Au passivation layer can lower the bonding temperature (150 °C) and improve electrical properties, comparing to the conventional Cu-Cu bonding. Furthermore, the electrical measurement results after reliability tests show that the Au passivation method is a reliable way to reduce the bonding temperature of Cu-Cu direct bonding.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130378591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058858
Chuei-Tang Wang, Douglas Yu
Novel InFO technologies have been developed to meet high bandwidth, low power consumption and small form factor requirements for system integration with key characteristics of thin dielectric layers, fine RDL lines, 3D vertical interconnects and multi-chip integration. The powerperformance advantages of the technology from the characteristics on power integrity (PI), signal integrity (SI) and RF are studied and compared to those of organic substrate technology. For PI, the InFO with IPD (Integrated Passive Device) has 56% lower of system power delivery networking (PDN) impedance and 25% lower of the 1st voltage droop. For SI, the effect of line width on data rate and line density is studied and a record high 10 Tbps/mm of bandwidth density is obtained by the submicron RDL on InFO. For RF system integration, a 3D solenoid inductor on InFO package is demonstrated. The 3D inductor with 3 turns achieves Q-factor (quality factor) of 59 at 3GHz and the simulation and measurement results are consistent. The power-performance study indicates the InFO is a wide-spectrum application technology.
{"title":"Power-Performance Advantages of InFO Technology for Advanced System Integration","authors":"Chuei-Tang Wang, Douglas Yu","doi":"10.1109/3DIC48104.2019.9058858","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058858","url":null,"abstract":"Novel InFO technologies have been developed to meet high bandwidth, low power consumption and small form factor requirements for system integration with key characteristics of thin dielectric layers, fine RDL lines, 3D vertical interconnects and multi-chip integration. The powerperformance advantages of the technology from the characteristics on power integrity (PI), signal integrity (SI) and RF are studied and compared to those of organic substrate technology. For PI, the InFO with IPD (Integrated Passive Device) has 56% lower of system power delivery networking (PDN) impedance and 25% lower of the 1st voltage droop. For SI, the effect of line width on data rate and line density is studied and a record high 10 Tbps/mm of bandwidth density is obtained by the submicron RDL on InFO. For RF system integration, a 3D solenoid inductor on InFO package is demonstrated. The 3D inductor with 3 turns achieves Q-factor (quality factor) of 59 at 3GHz and the simulation and measurement results are consistent. The power-performance study indicates the InFO is a wide-spectrum application technology.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127753358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3dic48104.2019.9058843
Rui Liang, Sungho Lee, Y. Miwa, Kousei Kumahara, M. Murugesan, H. Kino, T. Fukushima, Tetsu Tanaka
Through-silicon vias (TSVs) is one of the key technologies for 3D integration. To solve the issues induced by the high-temperature process for TSV liner formation in the multichip-to-wafer (MCtW) process, we applied the low-temperature SiO2 deposition method called OER (Ozone-Ethylene Radical generation)-TEOS-CVD®. In this study, we fabricated the MIS capacitors with the TSV liner deposited by OER-TEOS-CVD® at 150°C and room temperature (RT), and compared both the coverage and electrical characteristics with that formed by conventional plasma-enhanced chemical vapor deposition (PE-CVD) at 200°C. Furthermore, we analyzed these SiO2liners by FTIR and synchrotron XPS. These results showed that the OER-TEOS-CVD® has high potentials to realize highly-reliable TSVs and to apply to various processes in 3D integration.
{"title":"Impacts of Deposition Temperature and Annealing Condition on Ozone-Ethylene Radical Generation-TEOS-CVD SiO2 for Low-Temperature TSV Liner Formation","authors":"Rui Liang, Sungho Lee, Y. Miwa, Kousei Kumahara, M. Murugesan, H. Kino, T. Fukushima, Tetsu Tanaka","doi":"10.1109/3dic48104.2019.9058843","DOIUrl":"https://doi.org/10.1109/3dic48104.2019.9058843","url":null,"abstract":"Through-silicon vias (TSVs) is one of the key technologies for 3D integration. To solve the issues induced by the high-temperature process for TSV liner formation in the multichip-to-wafer (MCtW) process, we applied the low-temperature SiO2 deposition method called OER (Ozone-Ethylene Radical generation)-TEOS-CVD®. In this study, we fabricated the MIS capacitors with the TSV liner deposited by OER-TEOS-CVD® at 150°C and room temperature (RT), and compared both the coverage and electrical characteristics with that formed by conventional plasma-enhanced chemical vapor deposition (PE-CVD) at 200°C. Furthermore, we analyzed these SiO2liners by FTIR and synchrotron XPS. These results showed that the OER-TEOS-CVD® has high potentials to realize highly-reliable TSVs and to apply to various processes in 3D integration.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134220863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058900
K. Sakui, T. Ohba
This paper proposes a fundamental architecture for the High Bandwidth Memory (HBM) with the bumpless TSV for the Wafer-on-Wafer (WOW) technology. The bumpless interconnects technology can increase the number of TSVs per chip with fine pitch of TSVs, and reduce the impedance of the TSV interconnects with no bumps. Therefore, a further higher speed and higher density HBM can be realized. Also, the High Bandwidth NAND (HBN), which can read and program by plane instead of by line by using the bumpless TSV, has been proposed.
{"title":"High Bandwidth Memory (HBM) and High Bandwidth NAND (HBN) with the Bumpless TSV Technology","authors":"K. Sakui, T. Ohba","doi":"10.1109/3DIC48104.2019.9058900","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058900","url":null,"abstract":"This paper proposes a fundamental architecture for the High Bandwidth Memory (HBM) with the bumpless TSV for the Wafer-on-Wafer (WOW) technology. The bumpless interconnects technology can increase the number of TSVs per chip with fine pitch of TSVs, and reduce the impedance of the TSV interconnects with no bumps. Therefore, a further higher speed and higher density HBM can be realized. Also, the High Bandwidth NAND (HBN), which can read and program by plane instead of by line by using the bumpless TSV, has been proposed.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133838362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058784
T. R. Harris, W. R. Davis, S. Lipa, W. S. Pitts, P. Franzon
This paper presents thermal measurement data of GaN HEMT on CMOS heterogeneous integration (HI) using a Diverse Accessible Heterogeneous Integration (DAHI) process. Thermal T3ster measurements, a product and service available from Mentor are presented. The method uses thermal transients to characterize the vertical thermal path stack including the package. Here the thermal dominance of the thermal interface at the die attachment is apparent. The T3ster measurements are contrasted with in-channel micro-Raman thermal measurements along with simulated results.
{"title":"Vertical Stack Thermal Characterization of Heterogeneous Integration and Packages","authors":"T. R. Harris, W. R. Davis, S. Lipa, W. S. Pitts, P. Franzon","doi":"10.1109/3DIC48104.2019.9058784","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058784","url":null,"abstract":"This paper presents thermal measurement data of GaN HEMT on CMOS heterogeneous integration (HI) using a Diverse Accessible Heterogeneous Integration (DAHI) process. Thermal T3ster measurements, a product and service available from Mentor are presented. The method uses thermal transients to characterize the vertical thermal path stack including the package. Here the thermal dominance of the thermal interface at the die attachment is apparent. The T3ster measurements are contrasted with in-channel micro-Raman thermal measurements along with simulated results.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117274566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058832
T. Miura, M. Sakakibara, H. Takahashi, T. Taura, K. Tatani, Y. Oike, T. Ezaki
In this paper, we propose a 3D stacked global shutter CMOS image sensor with 3M Cu-Cu connections. Using a fine pitch and a large number of Cu-Cu connection technology, we achieved 1.46M pixels of size 6.9 μm × 6.9 μm. The pixel evaluation results reveal that all the 3M Cu-Cu connections were realized without defect.
{"title":"A 6.9 μm Pixel-Pitch 3D Stacked Global Shutter CMOS Image Sensor with 3M Cu-Cu connections","authors":"T. Miura, M. Sakakibara, H. Takahashi, T. Taura, K. Tatani, Y. Oike, T. Ezaki","doi":"10.1109/3DIC48104.2019.9058832","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058832","url":null,"abstract":"In this paper, we propose a 3D stacked global shutter CMOS image sensor with 3M Cu-Cu connections. Using a fine pitch and a large number of Cu-Cu connection technology, we achieved 1.46M pixels of size 6.9 μm × 6.9 μm. The pixel evaluation results reveal that all the 3M Cu-Cu connections were realized without defect.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131026198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058846
Q. Dinh, K. Kondo, T. Hirato
The mismatch in thermal expansion coefficient (TEC) between copper and silicon causes serious problems in three-dimensional (3D) packaging. The common problem is TSV pumping when TSV is exposed to high temperature (400oC-600oC) during the wiring process. The copper pumping destroys wiring above TSV and leads to the failure of electronic devices. Other problem is the area on silicon around the TSV where the transistors cannot be formed due to stress caused by copper when annealing. With our low TEC additive (additive A), copper pumping height in 5× 20 μm p-TEOS TSV was reduced to 0.5 μm from 2.0 μm in case of conventional copper. We also investigated the effect of polyimide which is used as liner layer in the TSV on copper pumping reduction. The first screening result showed that the pumping height of conventional copper in polyimide TSV was only 0.8 μm., compared to 2.0 μm p-TEOS TSV and 1.2 μm O3-TEOS TSV.
{"title":"Reduction of TSV Pumping","authors":"Q. Dinh, K. Kondo, T. Hirato","doi":"10.1109/3DIC48104.2019.9058846","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058846","url":null,"abstract":"The mismatch in thermal expansion coefficient (TEC) between copper and silicon causes serious problems in three-dimensional (3D) packaging. The common problem is TSV pumping when TSV is exposed to high temperature (400oC-600oC) during the wiring process. The copper pumping destroys wiring above TSV and leads to the failure of electronic devices. Other problem is the area on silicon around the TSV where the transistors cannot be formed due to stress caused by copper when annealing. With our low TEC additive (additive A), copper pumping height in 5× 20 μm p-TEOS TSV was reduced to 0.5 μm from 2.0 μm in case of conventional copper. We also investigated the effect of polyimide which is used as liner layer in the TSV on copper pumping reduction. The first screening result showed that the pumping height of conventional copper in polyimide TSV was only 0.8 μm., compared to 2.0 μm p-TEOS TSV and 1.2 μm O3-TEOS TSV.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114802526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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