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2019 International 3D Systems Integration Conference (3DIC)最新文献

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Program Schedule - October 8, 2019 (Hotel Metropolitan Sendai) 活动时间表- 2019年10月8日(仙台大都会酒店)
Pub Date : 2019-10-01 DOI: 10.1109/3DIC48104.2019.9058792
Program Schedule - October 8, 2019 (Hotel Metropolitan Sendai)
活动时间表- 2019年10月8日(仙台大都会酒店)
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引用次数: 0
Collective and Gang Bonding for Three-Dimensional Integrated Circuits in Chip-on-Wafer Process 片上三维集成电路的集体键合和群键合
Pub Date : 2019-10-01 DOI: 10.1109/3DIC48104.2019.9058909
Hiroto Tanaka, Y. Arai, Toshiyuki Jinda, N. Asahi, K. Terada
We report on a thermal compression postbonder (PB3000W) that can simultaneously bond 2-6 cubes and an eight-layer stacked integrated circuit on a wafer in a two-step bonding process. This bonder can perform both collective bonding and gang bonding. The throughput can be remarkably improved because multiple layers of chips can be pre-bonded using a pre-applied non-conductive film adhesive activated simultaneously for multiple chip layers with thermal pressure. Therefore, this bonder has a high throughput of over 7000 UPH. To perform both collective and gang bonding, this bonder is equipped with a new structure head for gang bonding, a backup stage with a pulse heater, and support stages as a heat sink and wafer holder.
我们报道了一种热压缩后键合器(PB3000W),它可以在两步键合过程中同时在晶圆上键合2-6个立方体和8层堆叠集成电路。这种粘合器既可以进行集体粘合,也可以进行团伙粘合。由于多层芯片可以使用热压同时激活的预涂非导电薄膜粘合剂进行预粘接,因此吞吐量可以显著提高。因此,该粘合剂具有超过7000 UPH的高吞吐量。为了进行集体键合和组键合,该键合机配备了一个用于组键合的新结构头,一个带脉冲加热器的备用级,以及作为散热器和晶圆支架的支持级。
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引用次数: 0
3D Integration Technologies for the Stacked CMOS Image Sensors 堆叠式CMOS图像传感器的3D集成技术
Pub Date : 2019-10-01 DOI: 10.1109/3DIC48104.2019.9058895
Y. Kagawa, H. Iwamoto
In this paper our 3D chip stacking technologies for CMOS image sensors (CISs) are introduced. We have developed wafer-to-wafer bonding technology for back-illuminated CIS (BICIS) and have developed Through-Silicon-Via (TSV) technology and Cu-Cu direct bonding technology for stacked BI-CIS. Our 3D chip stacking technologies have successfully realized the multifunctional, high-performance and highly productive CIS devices. Such innovative technologies are expected to evolve not only the CIS devices but also the general 3D stacked semiconductor devices.
本文介绍了CMOS图像传感器(CISs)的三维芯片堆叠技术。我们已经开发了用于背光CIS (BICIS)的晶圆间键合技术,并开发了用于堆叠BI-CIS的through silicon - via (TSV)技术和Cu-Cu直接键合技术。我们的3D芯片堆叠技术成功地实现了多功能、高性能和高生产率的CIS器件。预计这些创新技术不仅会发展CIS器件,还会发展一般的3D堆叠半导体器件。
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引用次数: 7
SiN used as a Stressor in Germanium-On-Insulator Substrate 用作绝缘体上锗衬底的应力源
Pub Date : 2019-10-01 DOI: 10.1109/3DIC48104.2019.9058896
S. Duangchan, K. Yamamoto, Dong Wang, H. Nakashima, A. Baba
This research aims to show the advantage of using silicon nitride as a stressor in a strained germanium-on-insulator substrate (strained Ge). A Si substrate is patterned on the surface before bonding for controlling the shape and the position of strained Ge. The SiN film is deposited on Ge substrate by PE-CVD with 150 nm thick approximately. Two substrates are bonded together by surface-activation bonding with 200°C post-anneal. It was found that the tensile strain of 1.16% for the flat part and 2.03% for the bucking part, which is higher than other reported GOI using SiO2 layer.
本研究旨在展示在应变锗衬底(应变锗)中使用氮化硅作为应力源的优势。为了控制应变Ge的形状和位置,在键合前在表面上图案化Si衬底。采用PE-CVD方法在Ge衬底上沉积了厚度约为150nm的SiN薄膜。两个衬底通过200°C退火后的表面活化键合在一起。结果表明,采用SiO2材料制备的GOI,扁平部分的拉伸应变为1.16%,屈曲部分的拉伸应变为2.03%,高于已有报道的GOI。
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引用次数: 0
Program-at-a-Glance Program-at-a-Glance
Pub Date : 1997-08-01 DOI: 10.1109/aiccsa.2018.8612777
T. Baukrowitz, P. Kovermann, Jacqueline Heger, Martina Krüger, Markus Bleich, K. Kusche-Vihrog, Alexander Schwoerer
Program-at-a-Glance
Program-at-a-Glance
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引用次数: 0
期刊
2019 International 3D Systems Integration Conference (3DIC)
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