Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058792
Program Schedule - October 8, 2019 (Hotel Metropolitan Sendai)
活动时间表- 2019年10月8日(仙台大都会酒店)
{"title":"Program Schedule - October 8, 2019 (Hotel Metropolitan Sendai)","authors":"","doi":"10.1109/3DIC48104.2019.9058792","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058792","url":null,"abstract":"Program Schedule - October 8, 2019 (Hotel Metropolitan Sendai)","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"105 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120905959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058909
Hiroto Tanaka, Y. Arai, Toshiyuki Jinda, N. Asahi, K. Terada
We report on a thermal compression postbonder (PB3000W) that can simultaneously bond 2-6 cubes and an eight-layer stacked integrated circuit on a wafer in a two-step bonding process. This bonder can perform both collective bonding and gang bonding. The throughput can be remarkably improved because multiple layers of chips can be pre-bonded using a pre-applied non-conductive film adhesive activated simultaneously for multiple chip layers with thermal pressure. Therefore, this bonder has a high throughput of over 7000 UPH. To perform both collective and gang bonding, this bonder is equipped with a new structure head for gang bonding, a backup stage with a pulse heater, and support stages as a heat sink and wafer holder.
{"title":"Collective and Gang Bonding for Three-Dimensional Integrated Circuits in Chip-on-Wafer Process","authors":"Hiroto Tanaka, Y. Arai, Toshiyuki Jinda, N. Asahi, K. Terada","doi":"10.1109/3DIC48104.2019.9058909","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058909","url":null,"abstract":"We report on a thermal compression postbonder (PB3000W) that can simultaneously bond 2-6 cubes and an eight-layer stacked integrated circuit on a wafer in a two-step bonding process. This bonder can perform both collective bonding and gang bonding. The throughput can be remarkably improved because multiple layers of chips can be pre-bonded using a pre-applied non-conductive film adhesive activated simultaneously for multiple chip layers with thermal pressure. Therefore, this bonder has a high throughput of over 7000 UPH. To perform both collective and gang bonding, this bonder is equipped with a new structure head for gang bonding, a backup stage with a pulse heater, and support stages as a heat sink and wafer holder.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121282360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058895
Y. Kagawa, H. Iwamoto
In this paper our 3D chip stacking technologies for CMOS image sensors (CISs) are introduced. We have developed wafer-to-wafer bonding technology for back-illuminated CIS (BICIS) and have developed Through-Silicon-Via (TSV) technology and Cu-Cu direct bonding technology for stacked BI-CIS. Our 3D chip stacking technologies have successfully realized the multifunctional, high-performance and highly productive CIS devices. Such innovative technologies are expected to evolve not only the CIS devices but also the general 3D stacked semiconductor devices.
本文介绍了CMOS图像传感器(CISs)的三维芯片堆叠技术。我们已经开发了用于背光CIS (BICIS)的晶圆间键合技术,并开发了用于堆叠BI-CIS的through silicon - via (TSV)技术和Cu-Cu直接键合技术。我们的3D芯片堆叠技术成功地实现了多功能、高性能和高生产率的CIS器件。预计这些创新技术不仅会发展CIS器件,还会发展一般的3D堆叠半导体器件。
{"title":"3D Integration Technologies for the Stacked CMOS Image Sensors","authors":"Y. Kagawa, H. Iwamoto","doi":"10.1109/3DIC48104.2019.9058895","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058895","url":null,"abstract":"In this paper our 3D chip stacking technologies for CMOS image sensors (CISs) are introduced. We have developed wafer-to-wafer bonding technology for back-illuminated CIS (BICIS) and have developed Through-Silicon-Via (TSV) technology and Cu-Cu direct bonding technology for stacked BI-CIS. Our 3D chip stacking technologies have successfully realized the multifunctional, high-performance and highly productive CIS devices. Such innovative technologies are expected to evolve not only the CIS devices but also the general 3D stacked semiconductor devices.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"227 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122351585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058896
S. Duangchan, K. Yamamoto, Dong Wang, H. Nakashima, A. Baba
This research aims to show the advantage of using silicon nitride as a stressor in a strained germanium-on-insulator substrate (strained Ge). A Si substrate is patterned on the surface before bonding for controlling the shape and the position of strained Ge. The SiN film is deposited on Ge substrate by PE-CVD with 150 nm thick approximately. Two substrates are bonded together by surface-activation bonding with 200°C post-anneal. It was found that the tensile strain of 1.16% for the flat part and 2.03% for the bucking part, which is higher than other reported GOI using SiO2 layer.
{"title":"SiN used as a Stressor in Germanium-On-Insulator Substrate","authors":"S. Duangchan, K. Yamamoto, Dong Wang, H. Nakashima, A. Baba","doi":"10.1109/3DIC48104.2019.9058896","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058896","url":null,"abstract":"This research aims to show the advantage of using silicon nitride as a stressor in a strained germanium-on-insulator substrate (strained Ge). A Si substrate is patterned on the surface before bonding for controlling the shape and the position of strained Ge. The SiN film is deposited on Ge substrate by PE-CVD with 150 nm thick approximately. Two substrates are bonded together by surface-activation bonding with 200°C post-anneal. It was found that the tensile strain of 1.16% for the flat part and 2.03% for the bucking part, which is higher than other reported GOI using SiO2 layer.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127896808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-08-01DOI: 10.1109/aiccsa.2018.8612777
T. Baukrowitz, P. Kovermann, Jacqueline Heger, Martina Krüger, Markus Bleich, K. Kusche-Vihrog, Alexander Schwoerer
Program-at-a-Glance
Program-at-a-Glance
{"title":"Program-at-a-Glance","authors":"T. Baukrowitz, P. Kovermann, Jacqueline Heger, Martina Krüger, Markus Bleich, K. Kusche-Vihrog, Alexander Schwoerer","doi":"10.1109/aiccsa.2018.8612777","DOIUrl":"https://doi.org/10.1109/aiccsa.2018.8612777","url":null,"abstract":"Program-at-a-Glance","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132069087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}