Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058859
S. Gopal, D. Heo, T. Karnik
For the first time, this work systematically develops the complete serial link by using hierarchical modeling with serial link power and delay models. This paper presents a comprehensive design methodology and optimization using analytical expressions that analyzes the intrinsic energy and area trade-offs of an inductive coupling based high speed serial link. Further, we also demonstrate that equalization is a potential technique of breaking the intrinsic energy and area trade-offs of a TCI channel and reduces link power consumption and inductor area.
{"title":"Hierarchical Design Methodology and Optimization for Proximity Communication based Contactless 3D ThruChip Interface","authors":"S. Gopal, D. Heo, T. Karnik","doi":"10.1109/3DIC48104.2019.9058859","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058859","url":null,"abstract":"For the first time, this work systematically develops the complete serial link by using hierarchical modeling with serial link power and delay models. This paper presents a comprehensive design methodology and optimization using analytical expressions that analyzes the intrinsic energy and area trade-offs of an inductive coupling based high speed serial link. Further, we also demonstrate that equalization is a potential technique of breaking the intrinsic energy and area trade-offs of a TCI channel and reduces link power consumption and inductor area.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121115242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058848
Cheong-Ha Jung, Won Seo, Gu-sung Kim
3D packaging technology, which has advantages such as power consumption and delay reduction, high integration, high bandwidth, and reduced form factor compared to conventional 2D packaging, has been actively studied as promising technology in the semiconductor package field. However, there are many issues in 3D stacking package such as IMD crack, interface delamination, TSV void, liner / barrier damage of TSV, thin die crack, and solder consumption etc. And these issues degrade package reliability. Therefore, in this paper, we propose a method to analyze the reliability problem from the viewpoint of stress through the 3D stacking package simulation and to improve the reliability. In order to carry out the computer simulation, a 3D structure in which a multi die is stacked with four layers is modeled and a thermal cycling test according to the JEDEC22-A104 standard is simulated. Each layer was connected to the RDL layer of the upper layer through a microsolder and the TMV filled with copper through a via hole in the lower layer mold. And the stress occurs in the package according to the rapid temperature change of the thermal cycle. As a result, the maximum stress occurred in the microsolders located at the bottom layer, especially at the part contacting the TMVs. This is consistent with the tendency of cracks, which is a problem that is often observed in microsolder and TMV. In addition, maximum strain and minimum stress were generated in the uppermost EMC layer Because the heat load was directly expressed as deformation not accumulating the stress.
{"title":"Thermal Stress Tracking in Multi-Die 3D Stacking Structure by Finite Element Analysis","authors":"Cheong-Ha Jung, Won Seo, Gu-sung Kim","doi":"10.1109/3DIC48104.2019.9058848","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058848","url":null,"abstract":"3D packaging technology, which has advantages such as power consumption and delay reduction, high integration, high bandwidth, and reduced form factor compared to conventional 2D packaging, has been actively studied as promising technology in the semiconductor package field. However, there are many issues in 3D stacking package such as IMD crack, interface delamination, TSV void, liner / barrier damage of TSV, thin die crack, and solder consumption etc. And these issues degrade package reliability. Therefore, in this paper, we propose a method to analyze the reliability problem from the viewpoint of stress through the 3D stacking package simulation and to improve the reliability. In order to carry out the computer simulation, a 3D structure in which a multi die is stacked with four layers is modeled and a thermal cycling test according to the JEDEC22-A104 standard is simulated. Each layer was connected to the RDL layer of the upper layer through a microsolder and the TMV filled with copper through a via hole in the lower layer mold. And the stress occurs in the package according to the rapid temperature change of the thermal cycle. As a result, the maximum stress occurred in the microsolders located at the bottom layer, especially at the part contacting the TMVs. This is consistent with the tendency of cracks, which is a problem that is often observed in microsolder and TMV. In addition, maximum strain and minimum stress were generated in the uppermost EMC layer Because the heat load was directly expressed as deformation not accumulating the stress.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123220681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058880
Sungho Lee, Y. Susumago, Z. Qian, N. Takahashi, H. Kino, Tetsu Tanaka, T. Fukushima
We have fabricated a new 3D-IC embedded flexible hybrid system (FHS) based on a Fan-Out Wafer-Level Packaging (FOWLP). The unique FHS structure is consisting of PDMS as a flexible substrate in which the 3D-IC with through-Si vias (TSVs) and microbumps are embedded. The mechanical and electrical properties of the 3D-IC embedded FHS are characterized by using repeated bending test with the TSV/microbump daisy chains. The new FHS can be expected to be used as high-performance wearable device systems for biomedical applications.
{"title":"Development of 3D-IC Embedded Flexible Hybrid System","authors":"Sungho Lee, Y. Susumago, Z. Qian, N. Takahashi, H. Kino, Tetsu Tanaka, T. Fukushima","doi":"10.1109/3DIC48104.2019.9058880","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058880","url":null,"abstract":"We have fabricated a new 3D-IC embedded flexible hybrid system (FHS) based on a Fan-Out Wafer-Level Packaging (FOWLP). The unique FHS structure is consisting of PDMS as a flexible substrate in which the 3D-IC with through-Si vias (TSVs) and microbumps are embedded. The mechanical and electrical properties of the 3D-IC embedded FHS are characterized by using repeated bending test with the TSV/microbump daisy chains. The new FHS can be expected to be used as high-performance wearable device systems for biomedical applications.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116930670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058794
Fan-Hsuan Tang, Hsu-Yu Kao, Shih-Hsu Huang, Jin-Fu Li
Previous 3D test wrapper chain synthesis algorithms do not consider the binding of I/O cells (i.e., the association between scan chains and I/O cells). However, the binding of I/O cells may be specified as synthesis constraints. In this paper, we propose a 3D test wrapper chain optimization algorithm with I/O cells binding considered. Our objective is not only to reduce the required test time but also to reduce the number of test TSVs (through-silicon-vias) under I/O cells binding constraints. Our experiments show that the proposed algorithm greatly reduces both test time and test TSV count.
{"title":"3D Test Wrapper Chain Optimization with I/O Cells Binding Considered","authors":"Fan-Hsuan Tang, Hsu-Yu Kao, Shih-Hsu Huang, Jin-Fu Li","doi":"10.1109/3DIC48104.2019.9058794","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058794","url":null,"abstract":"Previous 3D test wrapper chain synthesis algorithms do not consider the binding of I/O cells (i.e., the association between scan chains and I/O cells). However, the binding of I/O cells may be specified as synthesis constraints. In this paper, we propose a 3D test wrapper chain optimization algorithm with I/O cells binding considered. Our objective is not only to reduce the required test time but also to reduce the number of test TSVs (through-silicon-vias) under I/O cells binding constraints. Our experiments show that the proposed algorithm greatly reduces both test time and test TSV count.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115786132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058774
H. Park, H. Seo, S. Kim
Copper nitride passivated surface has been characterized and optimized by the design of experiment (DOE) technique with the aim of low-temperature (300°C) Cu-Cu bonding. In order to generate an oxidation-free surface prior to Cu-Cu bonding process, N2 plasma treatment was performed on Cu surface followed by Cu surface activation and cleaning by Ar plasma in the same conventional DC sputter chamber. In this study, N2 plasma treatment conditions were optimized using the response surface methodology (RSM) based on central composite design (CCD) in DOE. The chemical states of nitride passivated Cu surface were analyzed by XPS profiles and then, several meaningful peak areas of each element were calculated by a deconvolution technique. These peak areas and surface roughness by AFM were used as the input values for the response optimization process. Cu-Cu bonded interface quality using optimized plasma conditions at low-temperature (300°C) has been significantly improved and it shows this research has great potential for Cu-Cu bonding in mass production.
{"title":"Characterization of Nitride Passivated Cu Surface for Low-Temperature Cu-Cu Bonding","authors":"H. Park, H. Seo, S. Kim","doi":"10.1109/3DIC48104.2019.9058774","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058774","url":null,"abstract":"Copper nitride passivated surface has been characterized and optimized by the design of experiment (DOE) technique with the aim of low-temperature (300°C) Cu-Cu bonding. In order to generate an oxidation-free surface prior to Cu-Cu bonding process, N2 plasma treatment was performed on Cu surface followed by Cu surface activation and cleaning by Ar plasma in the same conventional DC sputter chamber. In this study, N2 plasma treatment conditions were optimized using the response surface methodology (RSM) based on central composite design (CCD) in DOE. The chemical states of nitride passivated Cu surface were analyzed by XPS profiles and then, several meaningful peak areas of each element were calculated by a deconvolution technique. These peak areas and surface roughness by AFM were used as the input values for the response optimization process. Cu-Cu bonded interface quality using optimized plasma conditions at low-temperature (300°C) has been significantly improved and it shows this research has great potential for Cu-Cu bonding in mass production.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"287 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122088795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058787
W. Feng, N. Watanabe, H. Shimamoto, M. Aoyagi, K. Kikuchi
In order to reduce the thermal stress in the Si substrate, we proposed a novel Through Silicon Via (TSV) structure as annular-trench-isolated (ATI) TSV. The origin of thermal stress is the mismatch in the Coefficient of Thermal Expansion (CTE) of different materials. Therefore, the core material affects the thermal behavior of ATI TSV. In this paper, we continued the study by investigating the thermal stress of ATI TSV with different core materials as Cu and Solder. A numerical model of ATI TSV was established based on the fabricated samples with different core material. The thermal stress with different metal core materials was simulated and analyzed by varying the temperature from 25 °C to 125 °C and −55 °C. The simulation results showed a similar stress distribution for ATI TSVs with two core materials. And the thermal stress variation profiles near the device area were also analyzed. Although the ATI TSV with Solder core showed lower stress in the core area, and higher stress in the Si ring layer, the stress outside Si ring is at the same level for ATI TSV with two core materials. The Si ring with high Young's modulus and low CTE value blocked the effect of the different core material of ATI TSV on thermal stress inside the Si ring and maintained the stress in Si substrate at the same level.
{"title":"Thermal Stress Comparison of Annular-Trench-Isolated (ATI) TSV with Cu and Solder Core","authors":"W. Feng, N. Watanabe, H. Shimamoto, M. Aoyagi, K. Kikuchi","doi":"10.1109/3DIC48104.2019.9058787","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058787","url":null,"abstract":"In order to reduce the thermal stress in the Si substrate, we proposed a novel Through Silicon Via (TSV) structure as annular-trench-isolated (ATI) TSV. The origin of thermal stress is the mismatch in the Coefficient of Thermal Expansion (CTE) of different materials. Therefore, the core material affects the thermal behavior of ATI TSV. In this paper, we continued the study by investigating the thermal stress of ATI TSV with different core materials as Cu and Solder. A numerical model of ATI TSV was established based on the fabricated samples with different core material. The thermal stress with different metal core materials was simulated and analyzed by varying the temperature from 25 °C to 125 °C and −55 °C. The simulation results showed a similar stress distribution for ATI TSVs with two core materials. And the thermal stress variation profiles near the device area were also analyzed. Although the ATI TSV with Solder core showed lower stress in the core area, and higher stress in the Si ring layer, the stress outside Si ring is at the same level for ATI TSV with two core materials. The Si ring with high Young's modulus and low CTE value blocked the effect of the different core material of ATI TSV on thermal stress inside the Si ring and maintained the stress in Si substrate at the same level.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129562878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058850
M. Yamada, S. Ono, Y. Arai, I. Kurachi, T. Tsuboyama, M. Ikebe, M. Motoyoshi
The international linear collider (ILC) experiment requires a vertex detector which is characterized by low hit occupancy, low material budget, high-speed readout and high spatial resolution better than 3 /xm. A high functional signal readout circuit and multi-analog memories have been implemented in a 20 × 20 μm,2 pixel with our 3D integration technology, Au micro-cylinder bump bonding, to maintain the spatial resolution. The material budget is lower than the conventional hybrid pixel detector used for high energy accelerator physics experiment by integrating monolithic pixel sensors, which are processed by Silicon-on-Insulator (SOI) technology. A 3D-integrated chip consists of two SOI pixel chips. The upper and lower chips are connected by Au micro-cylinder bump bonding instead of the generally used through silicon via (TSV). Analog and digital signals from the lower pixel are sent to the upper pixel via 3 /xm-diameter bumps. We have successfully demonstrated images of /3-ray tracks of 90 Sr by our prototype chip, SOFIST4, with a bump connection yield of 99.9 %.
{"title":"3D Integrated Pixel Sensor with Silicon-on-Insulator Technology for the International Linear Collider Experiment","authors":"M. Yamada, S. Ono, Y. Arai, I. Kurachi, T. Tsuboyama, M. Ikebe, M. Motoyoshi","doi":"10.1109/3DIC48104.2019.9058850","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058850","url":null,"abstract":"The international linear collider (ILC) experiment requires a vertex detector which is characterized by low hit occupancy, low material budget, high-speed readout and high spatial resolution better than 3 /xm. A high functional signal readout circuit and multi-analog memories have been implemented in a 20 × 20 μm,2 pixel with our 3D integration technology, Au micro-cylinder bump bonding, to maintain the spatial resolution. The material budget is lower than the conventional hybrid pixel detector used for high energy accelerator physics experiment by integrating monolithic pixel sensors, which are processed by Silicon-on-Insulator (SOI) technology. A 3D-integrated chip consists of two SOI pixel chips. The upper and lower chips are connected by Au micro-cylinder bump bonding instead of the generally used through silicon via (TSV). Analog and digital signals from the lower pixel are sent to the upper pixel via 3 /xm-diameter bumps. We have successfully demonstrated images of /3-ray tracks of 90 Sr by our prototype chip, SOFIST4, with a bump connection yield of 99.9 %.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127792507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058783
E. Bourjot, P. Stewart, C. Dubarry, E. Lagoutte, E. Rolland, N. Bresson, G. Romano, D. Scevola, V. Balan, J. Dechamp, M. Zussy, G. Mauguen, C. Castan, L. Sanchez, A. Jouve, F. Fournel, S. Chéramy
Die-to-wafer stacking is very promising for the next 3DIC generation since it offers the ability to assemble several dies with small interconnection pitches. This paper proposes an overall integration scheme D2W HB process to reinforce its robustness and its economical relevance for microelectronics industry. Firstly, a KGD strategy was developed to be compatible with hybrid bonding. A successful D2W bonding was demonstrated with tested pads. Secondly, the development of the planarization of stacked dies is presented.
{"title":"Towards a Complete Direct Hybrid Bonding D2W Integration Flow: Known-Good-Dies and Die Planarization Modules Development","authors":"E. Bourjot, P. Stewart, C. Dubarry, E. Lagoutte, E. Rolland, N. Bresson, G. Romano, D. Scevola, V. Balan, J. Dechamp, M. Zussy, G. Mauguen, C. Castan, L. Sanchez, A. Jouve, F. Fournel, S. Chéramy","doi":"10.1109/3DIC48104.2019.9058783","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058783","url":null,"abstract":"Die-to-wafer stacking is very promising for the next 3DIC generation since it offers the ability to assemble several dies with small interconnection pitches. This paper proposes an overall integration scheme D2W HB process to reinforce its robustness and its economical relevance for microelectronics industry. Firstly, a KGD strategy was developed to be compatible with hybrid bonding. A successful D2W bonding was demonstrated with tested pads. Secondly, the development of the planarization of stacked dies is presented.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124149603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058854
V. Sukharev, A. Kteyan, J. Choy
Novel approach for assessment of the effect of temperature and chip-package interaction (CPI) induced stress on performance and reliability of ICs with 2.5D/3D architectures is presented. A developed physics-based model and a multiphysics EDA tool-prototype analyze thermal, and thermomechanical problems during package assembly and chip operation. The tool employs effective anisotropic thermalmechanical properties methodology that accurately represents non-uniformity within a die or a layer, and significantly boosts computational performance by avoiding complex geometries. An implemented link between layout analysis tools and the multiphysics thermal mechanical tool enables to perform reliability check within the design flow. The developed stress simulation flow takes into account multiscale stress variations from a package macro-scale to an interconnect segment and transistor nano-scale. The obtained across-chip temperature and stress fields are used for calculating the variations in transistors electrical characteristics, and for analysis of potential cracking locations in the interconnect layers.
{"title":"An Accurate Assessment of Chip-Package Interaction is a Key Factor for Designing Resilient 3D IC Systems","authors":"V. Sukharev, A. Kteyan, J. Choy","doi":"10.1109/3DIC48104.2019.9058854","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058854","url":null,"abstract":"Novel approach for assessment of the effect of temperature and chip-package interaction (CPI) induced stress on performance and reliability of ICs with 2.5D/3D architectures is presented. A developed physics-based model and a multiphysics EDA tool-prototype analyze thermal, and thermomechanical problems during package assembly and chip operation. The tool employs effective anisotropic thermalmechanical properties methodology that accurately represents non-uniformity within a die or a layer, and significantly boosts computational performance by avoiding complex geometries. An implemented link between layout analysis tools and the multiphysics thermal mechanical tool enables to perform reliability check within the design flow. The developed stress simulation flow takes into account multiscale stress variations from a package macro-scale to an interconnect segment and transistor nano-scale. The obtained across-chip temperature and stress fields are used for calculating the variations in transistors electrical characteristics, and for analysis of potential cracking locations in the interconnect layers.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116528840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058884
T. Hancock, J. Demmin
Booz Allen Hamilton.
博思艾伦汉密尔顿。
{"title":"Heterogeneous and 3D Integration at DARPA","authors":"T. Hancock, J. Demmin","doi":"10.1109/3DIC48104.2019.9058884","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058884","url":null,"abstract":"Booz Allen Hamilton.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129052367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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