Three-dimensional (3D) dynamic random access memory (DRAM) using through-silicon-via (TSV) has been proposed to overcome the memory wall. WideIO DRAM is one type of 3D DRAMs. IOs of a WideIO DRAM die are wrapped by a 1149. 1-like boundary scan controlled by a scan controller. In this paper, we propose a built-in-self-test (BIST) scheme for the post-bond testing of TSVs of a logic-DRAM stack. The BIST circuit implemented in the logic die can generate control signals for the scan controller and test patterns for the testing of TSVs.
{"title":"A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs","authors":"Wei-Hsuan Yang, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun, Shih-Hsu Huang","doi":"10.1109/3DIC48104.2019.9058898","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058898","url":null,"abstract":"Three-dimensional (3D) dynamic random access memory (DRAM) using through-silicon-via (TSV) has been proposed to overcome the memory wall. WideIO DRAM is one type of 3D DRAMs. IOs of a WideIO DRAM die are wrapped by a 1149. 1-like boundary scan controlled by a scan controller. In this paper, we propose a built-in-self-test (BIST) scheme for the post-bond testing of TSVs of a logic-DRAM stack. The BIST circuit implemented in the logic die can generate control signals for the scan controller and test patterns for the testing of TSVs.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121397871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058853
M. Murugesan, M. Koyanagi, T. Fukushima
A feasibility study for the continuous formation of multi-layer graphene (MLG) on both through-Si-via (TSV) top surface and all through the TSV sidewall and the bottom surface of high-aspect-ratio TSV by thermal chemical vapor deposition (CVD) technique has been carried out. Both microstructural and μ-Raman studies on cross-sectional graphene-TSV samples confirmed that the continuous formation of MLG all along the TSV side wall for the CVD growth temperatures of 650°C and above, and it may be used as thermal TSVs for heat removal in the stacked tiers of 3D-LSI/IC.
{"title":"Growth Optimization of Multi-Layer Graphene for Thermal-TSV Application in 3D-LSI","authors":"M. Murugesan, M. Koyanagi, T. Fukushima","doi":"10.1109/3DIC48104.2019.9058853","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058853","url":null,"abstract":"A feasibility study for the continuous formation of multi-layer graphene (MLG) on both through-Si-via (TSV) top surface and all through the TSV sidewall and the bottom surface of high-aspect-ratio TSV by thermal chemical vapor deposition (CVD) technique has been carried out. Both microstructural and μ-Raman studies on cross-sectional graphene-TSV samples confirmed that the continuous formation of MLG all along the TSV side wall for the CVD growth temperatures of 650°C and above, and it may be used as thermal TSVs for heat removal in the stacked tiers of 3D-LSI/IC.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114172950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058780
J. Tao, Hongyu Li, P. Zhao, Y. Lim, A. Apriyana, C. S. Tan
Surface electrode ion trap with through-silicon-via (TSV) integration enables 3D stacking of ion trap chip on an interposer to eliminate the wire-bonds on the surface electrodes and also addresses the challenge of the ever increasing complexity of surface electrode design with low-parasitic and high-density interconnect requirements. In this work, we demonstrate the design and fabrication of TSV integrated surface electrode ion trap on a 300-mm Si wafer platform. By designing the TSV arrays directly underneath the surface electrodes, the surface electrode foot print is reduced and the TSV traps show better RF performance compared to the planar traps with wire-bonding pads.
{"title":"Design Considerations and Fabrication Challenges of Surface Electrode Ion Trap with TSV Integration","authors":"J. Tao, Hongyu Li, P. Zhao, Y. Lim, A. Apriyana, C. S. Tan","doi":"10.1109/3DIC48104.2019.9058780","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058780","url":null,"abstract":"Surface electrode ion trap with through-silicon-via (TSV) integration enables 3D stacking of ion trap chip on an interposer to eliminate the wire-bonds on the surface electrodes and also addresses the challenge of the ever increasing complexity of surface electrode design with low-parasitic and high-density interconnect requirements. In this work, we demonstrate the design and fabrication of TSV integrated surface electrode ion trap on a 300-mm Si wafer platform. By designing the TSV arrays directly underneath the surface electrodes, the surface electrode foot print is reduced and the TSV traps show better RF performance compared to the planar traps with wire-bonding pads.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121683620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058789
H. Seo, H. Park, S. Kim
This study depicts the comparative research between sputtered and electroplated Cu surfaces using argon and nitrogen ion bombardments to form copper nitride passivation layers. The thin copper nitride layer is formed in order to prohibit Cu oxidation on copper surface and to lower bonding temperature in Cu-Cu thermo-compression bonding process. Argon ion bombardment was applied to activate and clean copper surface. Nitrogen ion bombardment was utilized to passivate the Cu surface after argon ion bombardment. The sputtered Cu surface tended to form Cu4N layer, while the electroplated Cu surface tended to form Cu3N layer. In comparison with electroplated Cu, the sputtered Cu had a lower roughness and a slightly higher sheet resistance. The bonding quality of the sputtered Cu samples was better than that of the electroplated samples. Further research should improve the roughness and copper nitride properties of the Cu surface.
{"title":"Effects of Argon and Nitrogen ion Bombardments on Sputtered and Electroplated Cu Surfaces for Cu Bonding Application","authors":"H. Seo, H. Park, S. Kim","doi":"10.1109/3DIC48104.2019.9058789","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058789","url":null,"abstract":"This study depicts the comparative research between sputtered and electroplated Cu surfaces using argon and nitrogen ion bombardments to form copper nitride passivation layers. The thin copper nitride layer is formed in order to prohibit Cu oxidation on copper surface and to lower bonding temperature in Cu-Cu thermo-compression bonding process. Argon ion bombardment was applied to activate and clean copper surface. Nitrogen ion bombardment was utilized to passivate the Cu surface after argon ion bombardment. The sputtered Cu surface tended to form Cu4N layer, while the electroplated Cu surface tended to form Cu3N layer. In comparison with electroplated Cu, the sputtered Cu had a lower roughness and a slightly higher sheet resistance. The bonding quality of the sputtered Cu samples was better than that of the electroplated samples. Further research should improve the roughness and copper nitride properties of the Cu surface.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131475116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058902
K. Hamaguchi, M. Nakata, Kouta Segawa, N. Suzuki, T. Nonaka
Warpage and solder joint reliability of 2.5D and fan-out packages were investigated using Finite Element Method comparing with the flip chip package. It revealed that the warpage could be reduced to about 50% and the solder joint reliability could be increased to 1.2 times. Regarding the FO package, using the higher elastic modulus underfill material was effective to improve the both of the warpage and the solder joint reliability. It also indicated that the optimization of the combination of the material properties of underfill and the substrate core were required for the other two packages.
{"title":"Investigation of the Influence of Material Properties on Warpage and Solder Joint Reliability of 2.5D & FO Package","authors":"K. Hamaguchi, M. Nakata, Kouta Segawa, N. Suzuki, T. Nonaka","doi":"10.1109/3DIC48104.2019.9058902","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058902","url":null,"abstract":"Warpage and solder joint reliability of 2.5D and fan-out packages were investigated using Finite Element Method comparing with the flip chip package. It revealed that the warpage could be reduced to about 50% and the solder joint reliability could be increased to 1.2 times. Regarding the FO package, using the higher elastic modulus underfill material was effective to improve the both of the warpage and the solder joint reliability. It also indicated that the optimization of the combination of the material properties of underfill and the substrate core were required for the other two packages.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114241221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058781
I. Jani, D. Lattard, Sarah Kim, H. K. Seo, Hae-sung Park, K. Sakui, Takayuki Ohba, De-Gong Liu, Po-chih Chen, Yi-Chieh Tsai, Kuan-Neng Chen, Jing Tao, H. Y. Li, P. Zhao, Y. Lim, A. Apriyana, Chuan-Seng Tan, F. Inoue, J. Bertheau, M. Goto, Y. Honda, T. Watabe, K. Hagiwara, M. Nanba, Y. Iguchi, T. Saraya, Masaharu Kobayashi, E. Higurashi
3DIC 2019 Authors Index
3DIC 2019作者索引
{"title":"3DIC 2019 Authors Index","authors":"I. Jani, D. Lattard, Sarah Kim, H. K. Seo, Hae-sung Park, K. Sakui, Takayuki Ohba, De-Gong Liu, Po-chih Chen, Yi-Chieh Tsai, Kuan-Neng Chen, Jing Tao, H. Y. Li, P. Zhao, Y. Lim, A. Apriyana, Chuan-Seng Tan, F. Inoue, J. Bertheau, M. Goto, Y. Honda, T. Watabe, K. Hagiwara, M. Nanba, Y. Iguchi, T. Saraya, Masaharu Kobayashi, E. Higurashi","doi":"10.1109/3DIC48104.2019.9058781","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058781","url":null,"abstract":"3DIC 2019 Authors Index","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125035157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058776
Chia-Hsuan Lee, Hsin-Chi Chang, Jui-Han Liu, Hiroyuki Ito, Young-Suk Kim, Kuan-Neng Chen, T. Ohba
In this study, we investigated the temperature cycling reliability of bumpless through silicon vias (TSVs) using a wafer-on-wafer (WOW) process. TSV interconnects were fabricated with and without via bottom cleaning, and TCT tests were conducted under the same conditions. We examined how the cleaning process affected the temperature cycling reliability. In addition, self-aligned multiple TSVs were found to be a key feature of WOW bumpless TSVs. The impact of a multi-via structure on the temperature cycling reliability was investigated as well. The results show that the resistances of bumpless TSVs with via bottom cleaning and multiple TSVs exhibited better temperature cycling reliability.
{"title":"Temperature Cycling Reliability of WOW Bumpless Through Silicon Vias","authors":"Chia-Hsuan Lee, Hsin-Chi Chang, Jui-Han Liu, Hiroyuki Ito, Young-Suk Kim, Kuan-Neng Chen, T. Ohba","doi":"10.1109/3DIC48104.2019.9058776","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058776","url":null,"abstract":"In this study, we investigated the temperature cycling reliability of bumpless through silicon vias (TSVs) using a wafer-on-wafer (WOW) process. TSV interconnects were fabricated with and without via bottom cleaning, and TCT tests were conducted under the same conditions. We examined how the cleaning process affected the temperature cycling reliability. In addition, self-aligned multiple TSVs were found to be a key feature of WOW bumpless TSVs. The impact of a multi-via structure on the temperature cycling reliability was investigated as well. The results show that the resistances of bumpless TSVs with via bottom cleaning and multiple TSVs exhibited better temperature cycling reliability.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130249323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058897
Ken Suzuki, Ryota Mizuno, Yutaro Nakoshi, H. Miura
In this study, the effect of crystallinity of grain and grain boundaries in electroplated gold thin-film interconnections on their electromigation (EM) resistance was investigated experimentally. The activation energy in Black’s equation was evaluated by accelerated EM test and Arrhenius plot as a function of the crystallinity of the interconnection. The activation energy in the electroplated gold thin-film interconnection was increased from 0.54 to 0.61 eV by improving the crystallinity due to the annealing at 400°C after electroplating. The lifetime of the interconnection was estimated by using the evaluated activation energy. The estimated result showed that the lifetime of the interconnection annealed at 400°C was about 20 times longer than that of as-electroplated interconnection. Therefore, the control of the crystallinity is indispensable for improving the reliability of electronic devices.
{"title":"Crystallinity Dependence of Long-Term Reliability of Electroplated Gold Thin-Film Interconnections","authors":"Ken Suzuki, Ryota Mizuno, Yutaro Nakoshi, H. Miura","doi":"10.1109/3DIC48104.2019.9058897","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058897","url":null,"abstract":"In this study, the effect of crystallinity of grain and grain boundaries in electroplated gold thin-film interconnections on their electromigation (EM) resistance was investigated experimentally. The activation energy in Black’s equation was evaluated by accelerated EM test and Arrhenius plot as a function of the crystallinity of the interconnection. The activation energy in the electroplated gold thin-film interconnection was increased from 0.54 to 0.61 eV by improving the crystallinity due to the annealing at 400°C after electroplating. The lifetime of the interconnection was estimated by using the evaluated activation energy. The estimated result showed that the lifetime of the interconnection annealed at 400°C was about 20 times longer than that of as-electroplated interconnection. Therefore, the control of the crystallinity is indispensable for improving the reliability of electronic devices.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132860569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058782
A. Matsuzawa
This paper proposes and discusses a universal ADC for sensor applications that can covers almost all sensor applications with one ADC. The combination of SAR ADC and incremental ASADC can cover high speed with low resolution and low noise with low speed applications with a unified ADC. Two prototype ADCs have been developed for general purpose sensing systems and for CMOS image sensors. The former ADC realized open-loop integrators using dynamic amplifiers. High SNR of 84 dB has been achieved and high FoMs over the 170 dB can be kept in wide signal frequency from 62.5 to 625 kHz and the power dissipation is scalable with sampling rate. The SAR+ΔΣADC for CMOS image sensor can reduce the noise down to 66 μV and realized small occupied area of 20 μm x 770 μm.
{"title":"A Universal ADC for Sensor Applications","authors":"A. Matsuzawa","doi":"10.1109/3DIC48104.2019.9058782","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058782","url":null,"abstract":"This paper proposes and discusses a universal ADC for sensor applications that can covers almost all sensor applications with one ADC. The combination of SAR ADC and incremental ASADC can cover high speed with low resolution and low noise with low speed applications with a unified ADC. Two prototype ADCs have been developed for general purpose sensing systems and for CMOS image sensors. The former ADC realized open-loop integrators using dynamic amplifiers. High SNR of 84 dB has been achieved and high FoMs over the 170 dB can be kept in wide signal frequency from 62.5 to 625 kHz and the power dissipation is scalable with sampling rate. The SAR+ΔΣADC for CMOS image sensor can reduce the noise down to 66 μV and realized small occupied area of 20 μm x 770 μm.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"260 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122895817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058886
R. Fischbach, T. Horst, J. Lienig
Micro-transfer printing (μTP) is a promising assembly technology that enables heterogeneous integration of dies originating from different wafers. It combines the advantages of pick-and-place in terms of flexibility with the advantages of wafer-level processing in terms of high throughput. μTP applies an elastomer stamp to transfer multiple dies from source to target wafers in parallel. Increasing the stamp size allows for the transfer of more dies at once and reciprocally shortens the manufacturing time, enabling extensive cost reductions. On the other hand, larger stamps result in a lower wafer utilization, thereby causing increases in costs. Finding the cost-optimal stamp layout is one of the key tasks when designing heterogeneous systems for μTP. There is no trivial solution to calculate the wafer utilization needed to evaluate the quality of a stamp layout. Based on a graph problem known as maximum independent set, we propose a model to determine the wafer utilization subject to the stamp and wafer layout. We demonstrate the application of our model within an economic cost function to optimize a μTP design with regard to manufacturing costs.
{"title":"A Graph-Based Model of Micro-Transfer Printing for Cost-Optimized Heterogeneous 2.5D Systems","authors":"R. Fischbach, T. Horst, J. Lienig","doi":"10.1109/3DIC48104.2019.9058886","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058886","url":null,"abstract":"Micro-transfer printing (μTP) is a promising assembly technology that enables heterogeneous integration of dies originating from different wafers. It combines the advantages of pick-and-place in terms of flexibility with the advantages of wafer-level processing in terms of high throughput. μTP applies an elastomer stamp to transfer multiple dies from source to target wafers in parallel. Increasing the stamp size allows for the transfer of more dies at once and reciprocally shortens the manufacturing time, enabling extensive cost reductions. On the other hand, larger stamps result in a lower wafer utilization, thereby causing increases in costs. Finding the cost-optimal stamp layout is one of the key tasks when designing heterogeneous systems for μTP. There is no trivial solution to calculate the wafer utilization needed to evaluate the quality of a stamp layout. Based on a graph problem known as maximum independent set, we propose a model to determine the wafer utilization subject to the stamp and wafer layout. We demonstrate the application of our model within an economic cost function to optimize a μTP design with regard to manufacturing costs.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114166623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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