Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058860
Takuji Miki, M. Nagata, Akihiro Tsukioka, N. Miura, Takaaki Okidono, Y. Araga, N. Watanabe, H. Shimamoto, K. Kikuchi
A 2.5D structure with a Si interposer stacked on a CMOS chip is developed to reduce impedance of power delivery networks (PDNs). A thick Cu backside buried metal (BBM) in Si Interposer provides low resistive power/ground wiring and also forms a large parasitic bypass capacitance between power and ground patterns, which drastically suppresses the power supply noise. The Si interposer was implemented over an cryptographic chip with a large scale digital circuit fabricated in 130 nm CMOS. An internal noise monitoring circuit embedded in the CMOS chip indicates it that the proposed over-the-top Si interposer (OVTT-SiIP) reduces a peak-to-peak power supply noise and DC drop during cryptographic operation to less than 50%.
{"title":"Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs","authors":"Takuji Miki, M. Nagata, Akihiro Tsukioka, N. Miura, Takaaki Okidono, Y. Araga, N. Watanabe, H. Shimamoto, K. Kikuchi","doi":"10.1109/3DIC48104.2019.9058860","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058860","url":null,"abstract":"A 2.5D structure with a Si interposer stacked on a CMOS chip is developed to reduce impedance of power delivery networks (PDNs). A thick Cu backside buried metal (BBM) in Si Interposer provides low resistive power/ground wiring and also forms a large parasitic bypass capacitance between power and ground patterns, which drastically suppresses the power supply noise. The Si interposer was implemented over an cryptographic chip with a large scale digital circuit fabricated in 130 nm CMOS. An internal noise monitoring circuit embedded in the CMOS chip indicates it that the proposed over-the-top Si interposer (OVTT-SiIP) reduces a peak-to-peak power supply noise and DC drop during cryptographic operation to less than 50%.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115227113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058876
D. Velenis, J. D. Vos, Soon-Wook Kim, J. Derakhshandeh, P. Bex, G. Capuz, S. Suhard, K. Rebibis, S. V. Huylenbroeck, E. Marinissen, A. Phommahaxay, Andy Miller, G. Beyer, G. V. D. Plas, E. Beyne
The increased requirements of data processing and reduced data latency has driven the demand for multi-layer 3D stacks for high performance systems and memory applications. In this paper, different approaches for multi-layer stacking are considered, including wafer-to-wafer (W2W) and die-to-die (D2D) stacking. The complexity of each approach is evaluated in terms of manufacturing cost and its impact on the stacked-system yield.
{"title":"Process Complexity and Cost Considerations of Multi-Layer Die Stacks","authors":"D. Velenis, J. D. Vos, Soon-Wook Kim, J. Derakhshandeh, P. Bex, G. Capuz, S. Suhard, K. Rebibis, S. V. Huylenbroeck, E. Marinissen, A. Phommahaxay, Andy Miller, G. Beyer, G. V. D. Plas, E. Beyne","doi":"10.1109/3DIC48104.2019.9058876","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058876","url":null,"abstract":"The increased requirements of data processing and reduced data latency has driven the demand for multi-layer 3D stacks for high performance systems and memory applications. In this paper, different approaches for multi-layer stacking are considered, including wafer-to-wafer (W2W) and die-to-die (D2D) stacking. The complexity of each approach is evaluated in terms of manufacturing cost and its impact on the stacked-system yield.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"24 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116610802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058856
K. Kiyoyama, Qian Zhengy, H. Hashimoto, H. Kino, T. Fukushima, Tetsu Tanaka
This paper describes a highly parallel analog signal processing method with three-dimensional (3-D) stacked neural network chip for convolutional and deep neural networks (CNNs and DNNs). The proposed chip has a stacked structure, which enables highly parallel mixed-signal operations like human brains with low power consumption. The product-sum operation using analog circuit in highly parallel calculation with low power supply current, but repeated calculations result in excessive noise (e.g. the offset voltage of the amplifier and 1/f noise, kT/C noise etc.) accumulation and degraded calculation accuracy. Therefore, analog signal processing with 3-D stacked multiple layers neural network chip require the noise reduction technique. In this design, correlated double sampling (CDS) is used to noise reduction technique with which reduce noise generated in the circuit. The proposed CDS circuit is designed with CMOS 0.18nm technology. As results of simulation analysis, it was confirmed that the CDS circuit reduced the offset voltage of composing amplifier and the noise voltages of the circuits placed before the CDS circuit to less than 1.25mV.
{"title":"Development of a CDS Circuit for 3-D Stacked Neural Network Chip using CMOS Analog Signal Processing","authors":"K. Kiyoyama, Qian Zhengy, H. Hashimoto, H. Kino, T. Fukushima, Tetsu Tanaka","doi":"10.1109/3DIC48104.2019.9058856","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058856","url":null,"abstract":"This paper describes a highly parallel analog signal processing method with three-dimensional (3-D) stacked neural network chip for convolutional and deep neural networks (CNNs and DNNs). The proposed chip has a stacked structure, which enables highly parallel mixed-signal operations like human brains with low power consumption. The product-sum operation using analog circuit in highly parallel calculation with low power supply current, but repeated calculations result in excessive noise (e.g. the offset voltage of the amplifier and 1/f noise, kT/C noise etc.) accumulation and degraded calculation accuracy. Therefore, analog signal processing with 3-D stacked multiple layers neural network chip require the noise reduction technique. In this design, correlated double sampling (CDS) is used to noise reduction technique with which reduce noise generated in the circuit. The proposed CDS circuit is designed with CMOS 0.18nm technology. As results of simulation analysis, it was confirmed that the CDS circuit reduced the offset voltage of composing amplifier and the noise voltages of the circuits placed before the CDS circuit to less than 1.25mV.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"116 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131204856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058887
Tadao Nakamura
Today's computer systems rather have a “big issue,” which is what is called the memory bottleneck, especially as their scale has been growing with nanotechnology year by year toward EXA-scale supercomputing for scientific calculations and deep learning in neural-networking. To solve the issue, we must be back to the origin of computer system design pursuing what memory in computer systems should be. We are developing Marching Memory (MM), and can show how the features of it suit the solution with reasonable conditions such as higher speed with no latency under lower power consumption than SRAM.
{"title":"An Introduction to Marching Memory (MM)","authors":"Tadao Nakamura","doi":"10.1109/3DIC48104.2019.9058887","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058887","url":null,"abstract":"Today's computer systems rather have a “big issue,” which is what is called the memory bottleneck, especially as their scale has been growing with nanotechnology year by year toward EXA-scale supercomputing for scientific calculations and deep learning in neural-networking. To solve the issue, we must be back to the origin of computer system design pursuing what memory in computer systems should be. We are developing Marching Memory (MM), and can show how the features of it suit the solution with reasonable conditions such as higher speed with no latency under lower power consumption than SRAM.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129590573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058827
Tadatomo Yamada, Ken Takano, Toshiaki Menjo, S. Takyu
This paper repots on a novel pick-up and place process for FO-WLP using high expansion tape and tape expansion machine device. We previously reported that we have developed the novel tape expansion machine with a new function allowing that tapes can be expanded in four directions to individually control these expansions. However, the tapes which are generally used as conventional dicing tape have problems such as tape breaking during high expansion and uneven chip distances after expansion. In this study, the effect of stress-strain curve of adhesive for expansion tape is investigated in order to achieve both properties of chip distances and chip accuracies after expanding. As a result of evaluation, average chip distance increases to 2,930μm (initial chip distance; 35^m) with 3mm square Si chips and the standard deviation is 43μm
{"title":"Study of Optimizing Stress-Strain Curve of Adhesive for High Expansion Tape","authors":"Tadatomo Yamada, Ken Takano, Toshiaki Menjo, S. Takyu","doi":"10.1109/3DIC48104.2019.9058827","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058827","url":null,"abstract":"This paper repots on a novel pick-up and place process for FO-WLP using high expansion tape and tape expansion machine device. We previously reported that we have developed the novel tape expansion machine with a new function allowing that tapes can be expanded in four directions to individually control these expansions. However, the tapes which are generally used as conventional dicing tape have problems such as tape breaking during high expansion and uneven chip distances after expansion. In this study, the effect of stress-strain curve of adhesive for expansion tape is investigated in order to achieve both properties of chip distances and chip accuracies after expanding. As a result of evaluation, average chip distance increases to 2,930μm (initial chip distance; 35^m) with 3mm square Si chips and the standard deviation is 43μm","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"20 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116670832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058838
H. Kino, T. Fukushima, Tetsu Tanaka
The three-dimensional (3D) integration process is a promising candidate to enhance electron-device performance. Typical 3D integration systems consist of vertically stacked several thin IC chips that are electrically connected with lots of through-Si vias (TSVs) and metal microbumps. Metal microbumps are surrounded by organic adhesive. An epoxy-based material, so-called underfill, has been widely used to fill the gap between several chips. In general, the coefficient of thermal expansion (CTE) of the underfill material is larger than that of metal microbumps. This CTE mismatch induces local bending stress in thinned IC chips. This local bending stress would affect the CMOS circuit in thinned IC chips. Therefore, we should suppress the local bending stress to realize 3D IC with high reliability. To suppress the local bending stress, we have proposed a novel underfill with negative-thermal-expansion material. In this study, we investigated the characteristics of the negativethermal-expansion material surrounded by the matrix of the underfill.
{"title":"Investigation of the Underfill with Negative-Thermal-Expansion Material to Suppress Mechanical Stress in 3D Integration System","authors":"H. Kino, T. Fukushima, Tetsu Tanaka","doi":"10.1109/3DIC48104.2019.9058838","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058838","url":null,"abstract":"The three-dimensional (3D) integration process is a promising candidate to enhance electron-device performance. Typical 3D integration systems consist of vertically stacked several thin IC chips that are electrically connected with lots of through-Si vias (TSVs) and metal microbumps. Metal microbumps are surrounded by organic adhesive. An epoxy-based material, so-called underfill, has been widely used to fill the gap between several chips. In general, the coefficient of thermal expansion (CTE) of the underfill material is larger than that of metal microbumps. This CTE mismatch induces local bending stress in thinned IC chips. This local bending stress would affect the CMOS circuit in thinned IC chips. Therefore, we should suppress the local bending stress to realize 3D IC with high reliability. To suppress the local bending stress, we have proposed a novel underfill with negative-thermal-expansion material. In this study, we investigated the characteristics of the negativethermal-expansion material surrounded by the matrix of the underfill.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133613365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058905
A. Jouve, L. Sanchez, C. Castan, N. Bresson, F. Fournel, N. Raynaud, P. Metzger
Die-To-Wafer (D2W) direct hybrid bonding is foreseen as a major breakthrough for the future of 3D components; however, its industrialization rises some additional challenges compared to Wafer-To-Wafer processing. This paper presents a 300mm wafer complete solution developed at LETI to improve bonding yield of D2W hybrid bonding using copper interconnections until the assessment of the electrical performances thanks to a dedicated 300mm electrical test vehicle and robust stacking system. Stackings with +/-1.5μm accuracy and excellent bonding interface have been obtained (80% bonding yield). After stacking and annealing, the die can be thinned down to 10μm without damage. Electrical yield measured on daisy-chains with more than 20.000 connections present more than 75% yield and shown very limited drift after preliminary environmental reliability tests. All these results confirmed the high industrial potential of D2W hybrid bonding technology.
{"title":"Die to Wafer Direct Hybid Bonding Demonstration with High Alignment Accuracy and Electrical Yields","authors":"A. Jouve, L. Sanchez, C. Castan, N. Bresson, F. Fournel, N. Raynaud, P. Metzger","doi":"10.1109/3DIC48104.2019.9058905","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058905","url":null,"abstract":"Die-To-Wafer (D2W) direct hybrid bonding is foreseen as a major breakthrough for the future of 3D components; however, its industrialization rises some additional challenges compared to Wafer-To-Wafer processing. This paper presents a 300mm wafer complete solution developed at LETI to improve bonding yield of D2W hybrid bonding using copper interconnections until the assessment of the electrical performances thanks to a dedicated 300mm electrical test vehicle and robust stacking system. Stackings with +/-1.5μm accuracy and excellent bonding interface have been obtained (80% bonding yield). After stacking and annealing, the die can be thinned down to 10μm without damage. Electrical yield measured on daisy-chains with more than 20.000 connections present more than 75% yield and shown very limited drift after preliminary environmental reliability tests. All these results confirmed the high industrial potential of D2W hybrid bonding technology.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122361360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058891
Minami Nakayama, S. Abe, S. Matsumoto
Power supply on chip (power-SoC) has been caught attentions because ultimately miniaturize the power supplies. Especially, the 3D power-SoC is attractive and is fabricated using LSI and MEMS process. It is important to meet the various electrical requirements for expanding applications because they are fabricated using mass production process. In such situations, series and/or parallel connections of them is attractive. However, we generally use transformers as power supplies for floating gate driver circuits when we connect DC-DC converters series. Transformers are not suitable for power-SoC because they disturb miniaturization. In this paper, we propose a transformer-less floating gate driver circuit for 3D power SoC.
{"title":"Transformer-Less Floating Gate Driver for 3D Power SoC","authors":"Minami Nakayama, S. Abe, S. Matsumoto","doi":"10.1109/3DIC48104.2019.9058891","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058891","url":null,"abstract":"Power supply on chip (power-SoC) has been caught attentions because ultimately miniaturize the power supplies. Especially, the 3D power-SoC is attractive and is fabricated using LSI and MEMS process. It is important to meet the various electrical requirements for expanding applications because they are fabricated using mass production process. In such situations, series and/or parallel connections of them is attractive. However, we generally use transformers as power supplies for floating gate driver circuits when we connect DC-DC converters series. Transformers are not suitable for power-SoC because they disturb miniaturization. In this paper, we propose a transformer-less floating gate driver circuit for 3D power SoC.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124866472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058885
Ziyue Zhang, Yingtao Ding, Zhiming Chen, Mingrui Zhou, Lei Xiao, Ziru Cai, Miao Xiong, X. Gong
Three-dimensional (3D) integration and interposer technology provide a promising solution for the continued minimization of modern electronic system. In this paper, through-glass-via (TGV) technique is used to form an ultra-compact bandpass filter (BPF). The proposed BPF is fully composed of well-designed TGV -based 3D array capacitors and 3D spiral inductors, and corresponding redistribution layers (RDL). A TGV-based shielding ring is utilized, which enhances the anti-interference property of the BPF, and also improves its thermal dissipation capability. The central frequency (f0) of the BPF is near 5 GHz, and the insertion loss and return loss are 2.25 dB and 15.8 dB, respectively. Moreover, the device footprint is only 0.91 × 0.58 mm2even including the shielding ring. A feasible fabrication flow is also proposed for the BPF, showing the optimization on process complexity and fabrication cost. The BPF is promising for the minimization of future 5G applications and system integration.
{"title":"Design and Evaluation of a Novel and Ultra-Compact Fully-TGV-based Self-Shielding Bandpass Filter for 5G Applications","authors":"Ziyue Zhang, Yingtao Ding, Zhiming Chen, Mingrui Zhou, Lei Xiao, Ziru Cai, Miao Xiong, X. Gong","doi":"10.1109/3DIC48104.2019.9058885","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058885","url":null,"abstract":"Three-dimensional (3D) integration and interposer technology provide a promising solution for the continued minimization of modern electronic system. In this paper, through-glass-via (TGV) technique is used to form an ultra-compact bandpass filter (BPF). The proposed BPF is fully composed of well-designed TGV -based 3D array capacitors and 3D spiral inductors, and corresponding redistribution layers (RDL). A TGV-based shielding ring is utilized, which enhances the anti-interference property of the BPF, and also improves its thermal dissipation capability. The central frequency (f0) of the BPF is near 5 GHz, and the insertion loss and return loss are 2.25 dB and 15.8 dB, respectively. Moreover, the device footprint is only 0.91 × 0.58 mm2even including the shielding ring. A feasible fabrication flow is also proposed for the BPF, showing the optimization on process complexity and fabrication cost. The BPF is promising for the minimization of future 5G applications and system integration.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124984730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/3DIC48104.2019.9058786
A. Shigetou, Tilo H. Yang, C. Kao
In this study, a heterogeneous bonding between organic and inorganic materials was realized at low temperature without vacuum atmosphere, by means of the vapor-assisted vacuum ultraviolet (VUV) surface modification method. In this method, an ultrathin bridge layer was created between the surfaces via the VUV irradiation in nitrogen atmosphere containing lower alcohol vapor. The radical species of H, OH, and CH sequentially enabled the initial surface cleaning, partial deoxidization of native oxide, and the formation of hydroxyl-terminated alkyl bridge with multidentate carboxylate on the inorganic material. Due to the dynamic competition of reversible hydrolysis of the multidentate carboxylate, the waterproof characteristic was expected to the bridge layer. The bridge layer was then bonded strongly to the modified organic material surface by hydrogen bond on the moment of contact at room temperature, which was followed by the dehydration condensation upon heating at 423.2 K around. Given polyether ether ketone (PEEK) and wiring metals as the typical materials in the fields of flexible electronics and structural materials, the evolution of chemical surface binding condition was analyzed to optimize the bridge formation. The bond interface showed cohesive fracture after the high humidity storage testing at 358.2 K and RH 85% for 1000 hours. Such the hybrid bonding with ultrathin bridge layer will be of the actual use in 3D flexible integration in near future.
{"title":"Hydrolysis-Tolerant Hybrid Bonding in Ambient Atmosphere for 3D Integration","authors":"A. Shigetou, Tilo H. Yang, C. Kao","doi":"10.1109/3DIC48104.2019.9058786","DOIUrl":"https://doi.org/10.1109/3DIC48104.2019.9058786","url":null,"abstract":"In this study, a heterogeneous bonding between organic and inorganic materials was realized at low temperature without vacuum atmosphere, by means of the vapor-assisted vacuum ultraviolet (VUV) surface modification method. In this method, an ultrathin bridge layer was created between the surfaces via the VUV irradiation in nitrogen atmosphere containing lower alcohol vapor. The radical species of H, OH, and CH sequentially enabled the initial surface cleaning, partial deoxidization of native oxide, and the formation of hydroxyl-terminated alkyl bridge with multidentate carboxylate on the inorganic material. Due to the dynamic competition of reversible hydrolysis of the multidentate carboxylate, the waterproof characteristic was expected to the bridge layer. The bridge layer was then bonded strongly to the modified organic material surface by hydrogen bond on the moment of contact at room temperature, which was followed by the dehydration condensation upon heating at 423.2 K around. Given polyether ether ketone (PEEK) and wiring metals as the typical materials in the fields of flexible electronics and structural materials, the evolution of chemical surface binding condition was analyzed to optimize the bridge formation. The bond interface showed cohesive fracture after the high humidity storage testing at 358.2 K and RH 85% for 1000 hours. Such the hybrid bonding with ultrathin bridge layer will be of the actual use in 3D flexible integration in near future.","PeriodicalId":440556,"journal":{"name":"2019 International 3D Systems Integration Conference (3DIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129122562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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