Pub Date : 2019-06-01DOI: 10.23919/IWJT.2019.8802904
F. Guarín
CMOS device reliability is a key ingredient for the market introduction of leading edge semiconductor technologies. Performance enhancement and reliability balance is critical for the optimization of competitive CMOS solutions for advanced technology nodes. To fully leverage performance enhancement elements the device reliability impact needs to fully characterized on the CMOS circuits like SRAM, ring-oscillators and RF Power Amplifiers.A critical review of the reliability methods used for RF device characterization as well as the development of guidelines and qualification methodologies necessary for the introduction of Silicon based RF technologies to market is presented here. The implications and requirements to the reliability of RF applications will be considered and validated at the discrete device as well as for typical circuit applications. The selection of suitable stress/test methodologies as well as the selection of meaningful targets will be discussed.
{"title":"Reliability Considerations for the Qualification of Leading Edge CMOS Technologies","authors":"F. Guarín","doi":"10.23919/IWJT.2019.8802904","DOIUrl":"https://doi.org/10.23919/IWJT.2019.8802904","url":null,"abstract":"CMOS device reliability is a key ingredient for the market introduction of leading edge semiconductor technologies. Performance enhancement and reliability balance is critical for the optimization of competitive CMOS solutions for advanced technology nodes. To fully leverage performance enhancement elements the device reliability impact needs to fully characterized on the CMOS circuits like SRAM, ring-oscillators and RF Power Amplifiers.A critical review of the reliability methods used for RF device characterization as well as the development of guidelines and qualification methodologies necessary for the introduction of Silicon based RF technologies to market is presented here. The implications and requirements to the reliability of RF applications will be considered and validated at the discrete device as well as for typical circuit applications. The selection of suitable stress/test methodologies as well as the selection of meaningful targets will be discussed.","PeriodicalId":441279,"journal":{"name":"2019 19th International Workshop on Junction Technology (IWJT)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128777903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/IWJT.2019.8802903
E. Sangiorgi
The NEREID project (“NanoElectronics Roadmap for Europe: Identification and Dissemination”) is dedicated to map the future of European Nanoelectronics. NEREID’s objective is to develop a medium- and long-term roadmap for the European nanoelectronics industry, starting from the needs of applications to address societal challenges and leveraging the strengths of the European eco-system. In addition, it will lead to an early benchmark/identification of promising novel nano-electronic technologies, based on the advanced concepts developed by Research Centers and Universities, and an identification of bottlenecks all along the innovation (value) chain.
{"title":"NEREID: NanoElectronics Roadmap for Europe: Identification and Dissemination","authors":"E. Sangiorgi","doi":"10.23919/IWJT.2019.8802903","DOIUrl":"https://doi.org/10.23919/IWJT.2019.8802903","url":null,"abstract":"The NEREID project (“NanoElectronics Roadmap for Europe: Identification and Dissemination”) is dedicated to map the future of European Nanoelectronics. NEREID’s objective is to develop a medium- and long-term roadmap for the European nanoelectronics industry, starting from the needs of applications to address societal challenges and leveraging the strengths of the European eco-system. In addition, it will lead to an early benchmark/identification of promising novel nano-electronic technologies, based on the advanced concepts developed by Research Centers and Universities, and an identification of bottlenecks all along the innovation (value) chain.","PeriodicalId":441279,"journal":{"name":"2019 19th International Workshop on Junction Technology (IWJT)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123954702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/IWJT.2019.8802888
X. Gong, Ying Wu, Haiwen Xu, Kaizhen Han, L. Chua, W. Zou, T. Henry
Contact resistance R c in the source/drain (S/D) regions of field-effect transistors (FETs) has increased significantly due to the shrinkage of contact area accompanied with the scaling of device dimensions in the past decades [1] . For the state-of-art transistor technology, the contact area is around 10×10 nm 2 [2] . R c , inversely proportional to the effective contact area, is the main parasitic resistance that limits the on-state current and switching speed of the device in the leading technology. To alleviate the impact of R c , an ultralow specific contact resistivity ρ c of less than 10 −9 Ω-cm 2 is required [3] .
{"title":"Metal/P-type GeSn Contacts with Ultra-low Specific Contact Resistivity","authors":"X. Gong, Ying Wu, Haiwen Xu, Kaizhen Han, L. Chua, W. Zou, T. Henry","doi":"10.23919/IWJT.2019.8802888","DOIUrl":"https://doi.org/10.23919/IWJT.2019.8802888","url":null,"abstract":"Contact resistance R c in the source/drain (S/D) regions of field-effect transistors (FETs) has increased significantly due to the shrinkage of contact area accompanied with the scaling of device dimensions in the past decades [1] . For the state-of-art transistor technology, the contact area is around 10×10 nm 2 [2] . R c , inversely proportional to the effective contact area, is the main parasitic resistance that limits the on-state current and switching speed of the device in the leading technology. To alleviate the impact of R c , an ultralow specific contact resistivity ρ c of less than 10 −9 Ω-cm 2 is required [3] .","PeriodicalId":441279,"journal":{"name":"2019 19th International Workshop on Junction Technology (IWJT)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133914774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/IWJT.2019.8802619
Chuck Paeng, He Zhang, Y. Kim
Atomistic-isotropic film removal has been demonstrated using noble techniques. Its surface modification such as oxidation or halogenation has been used to form a volatile by-product of mono layer by decoupled plasma. Surface modification has been developed using various conditions to adsorb with specific chemistries such as ligands or halogens at low water temperature, and in-situ thermal pulse with flash lamp as a desorption step has been performed to remove films atomistically to avoid unwanted thermal budget and extremely high selectivity. Finally performing continuous sequential cycle of adsorption and desorption step enables to remove films consistently with infinite selectivity.
{"title":"Noble Approach to Remove Films Isotropically-Atomistically at Room Temperature by Introducing Rapid Thermal Pulse Sequentially","authors":"Chuck Paeng, He Zhang, Y. Kim","doi":"10.23919/IWJT.2019.8802619","DOIUrl":"https://doi.org/10.23919/IWJT.2019.8802619","url":null,"abstract":"Atomistic-isotropic film removal has been demonstrated using noble techniques. Its surface modification such as oxidation or halogenation has been used to form a volatile by-product of mono layer by decoupled plasma. Surface modification has been developed using various conditions to adsorb with specific chemistries such as ligands or halogens at low water temperature, and in-situ thermal pulse with flash lamp as a desorption step has been performed to remove films atomistically to avoid unwanted thermal budget and extremely high selectivity. Finally performing continuous sequential cycle of adsorption and desorption step enables to remove films consistently with infinite selectivity.","PeriodicalId":441279,"journal":{"name":"2019 19th International Workshop on Junction Technology (IWJT)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123760791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/IWJT.2019.8802616
W. Yoo, Jung Gon Kim, T. Ishigaki, K. Kang
Formation of high integrity junctions with low junction leakage and defects is essential for fabricating high performance devices with advanced node devices. Understanding of implant activation and implant damage recovery mechanisms during annealing process steps is limited. Development of noncontact implant activation and residual damage monitoring techniques would be beneficial.
{"title":"Comprehensive Characterization of B+ Implanted Silicon after Rapid Thermal Annealing","authors":"W. Yoo, Jung Gon Kim, T. Ishigaki, K. Kang","doi":"10.23919/IWJT.2019.8802616","DOIUrl":"https://doi.org/10.23919/IWJT.2019.8802616","url":null,"abstract":"Formation of high integrity junctions with low junction leakage and defects is essential for fabricating high performance devices with advanced node devices. Understanding of implant activation and implant damage recovery mechanisms during annealing process steps is limited. Development of noncontact implant activation and residual damage monitoring techniques would be beneficial.","PeriodicalId":441279,"journal":{"name":"2019 19th International Workshop on Junction Technology (IWJT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116039364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/IWJT.2019.8802885
Hao Yu, P. Hsu, A. Vais, E. Simoen, N. Waldron, N. Collaert
Electron traps are detected from vertical n+-GaAs/n−-InGaP/p+-GaAs diodes with deep-level transient spectroscopy (DLTS). Combining lock-in window (tw) varying DLTS and double-correlation DLTS (DDTLS), we assign the electron traps to surface states at the sidewalls of the diodes. The methodology is introduced in the paper.
{"title":"Electron Traps at Sidewalls of Vertical n+-GaAs/n−-InGaP/p+-GaAs Diodes Detected with Deep-Level Transient Spectroscopy","authors":"Hao Yu, P. Hsu, A. Vais, E. Simoen, N. Waldron, N. Collaert","doi":"10.23919/IWJT.2019.8802885","DOIUrl":"https://doi.org/10.23919/IWJT.2019.8802885","url":null,"abstract":"Electron traps are detected from vertical n<sup>+</sup>-GaAs/n<sup>−</sup>-InGaP/p<sup>+</sup>-GaAs diodes with deep-level transient spectroscopy (DLTS). Combining lock-in window (t<inf>w</inf>) varying DLTS and double-correlation DLTS (DDTLS), we assign the electron traps to surface states at the sidewalls of the diodes. The methodology is introduced in the paper.","PeriodicalId":441279,"journal":{"name":"2019 19th International Workshop on Junction Technology (IWJT)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121891687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/IWJT.2019.8802887
J. Borrel, M. Grégoire, E. Ghegin, S. Joblot, Rémi Vallat, A. Valery, M. Juhel, R. Bianchi
Until the 90-nm node, CoSi 2 silicide have been widely used in semiconductor industry. More recently, in order to meet performance requirements in advanced digital nodes, process integration have consensually shifted towards NiPt-based silicides [1] . Nevertheless, advanced memory and imaging technologies being still based on 90-nm core MOS, developments and studies on CoSi 2 silicide are still of the best interest as new challenges are emerging.
{"title":"Pre-Amorphization Implants and in-situ Surface Preparation Optimization for Low Co-Silicided Area Density","authors":"J. Borrel, M. Grégoire, E. Ghegin, S. Joblot, Rémi Vallat, A. Valery, M. Juhel, R. Bianchi","doi":"10.23919/IWJT.2019.8802887","DOIUrl":"https://doi.org/10.23919/IWJT.2019.8802887","url":null,"abstract":"Until the 90-nm node, CoSi 2 silicide have been widely used in semiconductor industry. More recently, in order to meet performance requirements in advanced digital nodes, process integration have consensually shifted towards NiPt-based silicides [1] . Nevertheless, advanced memory and imaging technologies being still based on 90-nm core MOS, developments and studies on CoSi 2 silicide are still of the best interest as new challenges are emerging.","PeriodicalId":441279,"journal":{"name":"2019 19th International Workshop on Junction Technology (IWJT)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126798845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/IWJT.2019.8802901
Kazuki Senga, S. Shibayama, M. Sakashita, S. Zaima, O. Nakatsuka
For realizing high-performance Ge-channel metal-oxide-semiconductor field-effect transistor (MOSFET), the reduction of parasitic resistance is one of the most important issues [1] . However, it is generally difficult to reduce the contact resistivity at metal/ n -Ge interface because of its high Schottky barrier height (SBH) around 0.5–0.6 eV, in which the Fermi level of the metal is pinned at the valence band edge of Ge; well-known Fermi level pinning (FLP) phenomenon [2] , [3] . One of the considerable reasons for FLP is disorder-induced gap states owing to dangling bonds at the metal/Ge interface [4] . There are some reports in which an epitaxial metal/Ge interface alleviates FLP and the SBH can be lowered with Fe 3 Si/ n -Ge(111) [5] , Mn 3 Ge 5 / n -Ge(111) [6] , and NiGe/ n -Ge(110) contacts [7] .
为了实现高性能的ge沟道金属氧化物半导体场效应晶体管(MOSFET)，降低寄生电阻是最重要的问题之一[1]。然而，由于金属/ n -Ge界面的肖特基势垒高度(SBH)在0.5 ~ 0.6 eV左右，金属的费米能级被钉住在Ge的价带边缘，因此通常难以降低金属/ n -Ge界面的接触电阻率;众所周知的费米能级钉住现象[2]，[3]。FLP的一个重要原因是由于金属/锗界面上的悬空键引起的无序间隙状态[4]。有一些报道称外延金属/Ge界面可以缓解FLP, Fe 3si / n -Ge(111) [5]， Mn 3ge 5 / n -Ge(111)[6]和nge / n -Ge(110)接触可以降低SBH[7]。
{"title":"Further reduction of Schottky barrier height of Hf-germanide/n-Ge(001) contacts by forming epitaxial HfGe2","authors":"Kazuki Senga, S. Shibayama, M. Sakashita, S. Zaima, O. Nakatsuka","doi":"10.23919/IWJT.2019.8802901","DOIUrl":"https://doi.org/10.23919/IWJT.2019.8802901","url":null,"abstract":"For realizing high-performance Ge-channel metal-oxide-semiconductor field-effect transistor (MOSFET), the reduction of parasitic resistance is one of the most important issues [1] . However, it is generally difficult to reduce the contact resistivity at metal/ n -Ge interface because of its high Schottky barrier height (SBH) around 0.5–0.6 eV, in which the Fermi level of the metal is pinned at the valence band edge of Ge; well-known Fermi level pinning (FLP) phenomenon [2] , [3] . One of the considerable reasons for FLP is disorder-induced gap states owing to dangling bonds at the metal/Ge interface [4] . There are some reports in which an epitaxial metal/Ge interface alleviates FLP and the SBH can be lowered with Fe 3 Si/ n -Ge(111) [5] , Mn 3 Ge 5 / n -Ge(111) [6] , and NiGe/ n -Ge(110) contacts [7] .","PeriodicalId":441279,"journal":{"name":"2019 19th International Workshop on Junction Technology (IWJT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127399394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/IWJT.2019.8802900
M. Current, G. Hobler, Yoji Kawasaki
This tutorial reviews key issues for use of highly-channeled profiles with MeV energy dopants in Si. Practical issues for systems and process, including beam-wafer alignment, beam divergence and wafer temperature, are discussed as well as the use of Monte-Carlo modeling to guide process development. Recent photo- and cathodo-luminescence results on the effects of elevated wafer implant temperatures on residual defects after annealing in channeled MeV dopant implants are outlined.
{"title":"Aspects of Highly-channeled MeV Implants of Dopants in Si(100)","authors":"M. Current, G. Hobler, Yoji Kawasaki","doi":"10.23919/IWJT.2019.8802900","DOIUrl":"https://doi.org/10.23919/IWJT.2019.8802900","url":null,"abstract":"This tutorial reviews key issues for use of highly-channeled profiles with MeV energy dopants in Si. Practical issues for systems and process, including beam-wafer alignment, beam divergence and wafer temperature, are discussed as well as the use of Monte-Carlo modeling to guide process development. Recent photo- and cathodo-luminescence results on the effects of elevated wafer implant temperatures on residual defects after annealing in channeled MeV dopant implants are outlined.","PeriodicalId":441279,"journal":{"name":"2019 19th International Workshop on Junction Technology (IWJT)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122535243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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