Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745202
Keerthi Heragu, J. Patel, V. Agrawal
We propose a simulation-based technique that uses a genetic algorithm (GA) to generate tests for delay faults on segments of any given length. At every line, we assume that an upper bound on the number of testable segment faults that originate there is known. Such a bound is efficiently computed by an implication-based technique. The fitness function for the GA is derived from an objective function that favors vectors which might detect a large number of faults. This is accomplished by a simulator used as a base engine, by dynamically identifying a line m with the highest upper bound for the number of segments on which faults can and are yet to be tested, and by ranking vectors according to their ability to target the simultaneous objectives of invoking a transition on m and maximizing the number of signals that propagate robustly in the fanout cone of m. Rather than limiting the number of generations of evolution in the GA, we obtain improved results by using the diversity of the individuals in a population as a stopping criterion. Results indicate that for small segment lengths, reasonable robust segment delay test coverages can be obtained for most benchmark circuits. Also, the tests generated using the segment delay fault model detect a large number of transition and path delay faults. For example in the benchmark circuit c3540, tests generated for faults on segments of length 5 had a transition fault coverage of 96.1% and were able to detect 9,246 path faults.
{"title":"A test generator for segment delay faults","authors":"Keerthi Heragu, J. Patel, V. Agrawal","doi":"10.1109/ICVD.1999.745202","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745202","url":null,"abstract":"We propose a simulation-based technique that uses a genetic algorithm (GA) to generate tests for delay faults on segments of any given length. At every line, we assume that an upper bound on the number of testable segment faults that originate there is known. Such a bound is efficiently computed by an implication-based technique. The fitness function for the GA is derived from an objective function that favors vectors which might detect a large number of faults. This is accomplished by a simulator used as a base engine, by dynamically identifying a line m with the highest upper bound for the number of segments on which faults can and are yet to be tested, and by ranking vectors according to their ability to target the simultaneous objectives of invoking a transition on m and maximizing the number of signals that propagate robustly in the fanout cone of m. Rather than limiting the number of generations of evolution in the GA, we obtain improved results by using the diversity of the individuals in a population as a stopping criterion. Results indicate that for small segment lengths, reasonable robust segment delay test coverages can be obtained for most benchmark circuits. Also, the tests generated using the segment delay fault model detect a large number of transition and path delay faults. For example in the benchmark circuit c3540, tests generated for faults on segments of length 5 had a transition fault coverage of 96.1% and were able to detect 9,246 path faults.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127916560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745190
Amit Narayan
ROBDDs are frequently used as the representation of choice to solve various CAD problems such as synthesis, digital-system verification and testing. However, the size of an ROBDD for a function can be exponential in the number of independent variables of the function. This so called "memory explosion problem" limits the applicability of ROBDD based algorithms and has been the locus of intense research over the past several years. Recently, some new techniques have been proposed which have significantly extended the frontiers of ROBDD based methods. This paper surveys some of these recent advances in this area and discusses their merits and shortcomings.
{"title":"Recent advances in BDD based representations for Boolean functions: a survey","authors":"Amit Narayan","doi":"10.1109/ICVD.1999.745190","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745190","url":null,"abstract":"ROBDDs are frequently used as the representation of choice to solve various CAD problems such as synthesis, digital-system verification and testing. However, the size of an ROBDD for a function can be exponential in the number of independent variables of the function. This so called \"memory explosion problem\" limits the applicability of ROBDD based algorithms and has been the locus of intense research over the past several years. Recently, some new techniques have been proposed which have significantly extended the frontiers of ROBDD based methods. This paper surveys some of these recent advances in this area and discusses their merits and shortcomings.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129806437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745162
Srivatsan Srinivasan, Parminder Chhabra, P. Jaini, A. Aziz, L. John
Formal verification of cache coherence in a multiprocessor environment is essential in ascertaining the validity of a cache coherence protocol. Although a number of cache coherence verification techniques are available, very few authors have reported results on verification of cache coherence protocols using symbolic model checking. In this paper we present the verification of a three state snoop-based cache coherence protocol using model checking in VIS. As symbolic model checking is beset with the state explosion problem, directly verifying the protocol for a large number of processors is infeasible. We have developed a set of modeling strategies that we found useful in verifying cache coherence of two to five processor configurations. In this paper, we report the techniques we adopted in modeling and verifying the protocol.
{"title":"Formal verification of a snoop-based cache coherence protocol using symbolic model checking","authors":"Srivatsan Srinivasan, Parminder Chhabra, P. Jaini, A. Aziz, L. John","doi":"10.1109/ICVD.1999.745162","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745162","url":null,"abstract":"Formal verification of cache coherence in a multiprocessor environment is essential in ascertaining the validity of a cache coherence protocol. Although a number of cache coherence verification techniques are available, very few authors have reported results on verification of cache coherence protocols using symbolic model checking. In this paper we present the verification of a three state snoop-based cache coherence protocol using model checking in VIS. As symbolic model checking is beset with the state explosion problem, directly verifying the protocol for a large number of processors is infeasible. We have developed a set of modeling strategies that we found useful in verifying cache coherence of two to five processor configurations. In this paper, we report the techniques we adopted in modeling and verifying the protocol.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"52 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132511392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745209
K. Paul, P. Dutta, D. R. Chowdhury, P. Nandi, P. P. Chaudhuri
A novel scheme for fast decompression of grey level image data has been presented in this paper. One of the major motivations for this work is to evolve a scheme to support on-line decompression of image data files. The throughput of the decompression hardware block has been shown to support on-line decompression of image data. The results presented in this paper show that the algorithm for decompression achieves good compression ratio as well as acceptable subjective and objective image fidelity.
{"title":"A VLSI architecture for on-line image decompression using GF(2/sup 8/) cellular automata","authors":"K. Paul, P. Dutta, D. R. Chowdhury, P. Nandi, P. P. Chaudhuri","doi":"10.1109/ICVD.1999.745209","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745209","url":null,"abstract":"A novel scheme for fast decompression of grey level image data has been presented in this paper. One of the major motivations for this work is to evolve a scheme to support on-line decompression of image data files. The throughput of the decompression hardware block has been shown to support on-line decompression of image data. The results presented in this paper show that the algorithm for decompression achieves good compression ratio as well as acceptable subjective and objective image fidelity.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122628399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745131
B. Bhaumik, G. Visweswaran, R. Lakshminarasimhan
Generalized Modified Positional Syndrome (GMPS), of order p, a new compaction scheme for test output data is presented. The order p determines the aliasing probability and the amount of hardware overhead required to implement the scheme. GMPS of order two gives an aliasing probability about an order of magnitude lower than the best scheme reported in literature with minimal extra hardware. A hardware realization scheme for GMPS has been presented. The scheme uses adders with feedback.
{"title":"A new test compression scheme","authors":"B. Bhaumik, G. Visweswaran, R. Lakshminarasimhan","doi":"10.1109/ICVD.1999.745131","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745131","url":null,"abstract":"Generalized Modified Positional Syndrome (GMPS), of order p, a new compaction scheme for test output data is presented. The order p determines the aliasing probability and the amount of hardware overhead required to implement the scheme. GMPS of order two gives an aliasing probability about an order of magnitude lower than the best scheme reported in literature with minimal extra hardware. A hardware realization scheme for GMPS has been presented. The scheme uses adders with feedback.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120925020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745145
S. Sundareswaran, D. Blaauw, A. Dharchoudhury
Static transistor level timing analysis has become a more and more accepted method for performance evaluation because of its reduced design cycle time when compared to the vector based timing analysis. These static timing analysis tools use transistor level delay modelling to identify timing-critical paths and estimate performance of the design. With increase in complexity of designs it becomes necessary to verify the timing-critical paths using SPICE-simulations. In order to perform accurate modelling for SPICE simulations, it becomes imperative to identify all the devices and the signal-states on the nodes, for a given input to output transition. The current techniques use greedy approaches for each input to output transition in a channel connected component. These techniques consider turning-on all transistors on the primary conducting path and turning-off remaining transistors on the side-paths. Thus, these techniques don't consider appropriate loading on the output node due to transistors on the side-paths and the fanout paths. These techniques also don't consider the input signal correlations. This paper presents a three-tier heuristics to determine side path assertions, such that it maximizes, as much as possible, the load at the output node, for a given set of input to output transitions. Also, a method to perform the fanout path assertions is presented. This technique has been used for SPICE-verification of the timing-critical paths of transistor level designs. The results have been compared using SPICE simulations of the same designs.
{"title":"A three-tier assertion technique for SPICE verification of transistor level timing analysis","authors":"S. Sundareswaran, D. Blaauw, A. Dharchoudhury","doi":"10.1109/ICVD.1999.745145","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745145","url":null,"abstract":"Static transistor level timing analysis has become a more and more accepted method for performance evaluation because of its reduced design cycle time when compared to the vector based timing analysis. These static timing analysis tools use transistor level delay modelling to identify timing-critical paths and estimate performance of the design. With increase in complexity of designs it becomes necessary to verify the timing-critical paths using SPICE-simulations. In order to perform accurate modelling for SPICE simulations, it becomes imperative to identify all the devices and the signal-states on the nodes, for a given input to output transition. The current techniques use greedy approaches for each input to output transition in a channel connected component. These techniques consider turning-on all transistors on the primary conducting path and turning-off remaining transistors on the side-paths. Thus, these techniques don't consider appropriate loading on the output node due to transistors on the side-paths and the fanout paths. These techniques also don't consider the input signal correlations. This paper presents a three-tier heuristics to determine side path assertions, such that it maximizes, as much as possible, the load at the output node, for a given set of input to output transitions. Also, a method to perform the fanout path assertions is presented. This technique has been used for SPICE-verification of the timing-critical paths of transistor level designs. The results have been compared using SPICE simulations of the same designs.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123138360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745155
Ajoy C. Siddabathuni, M. Balakrishnan
This article presents the core design of a high-speed [8 Gbps] nonblocking multicast ATM cell switch. The switch uses a self-routing ring of shift-registers to transfer cells from one port to another in a pipelined fashion resolving output contention and efficiently handling multicast cells. The "ring" architecture is advantageous from a VLSI standpoint. A novel feature of this design is an intelligent scheduler at the output buffers which provided a physical switch level support for QoS handling. This algorithm called helix-virtual-Q emulates a "Weighted-Round-Robin Scheduling" on a single-FIFO based output buffer. An object oriented high level simulation model provided key design parameters for the synthesizeable VHDL descriptions that followed.
{"title":"Simulation and modeling of a multicast ATM switch","authors":"Ajoy C. Siddabathuni, M. Balakrishnan","doi":"10.1109/ICVD.1999.745155","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745155","url":null,"abstract":"This article presents the core design of a high-speed [8 Gbps] nonblocking multicast ATM cell switch. The switch uses a self-routing ring of shift-registers to transfer cells from one port to another in a pipelined fashion resolving output contention and efficiently handling multicast cells. The \"ring\" architecture is advantageous from a VLSI standpoint. A novel feature of this design is an intelligent scheduler at the output buffers which provided a physical switch level support for QoS handling. This algorithm called helix-virtual-Q emulates a \"Weighted-Round-Robin Scheduling\" on a single-FIFO based output buffer. An object oriented high level simulation model provided key design parameters for the synthesizeable VHDL descriptions that followed.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115917569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745195
V. Krishna, N. Ranganathan, N. Vijaykrishnan
In this paper, we propose an energy efficient synthesis technique for datapath circuits. Specifically, we propose a time and resource constrained scheduling algorithm, (DFMVS), which utilizes the concept of Dynamic Frequency Clocking and Multiple Voltage Scaling. In the dynamic frequency scheme, all units are driven by a single clock line which changes at run time depending on the functional unit active at that time. Recently, the use of multiple voltages has been investigated in the context of energy minimization. DFMVS consists of two modules: Dynamic-freq-sched and Modify-sched. Based on the dynamic frequency scheme, Dynamic-freq-sched generates an initial schedule in which the control steps are clocked at different frequencies. Modify-sched incorporates a schedule modifier, that regroups the operations of the initial schedule such that multiple voltages can be used to reduce the energy consumption. The algorithm has been applied to various high level synthesis benchmark circuits under different time and resource constraints. The experimental results show that using three supply saving of 53.5% (with the time constraint of 2.0 times the critical path) is obtained as compared to using a uni-frequency clocking scheme with a single supply voltage.
{"title":"Energy efficient datapath synthesis using dynamic frequency clocking and multiple voltages","authors":"V. Krishna, N. Ranganathan, N. Vijaykrishnan","doi":"10.1109/ICVD.1999.745195","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745195","url":null,"abstract":"In this paper, we propose an energy efficient synthesis technique for datapath circuits. Specifically, we propose a time and resource constrained scheduling algorithm, (DFMVS), which utilizes the concept of Dynamic Frequency Clocking and Multiple Voltage Scaling. In the dynamic frequency scheme, all units are driven by a single clock line which changes at run time depending on the functional unit active at that time. Recently, the use of multiple voltages has been investigated in the context of energy minimization. DFMVS consists of two modules: Dynamic-freq-sched and Modify-sched. Based on the dynamic frequency scheme, Dynamic-freq-sched generates an initial schedule in which the control steps are clocked at different frequencies. Modify-sched incorporates a schedule modifier, that regroups the operations of the initial schedule such that multiple voltages can be used to reduce the energy consumption. The algorithm has been applied to various high level synthesis benchmark circuits under different time and resource constraints. The experimental results show that using three supply saving of 53.5% (with the time constraint of 2.0 times the critical path) is obtained as compared to using a uni-frequency clocking scheme with a single supply voltage.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125327439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745275
U. Narayanan, G. Stamoulis, R. Roy
Accuracy of gate level power estimation is very important because the decisions for power optimization are made based on estimation. In addition to the logical values of the primary inputs and the state of the circuit, there are a wide variety of other parameters that affect the switching activity of individual gates. Some of these factors include layout considerations such as transistor sizes, process considerations such as the supply voltage or parameters such as T/sub ox/, and finally timing considerations such as the gate delay model and the arrival time of the input signals. in this paper, we present empirical data that quantifies the relative impact of these factors on a wide variety of example circuits. The data indicates that if these factors are not taken into account, most gate level power estimates will be very inaccurate, and consequently most power estimation techniques will be of limited use.
{"title":"Characterizing individual gate power sensitivity in low power design","authors":"U. Narayanan, G. Stamoulis, R. Roy","doi":"10.1109/ICVD.1999.745275","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745275","url":null,"abstract":"Accuracy of gate level power estimation is very important because the decisions for power optimization are made based on estimation. In addition to the logical values of the primary inputs and the state of the circuit, there are a wide variety of other parameters that affect the switching activity of individual gates. Some of these factors include layout considerations such as transistor sizes, process considerations such as the supply voltage or parameters such as T/sub ox/, and finally timing considerations such as the gate delay model and the arrival time of the input signals. in this paper, we present empirical data that quantifies the relative impact of these factors on a wide variety of example circuits. The data indicates that if these factors are not taken into account, most gate level power estimates will be very inaccurate, and consequently most power estimation techniques will be of limited use.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132048460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745133
A. Kahng, G. Robins, Anish Singh, A. Zelikovsky
To reduce manufacturing variation due to chemical-mechanical polishing and to improve yield, layout must be made uniform with respect to density criteria. This is achieved by layout postprocessing to add fill geometries, either at the foundry or, for better convergence of performance verification flows, during layout synthesis. This paper proposes a new min-variation objective for the synthesis of fill geometries. Within the so-called fixed dissection regime (where density bounds are imposed on a predetermined set of windows in the layout), we exactly solve the min-variation objective using a linear programming formulation. We also state criteria for fill pattern synthesis, and discuss additional criteria that apply when fill, must be grounded for predictability of circuit performance. We believe that density control for CMP will become an important research topic in the VLSI design-manufacturing interface over the next several years.
{"title":"New and exact filling algorithms for layout density control","authors":"A. Kahng, G. Robins, Anish Singh, A. Zelikovsky","doi":"10.1109/ICVD.1999.745133","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745133","url":null,"abstract":"To reduce manufacturing variation due to chemical-mechanical polishing and to improve yield, layout must be made uniform with respect to density criteria. This is achieved by layout postprocessing to add fill geometries, either at the foundry or, for better convergence of performance verification flows, during layout synthesis. This paper proposes a new min-variation objective for the synthesis of fill geometries. Within the so-called fixed dissection regime (where density bounds are imposed on a predetermined set of windows in the layout), we exactly solve the min-variation objective using a linear programming formulation. We also state criteria for fill pattern synthesis, and discuss additional criteria that apply when fill, must be grounded for predictability of circuit performance. We believe that density control for CMP will become an important research topic in the VLSI design-manufacturing interface over the next several years.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129291710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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