Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032763
P. Devoge, H. Aziza, P. Lorenzini, P. Masson, F. Julien, A. Marzaki, A. Malherbe, J. Delalleau, T. Cabout, A. Régnier, S. Niel
An investigation of the effects of gate-to-drain/source overlap length and overlap asymmetry on the electrical and hot-carrier generation behavior is conducted on a medium-voltage (around 3 to 5 V) transistor in a 40 nm CMOS technology, using TCAD simulations calibrated with electrical measurements. The substrate current versus gate voltage is used to monitor the hot-carrier impact ionization rate. A novel numerical approach of decomposing the substrate current into its drain-side and source-side constituents is proposed, allowing to determine the junction where most of the impact ionization occurs depending on the geometrical and electrical parameters.
{"title":"Gate-to-drain/source overlap and asymmetry effects on hot-carrier generation","authors":"P. Devoge, H. Aziza, P. Lorenzini, P. Masson, F. Julien, A. Marzaki, A. Malherbe, J. Delalleau, T. Cabout, A. Régnier, S. Niel","doi":"10.1109/IIRW56459.2022.10032763","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032763","url":null,"abstract":"An investigation of the effects of gate-to-drain/source overlap length and overlap asymmetry on the electrical and hot-carrier generation behavior is conducted on a medium-voltage (around 3 to 5 V) transistor in a 40 nm CMOS technology, using TCAD simulations calibrated with electrical measurements. The substrate current versus gate voltage is used to monitor the hot-carrier impact ionization rate. A novel numerical approach of decomposing the substrate current into its drain-side and source-side constituents is proposed, allowing to determine the junction where most of the impact ionization occurs depending on the geometrical and electrical parameters.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114495247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032766
P. Rinaudo, A. Chasin, J. Franco, Z. Wu, N. Rassoul, R. Delhougne, B. Kaczer, I. Wolf, G. Kar
We studied the impact of gate and drain stress biases combination on IGZO based TFTs degradation targeting hot carrier regime. We show that typical signatures of this mechanism (e.g., saturation current degradation and SS increase) are not visible even at high drain biases, while a gate bias dependence only (BTI) is present in most of the degradation data.
{"title":"Degradation mapping of IGZO TFTs","authors":"P. Rinaudo, A. Chasin, J. Franco, Z. Wu, N. Rassoul, R. Delhougne, B. Kaczer, I. Wolf, G. Kar","doi":"10.1109/IIRW56459.2022.10032766","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032766","url":null,"abstract":"We studied the impact of gate and drain stress biases combination on IGZO based TFTs degradation targeting hot carrier regime. We show that typical signatures of this mechanism (e.g., saturation current degradation and SS increase) are not visible even at high drain biases, while a gate bias dependence only (BTI) is present in most of the degradation data.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116206725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032739
Minoru Watanabe
Recently, field programmable gate arrays (FPGAs) have come to be used widely for various applications. Nevertheless, the serial configuration function of FPGAs is well-known to be vulnerable to radiation in terms of total-ionizing-dose and soft-error tolerances. In order to increase the total-ionizing-dose tolerance of the configuration function of FPGAs, optically reconfigurable gate arrays that can support an optical parallel configuration have been developed. This paper presents an experiment to assess the soft-error tolerance of an optically reconfigurable gate array against neutron radiation.
{"title":"Cf-252 neutron soft-error tolerance of an optoelectronic field programmable gate array VLSI","authors":"Minoru Watanabe","doi":"10.1109/IIRW56459.2022.10032739","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032739","url":null,"abstract":"Recently, field programmable gate arrays (FPGAs) have come to be used widely for various applications. Nevertheless, the serial configuration function of FPGAs is well-known to be vulnerable to radiation in terms of total-ionizing-dose and soft-error tolerances. In order to increase the total-ionizing-dose tolerance of the configuration function of FPGAs, optically reconfigurable gate arrays that can support an optical parallel configuration have been developed. This paper presents an experiment to assess the soft-error tolerance of an optically reconfigurable gate array against neutron radiation.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124897179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/iirw56459.2022.10032754
B. Kaczer
{"title":"Discussion Group II – Circuit Reliability","authors":"B. Kaczer","doi":"10.1109/iirw56459.2022.10032754","DOIUrl":"https://doi.org/10.1109/iirw56459.2022.10032754","url":null,"abstract":"","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"253 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121321321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032759
Mathieu Sicre, X. Federspiel, D. Roy, Bastien Mamby, C. Coutier, F. Calmon
The reliability of Single-Photon Avalanche Diodes (SPADs) is addressed by measurement of Dark Count Rate (DCR) drift as a function of stress time (ΔDCR). The degradation mechanisms are analyzed performing stress-conditions at various temperatures, voltages, and irradiances. Measurement and simulation of current are performed to reinforce the degradation assumptions. Potential degradation locations are investigated by comparison of initial and post ageing DCR at different temperatures together with simulations covering defect position and number in the device. Different variations of manufacturing processes are also studied to further confirm defect positions. All the results have allowed identification of the plausible degradation mechanisms, including Hot-Carrier Degradation (HCD) and charge accumulation at the upper interface occurring in SPADs over a wide range of stress conditions.
{"title":"Identification of stress factors and degradation mechanisms inducing DCR drift in SPADs","authors":"Mathieu Sicre, X. Federspiel, D. Roy, Bastien Mamby, C. Coutier, F. Calmon","doi":"10.1109/IIRW56459.2022.10032759","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032759","url":null,"abstract":"The reliability of Single-Photon Avalanche Diodes (SPADs) is addressed by measurement of Dark Count Rate (DCR) drift as a function of stress time (ΔDCR). The degradation mechanisms are analyzed performing stress-conditions at various temperatures, voltages, and irradiances. Measurement and simulation of current are performed to reinforce the degradation assumptions. Potential degradation locations are investigated by comparison of initial and post ageing DCR at different temperatures together with simulations covering defect position and number in the device. Different variations of manufacturing processes are also studied to further confirm defect positions. All the results have allowed identification of the plausible degradation mechanisms, including Hot-Carrier Degradation (HCD) and charge accumulation at the upper interface occurring in SPADs over a wide range of stress conditions.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122165211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032746
L. Clark, Clifford Youngsciortino, Maximilian Siath, Leonardo Martinez, W. Brown, Shayena Khandker, Azad Derbedrosian, Sungho Kim, Ryan Melendez, S. Guertin, J. Yang-Scharlotta
Total ionizing dose (TID) has a significant effect on fully depleted silicon on insulator (FDSOI) transistors, which can be characterized the front gate threshold voltage (Vth) shift. We present transistor array test structure to characterize transistor TID. The resulting structure is one device under test (DUT) on a larger test integrated circuit (IC). The transistor array allows TID testing of a largenumber of devices in a packaged die that is amenable to gamma irradiation and other reliability studies, fabricated on a 22 nm FDSOI process. The approach is however, applicable to any fabrication process.
{"title":"A Transistor Array for Extracting Total Ionizing Dose Threshold Voltage Shifts","authors":"L. Clark, Clifford Youngsciortino, Maximilian Siath, Leonardo Martinez, W. Brown, Shayena Khandker, Azad Derbedrosian, Sungho Kim, Ryan Melendez, S. Guertin, J. Yang-Scharlotta","doi":"10.1109/IIRW56459.2022.10032746","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032746","url":null,"abstract":"Total ionizing dose (TID) has a significant effect on fully depleted silicon on insulator (FDSOI) transistors, which can be characterized the front gate threshold voltage (Vth) shift. We present transistor array test structure to characterize transistor TID. The resulting structure is one device under test (DUT) on a larger test integrated circuit (IC). The transistor array allows TID testing of a largenumber of devices in a packaged die that is amenable to gamma irradiation and other reliability studies, fabricated on a 22 nm FDSOI process. The approach is however, applicable to any fabrication process.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127746986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032762
Vishal Jha, M. Hoque, Mihilat Manahile, Joseph Rascon
Semiconductor companies using advanced technologies with FinFETs often rely on the foundry-provided SPICE model for reliability prediction. However, SPICE model has limitations in terms of its valid range of the operating conditions like voltage, temperature, etc. TCAD (technology computer aided design) simulation is not only critical for understanding semiconductor reliability physics, it can also bridge the gap to predict the device level reliability beyond the valid range of SPICE model. It is therefore, critical to calibrate the TCAD so that it represents silicon data reasonably well. In this paper, the calibration methodologies used to match TCAD with silicon-based SPICE model have been discussed for a 16nm FinFET technology. Self-heating effects (SHE) in FinFETs can cause severe reliability degradation. A calibrated TCAD deck has been used in this paper to study the SHE in FinFET into the operating conditions beyond the valid range of SPICE model.
{"title":"TCAD calibration for FinFET reliability predictions","authors":"Vishal Jha, M. Hoque, Mihilat Manahile, Joseph Rascon","doi":"10.1109/IIRW56459.2022.10032762","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032762","url":null,"abstract":"Semiconductor companies using advanced technologies with FinFETs often rely on the foundry-provided SPICE model for reliability prediction. However, SPICE model has limitations in terms of its valid range of the operating conditions like voltage, temperature, etc. TCAD (technology computer aided design) simulation is not only critical for understanding semiconductor reliability physics, it can also bridge the gap to predict the device level reliability beyond the valid range of SPICE model. It is therefore, critical to calibrate the TCAD so that it represents silicon data reasonably well. In this paper, the calibration methodologies used to match TCAD with silicon-based SPICE model have been discussed for a 16nm FinFET technology. Self-heating effects (SHE) in FinFETs can cause severe reliability degradation. A calibrated TCAD deck has been used in this paper to study the SHE in FinFET into the operating conditions beyond the valid range of SPICE model.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"450 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127609842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032767
L. Sheng, Wei Pan, Zdenek Axman
A full correlation of galvanic micro-pitting on AlCu pads has been for the first time revealed from FEOL buildups to IC chip. The presence of P-well was, in general, the primary factor of corrosion enhancement on specific pads. Therefore, the micro-pitting phenomenon should be more broadly examined well beyond the galvanic corrosion on individual pits. Furthermore, the electrons-limited electrochemical kinetics explain the pad-area dependence. This provides an excellent opportunity of design-for-reliability, where small pads can minimize the chance of micro-pitting occurrences.
{"title":"From FEOL Buildups to IC Chip: A Full Correlation of Galvanic Micro-Pitting on AlCu Pads","authors":"L. Sheng, Wei Pan, Zdenek Axman","doi":"10.1109/IIRW56459.2022.10032767","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032767","url":null,"abstract":"A full correlation of galvanic micro-pitting on AlCu pads has been for the first time revealed from FEOL buildups to IC chip. The presence of P-well was, in general, the primary factor of corrosion enhancement on specific pads. Therefore, the micro-pitting phenomenon should be more broadly examined well beyond the galvanic corrosion on individual pits. Furthermore, the electrons-limited electrochemical kinetics explain the pad-area dependence. This provides an excellent opportunity of design-for-reliability, where small pads can minimize the chance of micro-pitting occurrences.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125436013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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