Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032763
P. Devoge, H. Aziza, P. Lorenzini, P. Masson, F. Julien, A. Marzaki, A. Malherbe, J. Delalleau, T. Cabout, A. Régnier, S. Niel
An investigation of the effects of gate-to-drain/source overlap length and overlap asymmetry on the electrical and hot-carrier generation behavior is conducted on a medium-voltage (around 3 to 5 V) transistor in a 40 nm CMOS technology, using TCAD simulations calibrated with electrical measurements. The substrate current versus gate voltage is used to monitor the hot-carrier impact ionization rate. A novel numerical approach of decomposing the substrate current into its drain-side and source-side constituents is proposed, allowing to determine the junction where most of the impact ionization occurs depending on the geometrical and electrical parameters.
{"title":"Gate-to-drain/source overlap and asymmetry effects on hot-carrier generation","authors":"P. Devoge, H. Aziza, P. Lorenzini, P. Masson, F. Julien, A. Marzaki, A. Malherbe, J. Delalleau, T. Cabout, A. Régnier, S. Niel","doi":"10.1109/IIRW56459.2022.10032763","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032763","url":null,"abstract":"An investigation of the effects of gate-to-drain/source overlap length and overlap asymmetry on the electrical and hot-carrier generation behavior is conducted on a medium-voltage (around 3 to 5 V) transistor in a 40 nm CMOS technology, using TCAD simulations calibrated with electrical measurements. The substrate current versus gate voltage is used to monitor the hot-carrier impact ionization rate. A novel numerical approach of decomposing the substrate current into its drain-side and source-side constituents is proposed, allowing to determine the junction where most of the impact ionization occurs depending on the geometrical and electrical parameters.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114495247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032766
P. Rinaudo, A. Chasin, J. Franco, Z. Wu, N. Rassoul, R. Delhougne, B. Kaczer, I. Wolf, G. Kar
We studied the impact of gate and drain stress biases combination on IGZO based TFTs degradation targeting hot carrier regime. We show that typical signatures of this mechanism (e.g., saturation current degradation and SS increase) are not visible even at high drain biases, while a gate bias dependence only (BTI) is present in most of the degradation data.
{"title":"Degradation mapping of IGZO TFTs","authors":"P. Rinaudo, A. Chasin, J. Franco, Z. Wu, N. Rassoul, R. Delhougne, B. Kaczer, I. Wolf, G. Kar","doi":"10.1109/IIRW56459.2022.10032766","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032766","url":null,"abstract":"We studied the impact of gate and drain stress biases combination on IGZO based TFTs degradation targeting hot carrier regime. We show that typical signatures of this mechanism (e.g., saturation current degradation and SS increase) are not visible even at high drain biases, while a gate bias dependence only (BTI) is present in most of the degradation data.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116206725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032739
Minoru Watanabe
Recently, field programmable gate arrays (FPGAs) have come to be used widely for various applications. Nevertheless, the serial configuration function of FPGAs is well-known to be vulnerable to radiation in terms of total-ionizing-dose and soft-error tolerances. In order to increase the total-ionizing-dose tolerance of the configuration function of FPGAs, optically reconfigurable gate arrays that can support an optical parallel configuration have been developed. This paper presents an experiment to assess the soft-error tolerance of an optically reconfigurable gate array against neutron radiation.
{"title":"Cf-252 neutron soft-error tolerance of an optoelectronic field programmable gate array VLSI","authors":"Minoru Watanabe","doi":"10.1109/IIRW56459.2022.10032739","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032739","url":null,"abstract":"Recently, field programmable gate arrays (FPGAs) have come to be used widely for various applications. Nevertheless, the serial configuration function of FPGAs is well-known to be vulnerable to radiation in terms of total-ionizing-dose and soft-error tolerances. In order to increase the total-ionizing-dose tolerance of the configuration function of FPGAs, optically reconfigurable gate arrays that can support an optical parallel configuration have been developed. This paper presents an experiment to assess the soft-error tolerance of an optically reconfigurable gate array against neutron radiation.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124897179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/iirw56459.2022.10032754
B. Kaczer
{"title":"Discussion Group II – Circuit Reliability","authors":"B. Kaczer","doi":"10.1109/iirw56459.2022.10032754","DOIUrl":"https://doi.org/10.1109/iirw56459.2022.10032754","url":null,"abstract":"","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"253 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121321321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032759
Mathieu Sicre, X. Federspiel, D. Roy, Bastien Mamby, C. Coutier, F. Calmon
The reliability of Single-Photon Avalanche Diodes (SPADs) is addressed by measurement of Dark Count Rate (DCR) drift as a function of stress time (ΔDCR). The degradation mechanisms are analyzed performing stress-conditions at various temperatures, voltages, and irradiances. Measurement and simulation of current are performed to reinforce the degradation assumptions. Potential degradation locations are investigated by comparison of initial and post ageing DCR at different temperatures together with simulations covering defect position and number in the device. Different variations of manufacturing processes are also studied to further confirm defect positions. All the results have allowed identification of the plausible degradation mechanisms, including Hot-Carrier Degradation (HCD) and charge accumulation at the upper interface occurring in SPADs over a wide range of stress conditions.
{"title":"Identification of stress factors and degradation mechanisms inducing DCR drift in SPADs","authors":"Mathieu Sicre, X. Federspiel, D. Roy, Bastien Mamby, C. Coutier, F. Calmon","doi":"10.1109/IIRW56459.2022.10032759","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032759","url":null,"abstract":"The reliability of Single-Photon Avalanche Diodes (SPADs) is addressed by measurement of Dark Count Rate (DCR) drift as a function of stress time (ΔDCR). The degradation mechanisms are analyzed performing stress-conditions at various temperatures, voltages, and irradiances. Measurement and simulation of current are performed to reinforce the degradation assumptions. Potential degradation locations are investigated by comparison of initial and post ageing DCR at different temperatures together with simulations covering defect position and number in the device. Different variations of manufacturing processes are also studied to further confirm defect positions. All the results have allowed identification of the plausible degradation mechanisms, including Hot-Carrier Degradation (HCD) and charge accumulation at the upper interface occurring in SPADs over a wide range of stress conditions.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122165211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032746
L. Clark, Clifford Youngsciortino, Maximilian Siath, Leonardo Martinez, W. Brown, Shayena Khandker, Azad Derbedrosian, Sungho Kim, Ryan Melendez, S. Guertin, J. Yang-Scharlotta
Total ionizing dose (TID) has a significant effect on fully depleted silicon on insulator (FDSOI) transistors, which can be characterized the front gate threshold voltage (Vth) shift. We present transistor array test structure to characterize transistor TID. The resulting structure is one device under test (DUT) on a larger test integrated circuit (IC). The transistor array allows TID testing of a largenumber of devices in a packaged die that is amenable to gamma irradiation and other reliability studies, fabricated on a 22 nm FDSOI process. The approach is however, applicable to any fabrication process.
{"title":"A Transistor Array for Extracting Total Ionizing Dose Threshold Voltage Shifts","authors":"L. Clark, Clifford Youngsciortino, Maximilian Siath, Leonardo Martinez, W. Brown, Shayena Khandker, Azad Derbedrosian, Sungho Kim, Ryan Melendez, S. Guertin, J. Yang-Scharlotta","doi":"10.1109/IIRW56459.2022.10032746","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032746","url":null,"abstract":"Total ionizing dose (TID) has a significant effect on fully depleted silicon on insulator (FDSOI) transistors, which can be characterized the front gate threshold voltage (Vth) shift. We present transistor array test structure to characterize transistor TID. The resulting structure is one device under test (DUT) on a larger test integrated circuit (IC). The transistor array allows TID testing of a largenumber of devices in a packaged die that is amenable to gamma irradiation and other reliability studies, fabricated on a 22 nm FDSOI process. The approach is however, applicable to any fabrication process.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127746986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032752
A. Belmonte, Asir Intisar Khan, B. Kaczer, M. Siddabathula
Tutorial 1: Memory Technology: Reliability Challenges and Future PerspectivesAbstract: Memory technologies occupy a huge share of the semiconductor market. Despite a large plethora of memory device concepts proposed over the years, only a restricted group of them has achieved large-scale production. Reliability is one of the main aspects limiting the adoption of a memory technology by the semiconductor industry. This tutorial aims at outlining the main reliability characteristics of memory devices and the characterization techniques to assess them. Representative case studies, namely RRAM and DRAM, are provided, to review the challenges to be overcome before a memory technology is widely accepted by the industry, and to describe how the causes of reliability failure are identified and mitigated. As the pursuit of innovative memory devices and architectures is relentless and fast-paced, this tutorial also provides future perspectives on memory technology and the related reliability challenges.Tutorial 2: Reliability of Energy-Efficient Phase Change Memory Based on Novel Superlattices and NanocompositesAbstract: Today’s computing systems are reaching fundamental limits with conventional materials like silicon, and with conventional layouts that separate memory and computing. To overcome these challenges, phase change memory (PCM) technology based on chalcogenides like Ge2Sb2Te5 (GST225) hold great promise for both data storage and neuromorphic computing. However, using conventional phase change materials, PCM operation requires large power consumption and suffers from resistance drift, limiting its potential for neuro-inspired and energy-efficient data storage. In this tutorial, we will address some of these challenges in PCM devices using novel phase change nanocomposite Ge4Sb6Te7 (GST467) and GST based phase-change superlattices. We will discuss the operation of energy-efficient and neuro-inspired PCM devices demonstrating gradual change of resistance states, low power switching, and multilevel operation with low resistance drift. We will also focus on the fundamental correlation between superlattice material characteristics and PCM device performance, important to ensure reliability and robustness of such technology for low power and brain-inspired computing.Tutorial 3: Brief Introduction to Device and Circuit ReliabilityAbstract: After a brief review of selected reliability basics, we discuss the main degradation mechanisms occurring in Field-Effect Transistors (FETs). These mechanisms include SILC (Stress Induced Leakage Current), TDDB (Time-Dependent Dielectric Breakdown), BTI (Bias Temperature Instability), RTN (Random Telegraph Noise), and HCD (Hot Carrier Degradation) with the accompanying Self-Heating (SHE) and are linked with the underlying properties of defects. The effects of Mechanical Stress are also briefly reviewed. We then show that these defects play the essential role in many emerging technologies and applications, including Cry
{"title":"Summary of Tutorials","authors":"A. Belmonte, Asir Intisar Khan, B. Kaczer, M. Siddabathula","doi":"10.1109/IIRW56459.2022.10032752","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032752","url":null,"abstract":"Tutorial 1: Memory Technology: Reliability Challenges and Future PerspectivesAbstract: Memory technologies occupy a huge share of the semiconductor market. Despite a large plethora of memory device concepts proposed over the years, only a restricted group of them has achieved large-scale production. Reliability is one of the main aspects limiting the adoption of a memory technology by the semiconductor industry. This tutorial aims at outlining the main reliability characteristics of memory devices and the characterization techniques to assess them. Representative case studies, namely RRAM and DRAM, are provided, to review the challenges to be overcome before a memory technology is widely accepted by the industry, and to describe how the causes of reliability failure are identified and mitigated. As the pursuit of innovative memory devices and architectures is relentless and fast-paced, this tutorial also provides future perspectives on memory technology and the related reliability challenges.Tutorial 2: Reliability of Energy-Efficient Phase Change Memory Based on Novel Superlattices and NanocompositesAbstract: Today’s computing systems are reaching fundamental limits with conventional materials like silicon, and with conventional layouts that separate memory and computing. To overcome these challenges, phase change memory (PCM) technology based on chalcogenides like Ge2Sb2Te5 (GST225) hold great promise for both data storage and neuromorphic computing. However, using conventional phase change materials, PCM operation requires large power consumption and suffers from resistance drift, limiting its potential for neuro-inspired and energy-efficient data storage. In this tutorial, we will address some of these challenges in PCM devices using novel phase change nanocomposite Ge4Sb6Te7 (GST467) and GST based phase-change superlattices. We will discuss the operation of energy-efficient and neuro-inspired PCM devices demonstrating gradual change of resistance states, low power switching, and multilevel operation with low resistance drift. We will also focus on the fundamental correlation between superlattice material characteristics and PCM device performance, important to ensure reliability and robustness of such technology for low power and brain-inspired computing.Tutorial 3: Brief Introduction to Device and Circuit ReliabilityAbstract: After a brief review of selected reliability basics, we discuss the main degradation mechanisms occurring in Field-Effect Transistors (FETs). These mechanisms include SILC (Stress Induced Leakage Current), TDDB (Time-Dependent Dielectric Breakdown), BTI (Bias Temperature Instability), RTN (Random Telegraph Noise), and HCD (Hot Carrier Degradation) with the accompanying Self-Heating (SHE) and are linked with the underlying properties of defects. The effects of Mechanical Stress are also briefly reviewed. We then show that these defects play the essential role in many emerging technologies and applications, including Cry","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"121 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113990496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032767
L. Sheng, Wei Pan, Zdenek Axman
A full correlation of galvanic micro-pitting on AlCu pads has been for the first time revealed from FEOL buildups to IC chip. The presence of P-well was, in general, the primary factor of corrosion enhancement on specific pads. Therefore, the micro-pitting phenomenon should be more broadly examined well beyond the galvanic corrosion on individual pits. Furthermore, the electrons-limited electrochemical kinetics explain the pad-area dependence. This provides an excellent opportunity of design-for-reliability, where small pads can minimize the chance of micro-pitting occurrences.
{"title":"From FEOL Buildups to IC Chip: A Full Correlation of Galvanic Micro-Pitting on AlCu Pads","authors":"L. Sheng, Wei Pan, Zdenek Axman","doi":"10.1109/IIRW56459.2022.10032767","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032767","url":null,"abstract":"A full correlation of galvanic micro-pitting on AlCu pads has been for the first time revealed from FEOL buildups to IC chip. The presence of P-well was, in general, the primary factor of corrosion enhancement on specific pads. Therefore, the micro-pitting phenomenon should be more broadly examined well beyond the galvanic corrosion on individual pits. Furthermore, the electrons-limited electrochemical kinetics explain the pad-area dependence. This provides an excellent opportunity of design-for-reliability, where small pads can minimize the chance of micro-pitting occurrences.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125436013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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