Pub Date : 2021-12-07DOI: 10.1109/OJNANO.2021.3133213
Akash Jain;Heman Vaghasiya;Jai Narayan Tripathi
In the era of advanced nanotechnology where billions of transistors are fabricated in a single chip, high-speed operations are challenging due to packaging related issues. In High-Speed Very Large Scale Integration (VLSI) systems, decoupling capacitors are essentially used in power delivery networks to reduce power supply noise and to maintain a low impedance of the power delivery networks. In this paper, the cumulative impedance of a power delivery network is reduced below the target impedance by using state-of-the-art metaheuristic algorithms to choose and place decoupling capacitors optimally. A Matrix-based Evolutionary Computing (MEC) approach is used for efficient usage of metaheuristic algorithms. Two case studies are presented on a practical system to demonstrate the proposed approach. A comparative analysis of the performance of state-of-the-art metaheuristics is presented with the insights of practical implementation. The consistency of results in both the case studies confirms the validity of the proposed appraoch.
{"title":"Efficient Selection and Placement of In-Package Decoupling Capacitors Using Matrix-Based Evolutionary Computation","authors":"Akash Jain;Heman Vaghasiya;Jai Narayan Tripathi","doi":"10.1109/OJNANO.2021.3133213","DOIUrl":"https://doi.org/10.1109/OJNANO.2021.3133213","url":null,"abstract":"In the era of advanced nanotechnology where billions of transistors are fabricated in a single chip, high-speed operations are challenging due to packaging related issues. In High-Speed Very Large Scale Integration (VLSI) systems, decoupling capacitors are essentially used in power delivery networks to reduce power supply noise and to maintain a low impedance of the power delivery networks. In this paper, the cumulative impedance of a power delivery network is reduced below the target impedance by using state-of-the-art metaheuristic algorithms to choose and place decoupling capacitors optimally. A Matrix-based Evolutionary Computing (MEC) approach is used for efficient usage of metaheuristic algorithms. Two case studies are presented on a practical system to demonstrate the proposed approach. A comparative analysis of the performance of state-of-the-art metaheuristics is presented with the insights of practical implementation. The consistency of results in both the case studies confirms the validity of the proposed appraoch.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"2 ","pages":"191-200"},"PeriodicalIF":1.7,"publicationDate":"2021-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782713/9316416/09640572.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3500653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-07DOI: 10.1109/OJNANO.2021.3133325
Jai Narayan Tripathi;Heman Vaghasiya;Dinesh Junjariya;Aksh Chordia
Interconnects are essential components of any electronic system. Their design, modeling and optimization are becoming complex and computationally expensive with the evolution of semiconductor technology as the devices of nanometer dimensions are being used. In high-speed applications, system level simulations are needed to ensure the robustness of a system in terms of signal and power quality. The simulations are becoming very expensive because of the large dimensional systems and their full-wave models. Machine learning techniques can be used as computationally efficient alternatives in the design cycle of the interconnects. This paper presents a review of the applications of machine learning techniques for design, optimization and analysis of interconnects in high-speed electronic systems. A holistic discussion is presented, including the basics of interconnects, their impact on the system performance, popular machine learning techniques and their applications related to the interconnects. The performance evaluation, optimization and variability analysis of interconnects are discussed in detail. Future scope and overlook that are presented in the literature are also discussed.
{"title":"Machine Learning Techniques for Modeling and Performance Analysis of Interconnects","authors":"Jai Narayan Tripathi;Heman Vaghasiya;Dinesh Junjariya;Aksh Chordia","doi":"10.1109/OJNANO.2021.3133325","DOIUrl":"https://doi.org/10.1109/OJNANO.2021.3133325","url":null,"abstract":"Interconnects are essential components of any electronic system. Their design, modeling and optimization are becoming complex and computationally expensive with the evolution of semiconductor technology as the devices of nanometer dimensions are being used. In high-speed applications, system level simulations are needed to ensure the robustness of a system in terms of signal and power quality. The simulations are becoming very expensive because of the large dimensional systems and their full-wave models. Machine learning techniques can be used as computationally efficient alternatives in the design cycle of the interconnects. This paper presents a review of the applications of machine learning techniques for design, optimization and analysis of interconnects in high-speed electronic systems. A holistic discussion is presented, including the basics of interconnects, their impact on the system performance, popular machine learning techniques and their applications related to the interconnects. The performance evaluation, optimization and variability analysis of interconnects are discussed in detail. Future scope and overlook that are presented in the literature are also discussed.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"2 ","pages":"178-190"},"PeriodicalIF":1.7,"publicationDate":"2021-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782713/9316416/09640578.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3500094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-02DOI: 10.1109/OJNANO.2021.3131653
Alvin Chao-Yu Chen;Yun-Wen Tong;Chih-Hao Chiu;Kin Fong Lei
Periosteum-derived progenitor cells (PDPCs) are highly promising cell sources for bone fracture healing because of their stem cell-like multipotency to undergo osteogenesis and chondrogenesis. Both externally physical stimulation and internally biochemical signal were reported to enhance osteogenic differentiation of bone tissues. Electric stimulation (ES) could trigger the differentiation of stem cells, like mesenchymal stem cells (MSCs) and adipose-derived stem cells (ADSCs). But the effect is still unclear on PDPCs. In order to investigate the differentiation ability of PDPCs co-induced by ES and ADSCs, a biomimetic 3-dimensional (3D) co-culture system was developed for providing ES and co-culturing with ADSCs. Gene expression was studied after a 3-day culture course. From our results, osteogenic differentiation of PDPCs was significantly activated under the ES of 0.7 V/cm, 80 kHz, and 3 hrs/day. Moreover, co-culturing with ADSCs during the ES treatment was found to have synergistic effect of osteogenic differentiation. In addition, chondrogenic differentiation was shown when the PDPCs were cultured for a long culture course. In summary, osteogenic differentiation of PDPCs was shown to be co-induced by ES and ADSCs. This study provides significant insights of the PDPC therapy for bone tissue regeneration.
{"title":"Osteogenic Effect of Rabbit Periosteum-Derived Precursor Cells Co-Induced by Electric Stimulation and Adipose-Derived Stem Cells in a 3D Co-Culture System","authors":"Alvin Chao-Yu Chen;Yun-Wen Tong;Chih-Hao Chiu;Kin Fong Lei","doi":"10.1109/OJNANO.2021.3131653","DOIUrl":"https://doi.org/10.1109/OJNANO.2021.3131653","url":null,"abstract":"Periosteum-derived progenitor cells (PDPCs) are highly promising cell sources for bone fracture healing because of their stem cell-like multipotency to undergo osteogenesis and chondrogenesis. Both externally physical stimulation and internally biochemical signal were reported to enhance osteogenic differentiation of bone tissues. Electric stimulation (ES) could trigger the differentiation of stem cells, like mesenchymal stem cells (MSCs) and adipose-derived stem cells (ADSCs). But the effect is still unclear on PDPCs. In order to investigate the differentiation ability of PDPCs co-induced by ES and ADSCs, a biomimetic 3-dimensional (3D) co-culture system was developed for providing ES and co-culturing with ADSCs. Gene expression was studied after a 3-day culture course. From our results, osteogenic differentiation of PDPCs was significantly activated under the ES of 0.7 V/cm, 80 kHz, and 3 hrs/day. Moreover, co-culturing with ADSCs during the ES treatment was found to have synergistic effect of osteogenic differentiation. In addition, chondrogenic differentiation was shown when the PDPCs were cultured for a long culture course. In summary, osteogenic differentiation of PDPCs was shown to be co-induced by ES and ADSCs. This study provides significant insights of the PDPC therapy for bone tissue regeneration.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"2 ","pages":"153-160"},"PeriodicalIF":1.7,"publicationDate":"2021-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782713/9316416/09633183.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3482739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Femtosecond laser processing is fast becoming a pervasive method for fabricating micro/nanostructures because it can be used to produce micro/nanostructures on myriads of materials with high precision and resolution, requires little control over environmental conditions, and is simple to implement. Here, we review recent developments in the use of femtosecond lasers for the fabrication of micro/nanostructures through ablation and two-photon polymerization (TPP). Moreover, the applications of some of the fabricated micro/nanostructures are also discussed. We highlight the advantages of femtosecond laser processing by explaining the underlying principles of laser ablation and TPP. We also show the use of this method to fabricate new devices with outstanding performance in several application realm, such as sensors, optical devices, microfluidic chips, and soft robotics.
{"title":"Recent Advances in Femtosecond Laser Fabrication: From Structures to Applications","authors":"Yangdong Wen;Haibo Yu;Yuzhao Zhang;Ye Qiu;Peiwen Li;Xiaoduo Wang;Boliang Jia;Lianqing Liu;Wen Jung Li","doi":"10.1109/OJNANO.2021.3131818","DOIUrl":"https://doi.org/10.1109/OJNANO.2021.3131818","url":null,"abstract":"Femtosecond laser processing is fast becoming a pervasive method for fabricating micro/nanostructures because it can be used to produce micro/nanostructures on myriads of materials with high precision and resolution, requires little control over environmental conditions, and is simple to implement. Here, we review recent developments in the use of femtosecond lasers for the fabrication of micro/nanostructures through ablation and two-photon polymerization (TPP). Moreover, the applications of some of the fabricated micro/nanostructures are also discussed. We highlight the advantages of femtosecond laser processing by explaining the underlying principles of laser ablation and TPP. We also show the use of this method to fabricate new devices with outstanding performance in several application realm, such as sensors, optical devices, microfluidic chips, and soft robotics.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"2 ","pages":"161-177"},"PeriodicalIF":1.7,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782713/9316416/09632350.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3482578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The phonon transport in the lateral direction for gap-controlled Si nanopillar (NP) /SiGe interlayer composite materials was investigated to eliminate heat generation in the channel area for advanced MOS transistors. The gap-controlled Si NP/SiGe composite layer showed 1/250 times lower thermal conductivity than Si bulk. Then, the phonon transport behavior in lateral direction could be predicted by the combination between the 3-omega measurement method for thermal conductivity and the Landauer approach for phonon transport in Si NP/Si 0.7 Ge 0.3 interlayer composite structure. We found that the NP structure could regulate the phonon transport in the lateral direction by changing the NP gaps by preventing the phonon transportation from the drain region and the potential heat generation. As such, this structure achieves the first step toward phonon transport management in the same electron transportation direction of planar-type MOSFETs and represents a promising solution to heat generation for advanced CMOS devices.
{"title":"Management of Phonon Transport in Lateral Direction for Gap-Controlled Si Nanopillar/SiGe Interlayer Composite Materials","authors":"Daisuke Ohori;Min-Hui Chuang;Asahi Sato;Sou Takeuchi;Masayuki Murata;Atsushi Yamamoto;Ming-Yi Lee;Kazuhiko Endo;Yiming Li;Jenn-Hwan Tarng;Yao-Jen Lee;Seiji Samukawa","doi":"10.1109/OJNANO.2021.3131165","DOIUrl":"https://doi.org/10.1109/OJNANO.2021.3131165","url":null,"abstract":"The phonon transport in the lateral direction for gap-controlled Si nanopillar (NP) /SiGe interlayer composite materials was investigated to eliminate heat generation in the channel area for advanced MOS transistors. The gap-controlled Si NP/SiGe composite layer showed 1/250 times lower thermal conductivity than Si bulk. Then, the phonon transport behavior in lateral direction could be predicted by the combination between the 3-omega measurement method for thermal conductivity and the Landauer approach for phonon transport in Si NP/Si\u0000<sub>0.7</sub>\u0000Ge\u0000<sub>0.3</sub>\u0000 interlayer composite structure. We found that the NP structure could regulate the phonon transport in the lateral direction by changing the NP gaps by preventing the phonon transportation from the drain region and the potential heat generation. As such, this structure achieves the first step toward phonon transport management in the same electron transportation direction of planar-type MOSFETs and represents a promising solution to heat generation for advanced CMOS devices.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"2 ","pages":"148-152"},"PeriodicalIF":1.7,"publicationDate":"2021-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782713/9316416/09628021.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3482736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-23DOI: 10.1109/OJNANO.2021.3129858
Mingliang Zhang;Xiaokuo Yang;Huanqing Cui;Zhigang Gu;Zhenglin Han
The quantum-dot cellular automata (QCA) present great promising advantages for emerging nano logic circuits. However, feedback design in QCA sequential circuit is often a big problem. Especially in line feedback shift registers (LFSR), each feedback loop consists of at least a modulo-2 adder and a trigger unit, which is hard to implement using the conventional methods. Given the importance of LFSR in communication systems, a design methodology with QCA is proposed in this work. At first, a new structure is presented to be used in every single feedback LFSR since it can make the feedback loop consume only one clock cycle of delay. Subsequently, quantitative criteria are presented to judge whether any multi-feedback LFSR can be directly designed using the proposed structure. LFSR that cannot satisfy the criteria are supposed to be transformed to their equivalent forms. We verify any LFSR can be transformed to the type of single feedback, according to the theorem of searching the monic and irreducible polynomials over Galois field GF (2). The step-by-step method of transforming multi-feedback into single feedback is given on the consideration of all kinds of cases. Further, two other simple transforming methods are presented to cope with the exponential growth of clock delay in the multi-to-single transforming method. The most remarkable advantage of this series of methods is to keep from introducing undesired bits into the payload data flowing in the sequential circuits.
{"title":"A Design Methodology of Line Feedback Shift Registers With Quantum Cellular Automata","authors":"Mingliang Zhang;Xiaokuo Yang;Huanqing Cui;Zhigang Gu;Zhenglin Han","doi":"10.1109/OJNANO.2021.3129858","DOIUrl":"https://doi.org/10.1109/OJNANO.2021.3129858","url":null,"abstract":"The quantum-dot cellular automata (QCA) present great promising advantages for emerging nano logic circuits. However, feedback design in QCA sequential circuit is often a big problem. Especially in line feedback shift registers (LFSR), each feedback loop consists of at least a modulo-2 adder and a trigger unit, which is hard to implement using the conventional methods. Given the importance of LFSR in communication systems, a design methodology with QCA is proposed in this work. At first, a new structure is presented to be used in every single feedback LFSR since it can make the feedback loop consume only one clock cycle of delay. Subsequently, quantitative criteria are presented to judge whether any multi-feedback LFSR can be directly designed using the proposed structure. LFSR that cannot satisfy the criteria are supposed to be transformed to their equivalent forms. We verify any LFSR can be transformed to the type of single feedback, according to the theorem of searching the monic and irreducible polynomials over Galois field GF (2). The step-by-step method of transforming multi-feedback into single feedback is given on the consideration of all kinds of cases. Further, two other simple transforming methods are presented to cope with the exponential growth of clock delay in the multi-to-single transforming method. The most remarkable advantage of this series of methods is to keep from introducing undesired bits into the payload data flowing in the sequential circuits.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"2 ","pages":"129-139"},"PeriodicalIF":1.7,"publicationDate":"2021-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782713/9316416/09625794.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3515466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-23DOI: 10.1109/OJNANO.2021.3130043
Hui Lv;Huiwen Li;Qiang Zhang
The realization of molecular logic circuit is inseparable from the design and analysis of catalytic reaction chain, and the DNA catalytic gate plays an important role in it. Discuss the nature of the solution to DNA catalytic reaction system, using Khasminskii's periodicity and Lyapunov analysis methods to obtain the existence of non-trivial positive periodic solutions of the system, and the solution is globally attractive. The existence of the solution indicates that according to the mathematical model established by the DNA catalytic reaction system, the system may reach the expected concentration value of an ideal state and obtain better reaction data, which provides a theoretical basis for the realization of the DNA catalytic gate function. Numerical simulation results show that under the influence of random disturbance and periodic parameters, the solution to the random DNA catalytic reaction system exists and is globally attractive, which also reflects that the DNA catalytic reaction system can reach an ideal reaction state. The solution to the DNA catalytic system with random disturbance will converge on a certain value and oscillate periodically between the solution to the deterministic system.
{"title":"Analysis of Periodic Solution of DNA Catalytic Reaction Model With Random Disturbance","authors":"Hui Lv;Huiwen Li;Qiang Zhang","doi":"10.1109/OJNANO.2021.3130043","DOIUrl":"https://doi.org/10.1109/OJNANO.2021.3130043","url":null,"abstract":"The realization of molecular logic circuit is inseparable from the design and analysis of catalytic reaction chain, and the DNA catalytic gate plays an important role in it. Discuss the nature of the solution to DNA catalytic reaction system, using Khasminskii's periodicity and Lyapunov analysis methods to obtain the existence of non-trivial positive periodic solutions of the system, and the solution is globally attractive. The existence of the solution indicates that according to the mathematical model established by the DNA catalytic reaction system, the system may reach the expected concentration value of an ideal state and obtain better reaction data, which provides a theoretical basis for the realization of the DNA catalytic gate function. Numerical simulation results show that under the influence of random disturbance and periodic parameters, the solution to the random DNA catalytic reaction system exists and is globally attractive, which also reflects that the DNA catalytic reaction system can reach an ideal reaction state. The solution to the DNA catalytic system with random disturbance will converge on a certain value and oscillate periodically between the solution to the deterministic system.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"2 ","pages":"140-147"},"PeriodicalIF":1.7,"publicationDate":"2021-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782713/9316416/09625705.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3515470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In recent years, the aggressive downscaling of electronic components has led to highly dense and power-hungry devices. With Moore’s law expected to soon reach its physical limit, there is a pressing need to significantly improve the efficiency and performance not only of nanodevices, but also of the embedding environment in which such nanodevices are integrated. In this context, key for improving the performance and for reducing both system cost and size is electronics packaging. However, electronics packaging at the nanoscale (i.e., nanopackaging) is currently facing several technological challenges, as in such scale conventional materials present intrinsic physical limitations. To address this, it becomes necessary to replace these latter with novel alternatives, such as low-dimensional carbon-based nanomaterials. Carbon nanotubes (CNTs) and graphene (materials with 1D and 2D dimensionality, respectively) have the potential to be successfully integrated into traditional silicon-based electronics as well as with beyond-silicon electronics, and their unique electrical, thermal, mechanical, and optical properties could be key enablers for significant performance improvements. In this short review we describe why these nanomaterials are very promising for electronics nanopackaging, and we outline the key application areas, mainly interconnects, thermal management, and flexible devices.
{"title":"Graphene and Carbon Nanotubes for Electronics Nanopackaging","authors":"Gabriele Boschetto;Stefania Carapezzi;Aida Todri-Sanial","doi":"10.1109/OJNANO.2021.3127652","DOIUrl":"https://doi.org/10.1109/OJNANO.2021.3127652","url":null,"abstract":"In recent years, the aggressive downscaling of electronic components has led to highly dense and power-hungry devices. With Moore’s law expected to soon reach its physical limit, there is a pressing need to significantly improve the efficiency and performance not only of nanodevices, but also of the embedding environment in which such nanodevices are integrated. In this context, key for improving the performance and for reducing both system cost and size is electronics packaging. However, electronics packaging at the nanoscale (i.e., nanopackaging) is currently facing several technological challenges, as in such scale conventional materials present intrinsic physical limitations. To address this, it becomes necessary to replace these latter with novel alternatives, such as low-dimensional carbon-based nanomaterials. Carbon nanotubes (CNTs) and graphene (materials with 1D and 2D dimensionality, respectively) have the potential to be successfully integrated into traditional silicon-based electronics as well as with beyond-silicon electronics, and their unique electrical, thermal, mechanical, and optical properties could be key enablers for significant performance improvements. In this short review we describe why these nanomaterials are very promising for electronics nanopackaging, and we outline the key application areas, mainly interconnects, thermal management, and flexible devices.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"2 ","pages":"120-128"},"PeriodicalIF":1.7,"publicationDate":"2021-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782713/9316416/09613740.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3515458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper proposes novel solutions to improve the signal and thermal integrity of crossbar arrays of Resistive Random-Access Memories, that are among the most promising technologies for the 3D monolithic integration. These structures suffer from electrothermal issues, due to the heat generated by the power dissipation during the write process. This paper explores novel solutions based on new architectures and materials, for managing the issues related to the voltage drop along the interconnects and to thermal crosstalk between memory cells. The analyzed memristor is the 1 Diode - 1 Resistor memory. The two architectural solutions are given by a reverse architecture and a complementary resistive switching one. Compared to conventional architectures, both of them are also reducing the number of layers where the bias is applied. The electrothermal performance of these new structures is compared to that of the reference one, for a case-study given by a 4 × 4 × 4 array. To this end, a full-3D numerical Multiphysics model is implemented and successfully compared against other models in literature. The possibility of changing the interconnect materials is also analyzed. The results of this performance analysis clearly show the benefits of moving to these novel architectures, together with the choice of new materials.
{"title":"Performance Enhancement of Large Crossbar Resistive Memories With Complementary and 1D1R-1R1D RRAM Structures","authors":"Khitem Lahbacha;Fakhreddine Zayer;Hamdi Belgacem;Wael Dghais;Antonio Maffucci","doi":"10.1109/OJNANO.2021.3124846","DOIUrl":"https://doi.org/10.1109/OJNANO.2021.3124846","url":null,"abstract":"The paper proposes novel solutions to improve the signal and thermal integrity of crossbar arrays of Resistive Random-Access Memories, that are among the most promising technologies for the 3D monolithic integration. These structures suffer from electrothermal issues, due to the heat generated by the power dissipation during the write process. This paper explores novel solutions based on new architectures and materials, for managing the issues related to the voltage drop along the interconnects and to thermal crosstalk between memory cells. The analyzed memristor is the 1 Diode - 1 Resistor memory. The two architectural solutions are given by a reverse architecture and a complementary resistive switching one. Compared to conventional architectures, both of them are also reducing the number of layers where the bias is applied. The electrothermal performance of these new structures is compared to that of the reference one, for a case-study given by a 4 × 4 × 4 array. To this end, a full-3D numerical Multiphysics model is implemented and successfully compared against other models in literature. The possibility of changing the interconnect materials is also analyzed. The results of this performance analysis clearly show the benefits of moving to these novel architectures, together with the choice of new materials.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"2 ","pages":"111-119"},"PeriodicalIF":1.7,"publicationDate":"2021-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782713/9316416/09601273.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3488262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-02DOI: 10.1109/OJNANO.2021.3124363
Peng Zhao;Yu Dian Lim;Hong Yu Li;Guidoni Luca;Chuan Seng Tan
As a key approach to augment Moore's Law scaling, 3D integration technologies have enabled small form factor, low cost, diverse, modular and flexible assembly of integrated circuits in the semiconductor industry. It is therefore essential to adopt these technologies to the quantum computing devices which are at the nascent stage and generally require large scale integration to be practical. In this review, we focus on four popular quantum bit (qubit) candidates (trapped ion, superconducting circuit, silicon spin and photon) which are encoded by distinct physical systems but all intrinsically compatible with advanced CMOS fabrication process. We introduce the specific scalability bottlenecks of each qubit type and present the current solutions using 3D integration technologies. We evaluate and classify these technologies into three main categories based on the hierarchy. A brief discussion regarding the thermal management is also provided. We believe this review serves to provide some useful insights on the contributions of interconnect, integration and packaging to the field of quantum computing where rapid development is ongoing.
{"title":"Advanced 3D Integration Technologies in Various Quantum Computing Devices","authors":"Peng Zhao;Yu Dian Lim;Hong Yu Li;Guidoni Luca;Chuan Seng Tan","doi":"10.1109/OJNANO.2021.3124363","DOIUrl":"https://doi.org/10.1109/OJNANO.2021.3124363","url":null,"abstract":"As a key approach to augment Moore's Law scaling, 3D integration technologies have enabled small form factor, low cost, diverse, modular and flexible assembly of integrated circuits in the semiconductor industry. It is therefore essential to adopt these technologies to the quantum computing devices which are at the nascent stage and generally require large scale integration to be practical. In this review, we focus on four popular quantum bit (qubit) candidates (trapped ion, superconducting circuit, silicon spin and photon) which are encoded by distinct physical systems but all intrinsically compatible with advanced CMOS fabrication process. We introduce the specific scalability bottlenecks of each qubit type and present the current solutions using 3D integration technologies. We evaluate and classify these technologies into three main categories based on the hierarchy. A brief discussion regarding the thermal management is also provided. We believe this review serves to provide some useful insights on the contributions of interconnect, integration and packaging to the field of quantum computing where rapid development is ongoing.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"2 ","pages":"101-110"},"PeriodicalIF":1.7,"publicationDate":"2021-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782713/9316416/09599482.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3514497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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