The junctionless multi-nanowire (JL-MNW) gate-all-around (GAA) field-effect transistor (FET) has become an emerging device in the advanced node of modern semiconductor devices because of its inherent operational mechanism properties. Therefore, in this paper, the Sentaurus TCAD simulator is calibrated with a compact thermal conductivity model using experimentally measured I-V characteristic data of JL-MNW GAA FET and electro-thermal characteristics of the experimental device are mapped into the contour plots. The non-uniform lattice temperature distribution is observed in an experimental device, and the change of peak lattice temperature $(Delta text{T}~_{mathrm{ L,,max}}$ ) is linearly increased with DC power. Further, in the sub-5nm technology node, the self-heating effect (SHE) is analyzed with variations of device active areas, such as vertical nanowire stacking and poly gate thickness (TP) between two nanowires in a DC operation. This work reveals that the device’s physical parameter variation affects overall performance in sub-5 nm technology nodes, such as ON-current (ION) degradation and delay time. But its thermal reliability is better than the inversion mode GAA FET, such as the peak of lattice temperature (T $_{mathrm{ L,,max}}$ ) and thermal resistance (RTH). These are extensively investigated using the Figure of Merit (FoM). Furthermore, the thermal reliability of the experimental device and advanced node JL-MNW GAA FETs are also analyzed in terms of hot carrier injection (HCI) lifetime and bias temperature instability (BTI) lifetime degradation with respect to the $text{T}_{mathrm{ L,max}}$ and TP. Considering these results, the junctionless device is expected to be an attractive candidate to improve the performance and reliability in advanced nodes simultaneously.
{"title":"Self-Heating Mapping of the Experimental Device and Its Optimization in Advance Sub-5 nm Node Junctionless Multi-Nanowire FETs","authors":"Nitish Kumar;Shraddha Pali;Ankur Gupta;Pushpapraj Singh","doi":"10.1109/TDMR.2023.3340032","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3340032","url":null,"abstract":"The junctionless multi-nanowire (JL-MNW) gate-all-around (GAA) field-effect transistor (FET) has become an emerging device in the advanced node of modern semiconductor devices because of its inherent operational mechanism properties. Therefore, in this paper, the Sentaurus TCAD simulator is calibrated with a compact thermal conductivity model using experimentally measured I-V characteristic data of JL-MNW GAA FET and electro-thermal characteristics of the experimental device are mapped into the contour plots. The non-uniform lattice temperature distribution is observed in an experimental device, and the change of peak lattice temperature \u0000<inline-formula> <tex-math>$(Delta text{T}~_{mathrm{ L,,max}}$ </tex-math></inline-formula>\u0000) is linearly increased with DC power. Further, in the sub-5nm technology node, the self-heating effect (SHE) is analyzed with variations of device active areas, such as vertical nanowire stacking and poly gate thickness (TP) between two nanowires in a DC operation. This work reveals that the device’s physical parameter variation affects overall performance in sub-5 nm technology nodes, such as ON-current (ION) degradation and delay time. But its thermal reliability is better than the inversion mode GAA FET, such as the peak of lattice temperature (T \u0000<inline-formula> <tex-math>$_{mathrm{ L,,max}}$ </tex-math></inline-formula>\u0000) and thermal resistance (RTH). These are extensively investigated using the Figure of Merit (FoM). Furthermore, the thermal reliability of the experimental device and advanced node JL-MNW GAA FETs are also analyzed in terms of hot carrier injection (HCI) lifetime and bias temperature instability (BTI) lifetime degradation with respect to the \u0000<inline-formula> <tex-math>$text{T}_{mathrm{ L,max}}$ </tex-math></inline-formula>\u0000 and TP. Considering these results, the junctionless device is expected to be an attractive candidate to improve the performance and reliability in advanced nodes simultaneously.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"33-40"},"PeriodicalIF":2.0,"publicationDate":"2023-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140067244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-06DOI: 10.1109/TDMR.2023.3336491
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Pub Date : 2023-12-06DOI: 10.1109/TDMR.2023.3336490
{"title":"IEEE Transactions on Device and Materials Reliability Information for Authors","authors":"","doi":"10.1109/TDMR.2023.3336490","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3336490","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"23 4","pages":"C3-C3"},"PeriodicalIF":2.0,"publicationDate":"2023-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10346025","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138502125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-06DOI: 10.1109/TDMR.2023.3331066
{"title":"Special Issue on Semiconductor Design for Manufacturing (DFM)Joint Call for Papers","authors":"","doi":"10.1109/TDMR.2023.3331066","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3331066","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"23 4","pages":"623-623"},"PeriodicalIF":2.0,"publicationDate":"2023-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10346020","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138502127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-06DOI: 10.1109/TDMR.2023.3336489
{"title":"IEEE Transactions on Device and Materials Reliability Publication Information","authors":"","doi":"10.1109/TDMR.2023.3336489","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3336489","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"23 4","pages":"C2-C2"},"PeriodicalIF":2.0,"publicationDate":"2023-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10346026","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138502131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-31DOI: 10.1109/TDMR.2023.3328601
Uttara Chakraborty;Emmanuel Bender;Duane S. Boning;Carl V. Thompson
Assessing the reliability of electronic devices, circuits and packages requires accurate lifetime predictions and identification of failure modes. This paper demonstrates a new approach to the extraction of underlying failure mechanism distribution parameters from data corresponding to a combined distribution of two distinct mechanisms. Specifically, a differential evolution approach is developed for parameter identification in competing-risks and mixture models. Use of multiple metrics for performance evaluation shows that our approach outperforms the best-known methods in the literature. Numerical results are shown for simulated data and also for package-level and device-level real failure data. On the modeling of industrial package failure data, our approach provides up to 92% reduction in mean squared error, up to 7% increase in log-likelihood and up to 61% decrease in the maximum Kolmogorov-Smirnov distance. On ring oscillator data obtained from our laboratory experiments, the corresponding improvements are 94%, 5% and 77%, respectively. For both simulated and real datasets, the improvement in performance is validated through statistical tests of significance. An application of the approach is demonstrated for empirical extraction of the temperature-dependence of parameters from lifetime data at different test temperatures.
{"title":"Identification of Multiple Failure Mechanisms for Device Reliability Using Differential Evolution","authors":"Uttara Chakraborty;Emmanuel Bender;Duane S. Boning;Carl V. Thompson","doi":"10.1109/TDMR.2023.3328601","DOIUrl":"10.1109/TDMR.2023.3328601","url":null,"abstract":"Assessing the reliability of electronic devices, circuits and packages requires accurate lifetime predictions and identification of failure modes. This paper demonstrates a new approach to the extraction of underlying failure mechanism distribution parameters from data corresponding to a combined distribution of two distinct mechanisms. Specifically, a differential evolution approach is developed for parameter identification in competing-risks and mixture models. Use of multiple metrics for performance evaluation shows that our approach outperforms the best-known methods in the literature. Numerical results are shown for simulated data and also for package-level and device-level real failure data. On the modeling of industrial package failure data, our approach provides up to 92% reduction in mean squared error, up to 7% increase in log-likelihood and up to 61% decrease in the maximum Kolmogorov-Smirnov distance. On ring oscillator data obtained from our laboratory experiments, the corresponding improvements are 94%, 5% and 77%, respectively. For both simulated and real datasets, the improvement in performance is validated through statistical tests of significance. An application of the approach is demonstrated for empirical extraction of the temperature-dependence of parameters from lifetime data at different test temperatures.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"23 4","pages":"599-614"},"PeriodicalIF":2.0,"publicationDate":"2023-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135263574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-25DOI: 10.1109/TDMR.2023.3327664
Emmanuel Chery;Corinna Fohn;Joke De Messemaeker;Eric Beyne
As the traditional more Moore approach is slowing down, due to the increase in development costs and logic complexity, 3D technologies are enabling complex More than Moore Systems-on-Chip (SoC), offering higher performances and functionalities to customers. 3D SoC combine efficiently chips from different technology nodes through vertical interconnections, enabling complex designs out of reach of the monolithic approach. Vertical interconnection technologies are therefore key enablers of the More than Moore paradigm, allowing higher densities with reduced latencies. In particular, through silicon vias (TSV) and wafer-to-wafer hybrid bonding will be key to the success of the next generation of 3D Systems-on-Chip by bringing the interconnect densities above 106 mm−2. In this article, the reliability challenges and failure mechanisms related to these two technologies are reviewed and potential mitigation solutions developed at imec are introduced. In the first section, the process and technology choices enabling the TSV and SiCN–SiCN wafer-to-wafer hybrid-bonding technologies are summarized. Subsequently, the impact of mechanical stress and liner integrity on the reliability of TSVs are discussed. In this context, it is shown that copper poisoning in the dielectric during the liner opening etch is a major challenge, requiring careful optimization of the etch recipe. A lifetime assessment of the hybrid-bonding pad-to-pad interface is then presented. The importance of a soft CMP process, that minimizes the degradation of the bonding dielectric and therefore the creation of defects is demonstrated. Additionally, the impact of copper migration along the bonding interface on the reliability performance is mentioned. Finally, the role of bonding voids in the electromigration performances of copper pads will be discussed.
{"title":"Reliability Challenges in Advanced 3D Technologies: The Case of Through Silicon Vias and SiCN–SiCN Wafer-to-Wafer Hybrid-Bonding Technologies","authors":"Emmanuel Chery;Corinna Fohn;Joke De Messemaeker;Eric Beyne","doi":"10.1109/TDMR.2023.3327664","DOIUrl":"10.1109/TDMR.2023.3327664","url":null,"abstract":"As the traditional more Moore approach is slowing down, due to the increase in development costs and logic complexity, 3D technologies are enabling complex More than Moore Systems-on-Chip (SoC), offering higher performances and functionalities to customers. 3D SoC combine efficiently chips from different technology nodes through vertical interconnections, enabling complex designs out of reach of the monolithic approach. Vertical interconnection technologies are therefore key enablers of the More than Moore paradigm, allowing higher densities with reduced latencies. In particular, through silicon vias (TSV) and wafer-to-wafer hybrid bonding will be key to the success of the next generation of 3D Systems-on-Chip by bringing the interconnect densities above 106 mm−2. In this article, the reliability challenges and failure mechanisms related to these two technologies are reviewed and potential mitigation solutions developed at imec are introduced. In the first section, the process and technology choices enabling the TSV and SiCN–SiCN wafer-to-wafer hybrid-bonding technologies are summarized. Subsequently, the impact of mechanical stress and liner integrity on the reliability of TSVs are discussed. In this context, it is shown that copper poisoning in the dielectric during the liner opening etch is a major challenge, requiring careful optimization of the etch recipe. A lifetime assessment of the hybrid-bonding pad-to-pad interface is then presented. The importance of a soft CMP process, that minimizes the degradation of the bonding dielectric and therefore the creation of defects is demonstrated. Additionally, the impact of copper migration along the bonding interface on the reliability performance is mentioned. Finally, the role of bonding voids in the electromigration performances of copper pads will be discussed.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"23 4","pages":"615-622"},"PeriodicalIF":2.0,"publicationDate":"2023-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135158606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-23DOI: 10.1109/TDMR.2023.3326778
Nikita Kar Chowdhury;Aditya Kumar Singh;Arnab Hazra;Basanta Bhowmik
In the present paper, $TiO_{2}$ nanoparticles were synthesized through low cost hydrothermal method at 150°C. Structural, morphological and optical properties of the grown materials were characterized through X-ray diffraction (XRD), Field emission scanning electron microscopy (FESEM), Raman Spectroscopy, and Photoluminescence spectroscopy, respectively. X-ray diffraction confirms the anatase phase with average crystalline size of 6.8 nm. Non-uniform particles having numerous pores with large number of active sites offered superior capability to detect methanol even at lower concentrations. Band gap of the material were found to be 3.4 eV. $TiO_{2}$ nanoparticles in planner structure were investigated towards methanol (1-100 ppm) at the temperature ranging from (25-150°C). Sensor was found to be maximum responsive with response magnitude of 85% at 100°C and 47% at room temperature towards 100 ppm of methanol. At 1 ppm of methanol, sensor response was found to be 20%. Sensor response towards methanol was correlated with the surface state of nanoparticles with HOMO-LUMO energy.
{"title":"Highly Reproducible and Reliable Methanol Sensor Based on Hydrothermally Grown TiO2 Nanoparticles","authors":"Nikita Kar Chowdhury;Aditya Kumar Singh;Arnab Hazra;Basanta Bhowmik","doi":"10.1109/TDMR.2023.3326778","DOIUrl":"10.1109/TDMR.2023.3326778","url":null,"abstract":"In the present paper, \u0000<inline-formula> <tex-math>$TiO_{2}$ </tex-math></inline-formula>\u0000 nanoparticles were synthesized through low cost hydrothermal method at 150°C. Structural, morphological and optical properties of the grown materials were characterized through X-ray diffraction (XRD), Field emission scanning electron microscopy (FESEM), Raman Spectroscopy, and Photoluminescence spectroscopy, respectively. X-ray diffraction confirms the anatase phase with average crystalline size of 6.8 nm. Non-uniform particles having numerous pores with large number of active sites offered superior capability to detect methanol even at lower concentrations. Band gap of the material were found to be 3.4 eV. \u0000<inline-formula> <tex-math>$TiO_{2}$ </tex-math></inline-formula>\u0000 nanoparticles in planner structure were investigated towards methanol (1-100 ppm) at the temperature ranging from (25-150°C). Sensor was found to be maximum responsive with response magnitude of 85% at 100°C and 47% at room temperature towards 100 ppm of methanol. At 1 ppm of methanol, sensor response was found to be 20%. Sensor response towards methanol was correlated with the surface state of nanoparticles with HOMO-LUMO energy.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"23 4","pages":"591-598"},"PeriodicalIF":2.0,"publicationDate":"2023-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135151567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-13DOI: 10.1109/TDMR.2023.3323899
Lin Cheng;Hongliang Lu;Silu Yan;Junjun Qi;Wei Cheng;Yuming Zhang;Yimen Zhang
To predict the aging effect on indium phosphide (InP) heterojunction bipolar transistors (HBTs), an aging small-signal equivalent circuit modeling method is proposed in this paper, with special attention to the degradation of the key small-signal model parameters of the InP HBTs in aging experiments. Based on the analysis of the aging sensitivity of the complete small-signal equivalent circuit parameters, semi-empirical approach is used to model the degradation of the key parameters in bipolar transistors as a function of stress magnitude and stress time. Its validity and accuracy are demonstrated by comparison of the modeled and measured results for InP HBTs before and after degradation.
{"title":"An Aging Small-Signal Equivalent Circuit Modeling Method for InP HBT","authors":"Lin Cheng;Hongliang Lu;Silu Yan;Junjun Qi;Wei Cheng;Yuming Zhang;Yimen Zhang","doi":"10.1109/TDMR.2023.3323899","DOIUrl":"10.1109/TDMR.2023.3323899","url":null,"abstract":"To predict the aging effect on indium phosphide (InP) heterojunction bipolar transistors (HBTs), an aging small-signal equivalent circuit modeling method is proposed in this paper, with special attention to the degradation of the key small-signal model parameters of the InP HBTs in aging experiments. Based on the analysis of the aging sensitivity of the complete small-signal equivalent circuit parameters, semi-empirical approach is used to model the degradation of the key parameters in bipolar transistors as a function of stress magnitude and stress time. Its validity and accuracy are demonstrated by comparison of the modeled and measured results for InP HBTs before and after degradation.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"23 4","pages":"530-536"},"PeriodicalIF":2.0,"publicationDate":"2023-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136305820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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