Pub Date : 2025-03-13DOI: 10.1109/TDMR.2025.3569588
Pengyan Wen;Huixin Xiu;Shuming Zhang;Jianping Liu;Yimeng Chen;Hui Yang
Gallium nitride (GaN)-based lasers, spanning emission wavelengths from ultraviolet to green, are widely used as light sources in many application domains. Despite their widespread usage, the comprehensive analysis of atomic-level degradation remains challenging primarily due to limitations in metrology techniques. In this study, we investigated the aging-induced magnesium (Mg) clusters in GaN-based lasers utilizing atom probe tomography. Notably, we have identified Mg clusters of several nanometers in size within the p-type aluminum gallium nitride (p-AlGaN) cladding layer of aged lasers, marking the first observation of such clusters in this context. The presence of Mg clusters induces light scattering and absorption within the cladding layer, contributing to an increase in internal loss and a decrease in slope efficiency. Furthermore, our findings underscore the efficacy of atom probe tomography as a potent technique for conducting atomic-level device failure analysis of semiconductor devices.
{"title":"Aging-Induced Mg Cluster Observation in GaN-Based Lasers by Atom Probe Tomography","authors":"Pengyan Wen;Huixin Xiu;Shuming Zhang;Jianping Liu;Yimeng Chen;Hui Yang","doi":"10.1109/TDMR.2025.3569588","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3569588","url":null,"abstract":"Gallium nitride (GaN)-based lasers, spanning emission wavelengths from ultraviolet to green, are widely used as light sources in many application domains. Despite their widespread usage, the comprehensive analysis of atomic-level degradation remains challenging primarily due to limitations in metrology techniques. In this study, we investigated the aging-induced magnesium (Mg) clusters in GaN-based lasers utilizing atom probe tomography. Notably, we have identified Mg clusters of several nanometers in size within the p-type aluminum gallium nitride (p-AlGaN) cladding layer of aged lasers, marking the first observation of such clusters in this context. The presence of Mg clusters induces light scattering and absorption within the cladding layer, contributing to an increase in internal loss and a decrease in slope efficiency. Furthermore, our findings underscore the efficacy of atom probe tomography as a potent technique for conducting atomic-level device failure analysis of semiconductor devices.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"329-334"},"PeriodicalIF":2.5,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-13DOI: 10.1109/TDMR.2025.3550950
Yujie Fan;Jiawei Liu;Jie Jiang;Li-Mei Jiang
With the advancement of information technology, ferroelectric memories have garnered significant attention due to their non-volatility, high theoretical storage density, low power consumption, and excellent radiation resistance. Hafnium oxide-based ferroelectric materials have a high dielectric constant, a relatively wide bandgap, and good compatibility with CMOS processes, making them suitable for developing the next generation of ferroelectric memories. However, the stability issues hafnium oxide-based ferroelectric thin films face during service, including the wake-up effect and poor polarization retention, hinder the commercialization process of hafnium oxide-based ferroelectric memories developed from these thin films. This paper explores the possibility of optimizing the stability issues of HfO2-based ferroelectric thin films through ion irradiation based on a phase-field model of hafnium oxide-based ferroelectric thin films. The research results show that ion irradiation can effectively weaken the wake-up effect and improve the retention of the thin films. After irradiation with H, He, Fe, and Ar ions, the increase in remanent polarization values of HfO2-based ferroelectric thin films after wake-up was significantly reduced compared to the increase observed in non-irradiated films. Among them, the thin films irradiated with Ar ions showed the smallest increase in remanent polarization after wake-up, at only 9%, while the non-irradiated films exhibited a much higher increase of 260%. Additionally, the ten-year polarization retention efficiencies of the films post-irradiation were also excellent, reaching 95.2%, 93.3%, 92.7%, and 94.5% for H, He, Fe, and Ar ions, respectively. Since Ar ions most effectively reduce the wake-up effect and enhance polarization retention, this study recommends using Ar ions to optimize the stability of hafnium oxide-based ferroelectric thin films. This study provides new insights into optimizing HfO2-based ferroelectric thin films and explores their potential applications in ferroelectric memories.
{"title":"Ion Radiation Effects on the Stability of Hafnium Oxide-Based Ferroelectric Thin Films: Mechanisms and Regulation","authors":"Yujie Fan;Jiawei Liu;Jie Jiang;Li-Mei Jiang","doi":"10.1109/TDMR.2025.3550950","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3550950","url":null,"abstract":"With the advancement of information technology, ferroelectric memories have garnered significant attention due to their non-volatility, high theoretical storage density, low power consumption, and excellent radiation resistance. Hafnium oxide-based ferroelectric materials have a high dielectric constant, a relatively wide bandgap, and good compatibility with CMOS processes, making them suitable for developing the next generation of ferroelectric memories. However, the stability issues hafnium oxide-based ferroelectric thin films face during service, including the wake-up effect and poor polarization retention, hinder the commercialization process of hafnium oxide-based ferroelectric memories developed from these thin films. This paper explores the possibility of optimizing the stability issues of HfO2-based ferroelectric thin films through ion irradiation based on a phase-field model of hafnium oxide-based ferroelectric thin films. The research results show that ion irradiation can effectively weaken the wake-up effect and improve the retention of the thin films. After irradiation with H, He, Fe, and Ar ions, the increase in remanent polarization values of HfO2-based ferroelectric thin films after wake-up was significantly reduced compared to the increase observed in non-irradiated films. Among them, the thin films irradiated with Ar ions showed the smallest increase in remanent polarization after wake-up, at only 9%, while the non-irradiated films exhibited a much higher increase of 260%. Additionally, the ten-year polarization retention efficiencies of the films post-irradiation were also excellent, reaching 95.2%, 93.3%, 92.7%, and 94.5% for H, He, Fe, and Ar ions, respectively. Since Ar ions most effectively reduce the wake-up effect and enhance polarization retention, this study recommends using Ar ions to optimize the stability of hafnium oxide-based ferroelectric thin films. This study provides new insights into optimizing HfO2-based ferroelectric thin films and explores their potential applications in ferroelectric memories.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"314-322"},"PeriodicalIF":2.5,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The threshold voltage shift issue caused by traps in silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) is studied based on transient current method. Experiment results show gate stress, drain stress, and temperature all contribute to threshold voltage shift, with the underlying cause of traps. To obtain physical characteristics of the traps, we test the drain current of the device after filling the traps and utilize a Bayesian iterative deconvolution algorithm to extract the time constants. To accurately explore the impact of traps on the current, we further process the time constant spectrum into a differential amplitude spectrum (DAS), which provides greater precision in addressing the issue of trap amplitudes. We also analyze the variation of trap time constants at different environmental temperatures, and extract the activation energies of the traps in conjunction with the Arrhenius equation. Ultimately, experiments discover two types of electron traps and hole traps.
{"title":"Study of Trap Influence on Threshold Voltage of SiC MOSFET Based on Transient Current Method","authors":"Zhuoming Liu;Qian Wen;Xianwei Meng;Shijie Pan;Chunsheng Guo;Shiwei Feng;Yamin Zhang;Meng Zhang","doi":"10.1109/TDMR.2025.3569318","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3569318","url":null,"abstract":"The threshold voltage shift issue caused by traps in silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) is studied based on transient current method. Experiment results show gate stress, drain stress, and temperature all contribute to threshold voltage shift, with the underlying cause of traps. To obtain physical characteristics of the traps, we test the drain current of the device after filling the traps and utilize a Bayesian iterative deconvolution algorithm to extract the time constants. To accurately explore the impact of traps on the current, we further process the time constant spectrum into a differential amplitude spectrum (DAS), which provides greater precision in addressing the issue of trap amplitudes. We also analyze the variation of trap time constants at different environmental temperatures, and extract the activation energies of the traps in conjunction with the Arrhenius equation. Ultimately, experiments discover two types of electron traps and hole traps.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"323-328"},"PeriodicalIF":2.5,"publicationDate":"2025-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The insulated gate bipolar transistor (IGBT) has widespread application in energy storage systems, motor drives, smart grids, household appliances and other various fields. These applications demand accurate evaluation of reliability through lifespan prediction to ensure optimal performance and longevity. This study proposes an innovative IGBT lifespan prediction model using an improved dung beetle optimized back propagation neural network (IDBO-BP). The model integrates chebyshev chaotic mapping and golden sine strategy to address critical limitations of existing methods, including low accuracy, poor computational efficiency and weak dynamic adaptability. Chaotic initialization is applied to enhance population diversity and adaptive golden ratio-modulated step sizes are utilized to refine local search precision. This innovative approach delivers breakthroughs in enhancing prediction accuracy and accelerating computation speed without compromising the system’s global exploration capabilities. Besides, a constant case temperature-controlled AC power cycling test protocol was designed to verify the effectiveness of the improved algorithm. This test features suppression of thermal fluctuation interference and the consideration of both conduction losses and switching losses which better simulate real operating conditions. Experimental results demonstrate higher prediction accuracy of the IDBO-BP model compared to DBO-BP, PSO-BP, and GWO-BP. The ${mathrm { R}}^{2}$ values of IDBO-BP model surpass the other methods by an average of 4–27 percentage points respectively. Improved stability of IDBO-BP model is confirmed by lower RMSE values with average error reductions of 9.13–32.1 percentage points, which indicate enhanced robustness in handling nonlinear and fluctuating data for IGBT lifetime prediction.
{"title":"Lifetime Prediction of IGBT by BPNN Based on Improved Dung Beetle Optimization Algorithm","authors":"Peng Dai;Junyi Bao;Zheng Gong;Mingchang Gao;Qing Xu","doi":"10.1109/TDMR.2025.3567650","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3567650","url":null,"abstract":"The insulated gate bipolar transistor (IGBT) has widespread application in energy storage systems, motor drives, smart grids, household appliances and other various fields. These applications demand accurate evaluation of reliability through lifespan prediction to ensure optimal performance and longevity. This study proposes an innovative IGBT lifespan prediction model using an improved dung beetle optimized back propagation neural network (IDBO-BP). The model integrates chebyshev chaotic mapping and golden sine strategy to address critical limitations of existing methods, including low accuracy, poor computational efficiency and weak dynamic adaptability. Chaotic initialization is applied to enhance population diversity and adaptive golden ratio-modulated step sizes are utilized to refine local search precision. This innovative approach delivers breakthroughs in enhancing prediction accuracy and accelerating computation speed without compromising the system’s global exploration capabilities. Besides, a constant case temperature-controlled AC power cycling test protocol was designed to verify the effectiveness of the improved algorithm. This test features suppression of thermal fluctuation interference and the consideration of both conduction losses and switching losses which better simulate real operating conditions. Experimental results demonstrate higher prediction accuracy of the IDBO-BP model compared to DBO-BP, PSO-BP, and GWO-BP. The <inline-formula> <tex-math>${mathrm { R}}^{2}$ </tex-math></inline-formula> values of IDBO-BP model surpass the other methods by an average of 4–27 percentage points respectively. Improved stability of IDBO-BP model is confirmed by lower RMSE values with average error reductions of 9.13–32.1 percentage points, which indicate enhanced robustness in handling nonlinear and fluctuating data for IGBT lifetime prediction.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"341-351"},"PeriodicalIF":2.5,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-07DOI: 10.1109/TDMR.2025.3548979
Sai Gao;Shaoxiang Wang;Jianxiong Yang;Mingxing Du
This paper investigates the impact of bond wire aging on differential mode (DM) electromagnetic interference (EMI) noise emissions in IGBTs under the influence of high-frequency ringing. Using a DC-DC buck converter composed of an IGBT half-bridge module as an example, the study analyzes the changes in the EMI spectrum caused by bond wire lift-off in both the time and frequency domains. The paper explains the generation mechanism of high-frequency oscillations induced by the interaction between the stray inductance of the DC link and the freewheeling diode. The study reveals that bond wire lift-off alters DM EMI noise emissions by affecting the switching characteristics of the IGBT. Additionally, an increase in the number of lift-off bond wires during ringing significantly enhances DM EMI noise emissions at and above the resonance frequency. The findings of this study provide a new perspective on the aging effects of power electronic devices and their impact on EMI.
{"title":"The Influence of Bond Wire Aging on DM EMI Noise in IGBT Converters Considering High-Frequency Ringing","authors":"Sai Gao;Shaoxiang Wang;Jianxiong Yang;Mingxing Du","doi":"10.1109/TDMR.2025.3548979","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3548979","url":null,"abstract":"This paper investigates the impact of bond wire aging on differential mode (DM) electromagnetic interference (EMI) noise emissions in IGBTs under the influence of high-frequency ringing. Using a DC-DC buck converter composed of an IGBT half-bridge module as an example, the study analyzes the changes in the EMI spectrum caused by bond wire lift-off in both the time and frequency domains. The paper explains the generation mechanism of high-frequency oscillations induced by the interaction between the stray inductance of the DC link and the freewheeling diode. The study reveals that bond wire lift-off alters DM EMI noise emissions by affecting the switching characteristics of the IGBT. Additionally, an increase in the number of lift-off bond wires during ringing significantly enhances DM EMI noise emissions at and above the resonance frequency. The findings of this study provide a new perspective on the aging effects of power electronic devices and their impact on EMI.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"223-231"},"PeriodicalIF":2.5,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ferroelectric transistors can function as non-volatile memory devices with single-bit, multi-bit, and analog capabilities. State modulation is achieved by programming and erasing with bipolar pulse voltages, while a series of unipolar pulses enable synaptic potentiation and depression. This study examines the effect of pulse voltage stress on the reliability of ferroelectric thin-film transistors (FeTFT) with polycrystalline-silicon (poly-Si) ultra-thin body (UTB) channels. By applying various pulse stresses—bipolar, positive, and negative unipolar—with different pulse widths, we observed distinct degradation behaviors in UTB-FeTFT characteristics. Long bipolar pulse stress caused significant degradation due to the combined effects of the internal electric field from the ferroelectric layer and the external field. In contrast, short bipolar stress led to milder degradation, as lower remnant polarization reduced the total stress field. Rapid changes in electric field direction also limited charge accumulation in the channel, decreasing interface trap generation. Although short bipolar stress had minimal impact on subthreshold swing, it notably degraded maximum transconductance, primarily due to strain in the poly-Si channel’s atomic bonds. Enhancing device reliability is essential for improving FeTFT endurance.
{"title":"Impact of Pulse Voltage Stress on the Reliability of Ferroelectric Thin-Film Transistor","authors":"William Cheng-Yu Ma;Chun-Jung Su;Kuo-Hsing Kao;Yu-Chieh Yen;Ji-Min Yang;Yi-Han Li;Yen-Chen Chen;Jhe-Yu Lin;Hui-Wen Chang","doi":"10.1109/TDMR.2025.3548038","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3548038","url":null,"abstract":"Ferroelectric transistors can function as non-volatile memory devices with single-bit, multi-bit, and analog capabilities. State modulation is achieved by programming and erasing with bipolar pulse voltages, while a series of unipolar pulses enable synaptic potentiation and depression. This study examines the effect of pulse voltage stress on the reliability of ferroelectric thin-film transistors (FeTFT) with polycrystalline-silicon (poly-Si) ultra-thin body (UTB) channels. By applying various pulse stresses—bipolar, positive, and negative unipolar—with different pulse widths, we observed distinct degradation behaviors in UTB-FeTFT characteristics. Long bipolar pulse stress caused significant degradation due to the combined effects of the internal electric field from the ferroelectric layer and the external field. In contrast, short bipolar stress led to milder degradation, as lower remnant polarization reduced the total stress field. Rapid changes in electric field direction also limited charge accumulation in the channel, decreasing interface trap generation. Although short bipolar stress had minimal impact on subthreshold swing, it notably degraded maximum transconductance, primarily due to strain in the poly-Si channel’s atomic bonds. Enhancing device reliability is essential for improving FeTFT endurance.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"240-246"},"PeriodicalIF":2.5,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As the electromigration (EM) reliability margin reduces rapidly with scaling, novel approaches for EM-compliance checks are being intensively sought to enable more accurate and less conservative analyses. Currently, chip-level EM reliability is assessed based on the failure probability of individual lines and vias in the BEOL stack, overlooking potential redundant connections that could still ensure circuit operation despite isolated failures. This is particularly relevant for the power delivery network (PDN), which is redundant by definition due to its regular mesh structure. In this work, we leverage a new approach to perform EM-compliance checks that relies on considering the PDN as a matrix of identical network units-cells, henceforth referred to as tiles, and using them to compute the overall failure risk. As opposed to conventional methods, our approach captures the impact of redundancy within each individual PDN tile, thereby providing less conservative reliability estimations. After reviewing standard methods for EM-compliance checks, namely limit-based and statistical EM budgeting (SEB), we quantify the additional reliability margin provided by our PDN-tile approach. For our analysis, we considered a PDN featuring three different metallization schemes for Dual Damascene (DD) Cu/Low-k interconnects utilizing SiCN capping, Cobalt (Co) capping with and without Ruthenium (Ru) via prefill. Using the standard SEB method indicated that Co capping and Co capping + Ru Via Prefill lead to reductions in EM failure risk by 5 and 7 orders of magnitude, respectively, compared to SiCN capping. The new approach was implemented for the first metallization with SiCN capping. At 10 years lifetime, our PDN-tile approach foresees a failure probability which is 3 orders of magnitude smaller than the SEB approach. At an equivalent failure probability of 100ppm and the same target lifetime of 10 years, the current of standard cells can be increased by 2.8-fold, giving designers more margin to improve chip performances.
由于电迁移（EM）的可靠性裕度随着规模的扩大而迅速降低，人们正在积极寻求新的EM符合性检查方法，以实现更准确、更保守的分析。目前，芯片级电磁可靠性的评估是基于BEOL堆栈中单个线路和过孔的故障概率，忽略了潜在的冗余连接，这些连接在孤立故障的情况下仍然可以确保电路运行。这与电力输送网络（PDN）特别相关，由于其规则的网格结构，PDN在定义上是冗余的。在这项工作中，我们利用一种新的方法来执行em合规性检查，该方法依赖于将PDN视为相同网络单元-单元的矩阵，因此称为单元，并使用它们来计算整体故障风险。与传统方法相反，我们的方法捕获了每个PDN块中冗余的影响，从而提供了更保守的可靠性估计。在回顾了电磁符合性检查的标准方法，即基于限制和统计电磁预算（SEB）之后，我们量化了PDN-tile方法提供的额外可靠性裕度。在我们的分析中，我们考虑了一种具有三种不同金属化方案的PDN，用于双Damascene (DD) Cu/Low-k互连，利用SiCN封盖、钴（Co）封盖和不通过预填充的钌（Ru）。使用标准的SEB方法表明，与SiCN封盖相比，Co封盖和Co封盖+ Ru Via Prefill分别降低了5个和7个数量级的EM失效风险。新方法用于第一次SiCN封盖的金属化。在10年的寿命中，我们的PDN-tile方法预测的失效概率比SEB方法小3个数量级。在100ppm的等效失效概率和相同的目标寿命为10年的情况下，标准电池的电流可以增加2.8倍，为设计人员提供了更大的空间来提高芯片性能。
{"title":"Unit-Cell-Based Approach for Electromigration Compliance Checks in VLSI Power Delivery Networks","authors":"Simone Esposto;Ivan Ciofi;Giuliano Sisto;Kristof Croes;Dragomir Milojevic;Houman Zahedmanesh","doi":"10.1109/TDMR.2025.3566054","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3566054","url":null,"abstract":"As the electromigration (EM) reliability margin reduces rapidly with scaling, novel approaches for EM-compliance checks are being intensively sought to enable more accurate and less conservative analyses. Currently, chip-level EM reliability is assessed based on the failure probability of individual lines and vias in the BEOL stack, overlooking potential redundant connections that could still ensure circuit operation despite isolated failures. This is particularly relevant for the power delivery network (PDN), which is redundant by definition due to its regular mesh structure. In this work, we leverage a new approach to perform EM-compliance checks that relies on considering the PDN as a matrix of identical network units-cells, henceforth referred to as tiles, and using them to compute the overall failure risk. As opposed to conventional methods, our approach captures the impact of redundancy within each individual PDN tile, thereby providing less conservative reliability estimations. After reviewing standard methods for EM-compliance checks, namely limit-based and statistical EM budgeting (SEB), we quantify the additional reliability margin provided by our PDN-tile approach. For our analysis, we considered a PDN featuring three different metallization schemes for Dual Damascene (DD) Cu/Low-k interconnects utilizing SiCN capping, Cobalt (Co) capping with and without Ruthenium (Ru) via prefill. Using the standard SEB method indicated that Co capping and Co capping + Ru Via Prefill lead to reductions in EM failure risk by 5 and 7 orders of magnitude, respectively, compared to SiCN capping. The new approach was implemented for the first metallization with SiCN capping. At 10 years lifetime, our PDN-tile approach foresees a failure probability which is 3 orders of magnitude smaller than the SEB approach. At an equivalent failure probability of 100ppm and the same target lifetime of 10 years, the current of standard cells can be increased by 2.8-fold, giving designers more margin to improve chip performances.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"232-239"},"PeriodicalIF":2.5,"publicationDate":"2025-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recent research demonstrates the feasibility of X-ray attacks. Unlike traditional fault injection methods, X-rays offer precise spatial targeting because of their short wavelength and high penetration power. This allows attackers to selectively target specific regions within a device, from individual transistors to larger blocks. This necessitates a new perspective on hardening techniques, requiring designers to consider the impact of X-ray irradiation on both fault injection and power consumption. To address this challenge, the paper proposes a characterization flow that analyzes the differences in side-channel leakages of FPGA components and their susceptibility to increased leakage due to X-ray effects. Despite the fundamental differences between ASIC and FPGA layouts, they both share the characteristic of being MOS technology-based, which makes them both susceptible to TID effects. The simulation results strongly support the theory that X-rays can induce leakage currents, thereby amplifying the side-channel information leakage observed in our experiments on FPGAs. Furthermore, these results provide concrete evidence that different FPGA components exhibit varying susceptibility to X-ray-induced leakage. Our findings reveal a clear hierarchy of vulnerability, with interconnects being the most susceptible elements, followed by registers, and lastly, logic components (LUTs and MUXes). This differential vulnerability offers valuable information for designers of secure cryptographic circuits. By understanding how X-rays impact different components, hardening techniques can be strategically targeted to provide the most effective protection against both fault injection and side-channel leakage.
{"title":"FPGA Assessment Methodology of Adverse X-Ray Effects on Secure Digital Circuits","authors":"Nasr-Eddine Ouldei Tebina;Luc Salvo;Nacer-Eddine Zergainoh;Guillaume Hubert;Paolo Maistri","doi":"10.1109/TDMR.2025.3538484","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3538484","url":null,"abstract":"Recent research demonstrates the feasibility of X-ray attacks. Unlike traditional fault injection methods, X-rays offer precise spatial targeting because of their short wavelength and high penetration power. This allows attackers to selectively target specific regions within a device, from individual transistors to larger blocks. This necessitates a new perspective on hardening techniques, requiring designers to consider the impact of X-ray irradiation on both fault injection and power consumption. To address this challenge, the paper proposes a characterization flow that analyzes the differences in side-channel leakages of FPGA components and their susceptibility to increased leakage due to X-ray effects. Despite the fundamental differences between ASIC and FPGA layouts, they both share the characteristic of being MOS technology-based, which makes them both susceptible to TID effects. The simulation results strongly support the theory that X-rays can induce leakage currents, thereby amplifying the side-channel information leakage observed in our experiments on FPGAs. Furthermore, these results provide concrete evidence that different FPGA components exhibit varying susceptibility to X-ray-induced leakage. Our findings reveal a clear hierarchy of vulnerability, with interconnects being the most susceptible elements, followed by registers, and lastly, logic components (LUTs and MUXes). This differential vulnerability offers valuable information for designers of secure cryptographic circuits. By understanding how X-rays impact different components, hardening techniques can be strategically targeted to provide the most effective protection against both fault injection and side-channel leakage.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"85-94"},"PeriodicalIF":2.5,"publicationDate":"2025-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A negative bias temperature instability (NBTI) equivalent circuit model based on P-FinFET of a 12nm CMOS PDK and electrical components and arithmetic units of EDA software is presented. The P-FinFET circuit model consists of electrical components such as voltage sources, controlled sources, adders and multipliers, and other arithmetic units. The model is set up with five tunable input parameters, including stress time, gate width, gate length, process corner (slow/ fast/ typical), and temperature. The equivalent circuit model also takes into account bias conditions of transistor, such as gate-source voltage, drain source voltage, and drain gate voltage, which will affect NBTI. Simulation result shows that the degradation curves of the equivalent circuit model for P-FinFET are in concordance with experimental data presented in previously published literatures.
{"title":"An Equivalent Circuit Model of 12 nm P-FinFET for NBTI Effect","authors":"Jun-An Zhang;Hao Chen;Bo Liu;Chao Li;Dan Li;Tiehu Li;Yunhua Lu;Qingwei Zhang","doi":"10.1109/TDMR.2025.3543863","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3543863","url":null,"abstract":"A negative bias temperature instability (NBTI) equivalent circuit model based on P-FinFET of a 12nm CMOS PDK and electrical components and arithmetic units of EDA software is presented. The P-FinFET circuit model consists of electrical components such as voltage sources, controlled sources, adders and multipliers, and other arithmetic units. The model is set up with five tunable input parameters, including stress time, gate width, gate length, process corner (slow/ fast/ typical), and temperature. The equivalent circuit model also takes into account bias conditions of transistor, such as gate-source voltage, drain source voltage, and drain gate voltage, which will affect NBTI. Simulation result shows that the degradation curves of the equivalent circuit model for P-FinFET are in concordance with experimental data presented in previously published literatures.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"247-252"},"PeriodicalIF":2.5,"publicationDate":"2025-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-20DOI: 10.1109/TDMR.2025.3544208
Yiping Xiao;Chaoming Liu;Jiaming Zhou;Mingzheng Wang;Chunhua Qi;Tianqi Wang;Mingxue Huo
Maintaining the robustness of the gate oxide is a prerequisite for the on-orbit application of SiC MOSFETs. Recent research has demonstrated that the oxide undergoes premature breakdown within the operating voltage range after heavy ion irradiation, which is attributed to the activation of ion-induced gate latent damages (LDs) under gate post-irradiation gate stress (PIGS). However, the specific activation processes of LDs and oxide failure mechanism are not well understood. This study indicates that the dielectric breakdown induced epitaxy (DBIE) and thermal runaway effects are the dominant mechanisms when oxide rupture occurs, characterized by a step-like increase in gate leakage current during PIGS test. The failure analysis further confirmed the formation of DBIE hillock and percolation path. The results suggest that more attention should be paid to the gate oxide reliability before SiC MOSFETs could replace their Si-based counterparts in aerospace applications.
{"title":"Microstructural Evolution of Gate Oxide in SiC Power MOSFETs Under Heavy-Ion Irradiation","authors":"Yiping Xiao;Chaoming Liu;Jiaming Zhou;Mingzheng Wang;Chunhua Qi;Tianqi Wang;Mingxue Huo","doi":"10.1109/TDMR.2025.3544208","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3544208","url":null,"abstract":"Maintaining the robustness of the gate oxide is a prerequisite for the on-orbit application of SiC MOSFETs. Recent research has demonstrated that the oxide undergoes premature breakdown within the operating voltage range after heavy ion irradiation, which is attributed to the activation of ion-induced gate latent damages (LDs) under gate post-irradiation gate stress (PIGS). However, the specific activation processes of LDs and oxide failure mechanism are not well understood. This study indicates that the dielectric breakdown induced epitaxy (DBIE) and thermal runaway effects are the dominant mechanisms when oxide rupture occurs, characterized by a step-like increase in gate leakage current during PIGS test. The failure analysis further confirmed the formation of DBIE hillock and percolation path. The results suggest that more attention should be paid to the gate oxide reliability before SiC MOSFETs could replace their Si-based counterparts in aerospace applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"189-194"},"PeriodicalIF":2.5,"publicationDate":"2025-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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