Pub Date : 2025-03-19DOI: 10.1109/TDMR.2025.3544351
Luca Cassano;Mihalis Psarakis
The ten articles in this special issue present innovative research in the field of defect and fault tolerance in VLSI and nanotechnology systems and provide readers with valuable insights into the latest advances and future trends in these challenging research areas. The focus of these articles is on the reliability in the design, technology and testing of electronic devices and systems, integrated circuits, printed modules, as well as methodologies and tools used for reliability and security prediction, verification and design validation.
{"title":"Special Issue on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS 2023) in the IEEE Transactions on Device and Materials Reliability","authors":"Luca Cassano;Mihalis Psarakis","doi":"10.1109/TDMR.2025.3544351","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3544351","url":null,"abstract":"The ten articles in this special issue present innovative research in the field of defect and fault tolerance in VLSI and nanotechnology systems and provide readers with valuable insights into the latest advances and future trends in these challenging research areas. The focus of these articles is on the reliability in the design, technology and testing of electronic devices and systems, integrated circuits, printed modules, as well as methodologies and tools used for reliability and security prediction, verification and design validation.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"2-3"},"PeriodicalIF":2.5,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10934089","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper investigates three Silicon Controlled Rectifier (SCR) devices employing different shunting methods to enhance the holding voltage and prevent latch-up. The operating principles of these devices are analyzed using equivalent circuits and two-dimensional (2D) device simulations, while the device performance is validated through Transmission Line Pulse (TLP) testing and curve tracer characterization. The Weak Snapback SCR (WSSCR), utilizing the third shunting method, achieves the highest holding voltage (Vh) of 7.12 V while maintaining a trigger voltage as low as 8.92 V, fully meeting the 5V ESD design requirements. Meanwhile, during high-temperature and long-pulse-width TLP testing, its Vh remains above 5.5V, meeting the latch-up immunity requirement. The WSSCR exhibits unique double-snapback characteristics. Such feature is explained by analyzing transient waveforms at various points during the TLP test and Technology Computer Aided Design (TCAD) simulations.
{"title":"Weak Snapback Silicon Controlled Rectifier ESD Device With Double Snapback Characteristics","authors":"Zhong-Xin Wu;Yang Wang;Shuo-Xin Ji;Jun Deng;Zhen-Dong Tang","doi":"10.1109/TDMR.2025.3571056","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3571056","url":null,"abstract":"This paper investigates three Silicon Controlled Rectifier (SCR) devices employing different shunting methods to enhance the holding voltage and prevent latch-up. The operating principles of these devices are analyzed using equivalent circuits and two-dimensional (2D) device simulations, while the device performance is validated through Transmission Line Pulse (TLP) testing and curve tracer characterization. The Weak Snapback SCR (WSSCR), utilizing the third shunting method, achieves the highest holding voltage (Vh) of 7.12 V while maintaining a trigger voltage as low as 8.92 V, fully meeting the 5V ESD design requirements. Meanwhile, during high-temperature and long-pulse-width TLP testing, its Vh remains above 5.5V, meeting the latch-up immunity requirement. The WSSCR exhibits unique double-snapback characteristics. Such feature is explained by analyzing transient waveforms at various points during the TLP test and Technology Computer Aided Design (TCAD) simulations.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"401-409"},"PeriodicalIF":2.3,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-19DOI: 10.1109/TDMR.2025.3549656
{"title":"IEEE Transactions on Device and Materials Reliability Publication Information","authors":"","doi":"10.1109/TDMR.2025.3549656","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3549656","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"C2-C2"},"PeriodicalIF":2.5,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10934086","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-19DOI: 10.1109/TDMR.2025.3551112
{"title":"Exploration of the exciting world of multifunctional oxide-based electronic devices: from material to system-level applications","authors":"","doi":"10.1109/TDMR.2025.3551112","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3551112","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"177-178"},"PeriodicalIF":2.5,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10934109","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143654925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-19DOI: 10.1109/TDMR.2025.3551111
{"title":"Wide Band Gap Semiconductors for Automotive Applications","authors":"","doi":"10.1109/TDMR.2025.3551111","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3551111","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"175-176"},"PeriodicalIF":2.5,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10934110","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143655005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
High-temperature dc and ac capacitance dispersion analysis of the double-$pi $ gate AlGaN/GaN high electron mobility transistor (HEMT) is simulated to analyze the trapping effects. Self-heating phenomena in electronic devices degrade both performance and lifetime. Self-heating effects (SHE) lead to a rise in channel temperature, which directly impacts the bandgap (EG), mobility of the electrons ($mu _{e}$ ), electron saturation velocity (Vsat), threshold voltage (VTH), breakdown voltage (VBD), transconductance (gm), drain saturation current (IDS), output power (Pout) as well as memory effects and noise performance. To mitigate self-heating effects, a new double-$pi $ gate HEMT is designed with the gate stem divided into three pillars. This structure redistributes the electric field and reduces phonon scattering. Notably, the device current collapse (CC) percentage drastically decreased when operated at high temperature. Capacitance dispersion is simulated using 2-D TCAD across ambient temperatures ranging from 253°K to 1098°K. Simulation results showed minimal hot electron generation and trapping effects at extreme temperatures. A slight kink effect is observed at temperatures above 773°K for gate stem distances greater than 150 nm.
{"title":"Analysis of Trapping Mechanisms and Capacitance Dispersion in Double-π Gate AlGaN/GaN HEMTs Under High-Temperature Conditions","authors":"Rayabarapu Venkateswarlu;Bibhudendra Acharya;Guru Prasad Mishra","doi":"10.1109/TDMR.2025.3570841","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3570841","url":null,"abstract":"High-temperature dc and ac capacitance dispersion analysis of the double-<inline-formula> <tex-math>$pi $ </tex-math></inline-formula> gate AlGaN/GaN high electron mobility transistor (HEMT) is simulated to analyze the trapping effects. Self-heating phenomena in electronic devices degrade both performance and lifetime. Self-heating effects (SHE) lead to a rise in channel temperature, which directly impacts the bandgap (EG), mobility of the electrons (<inline-formula> <tex-math>$mu _{e}$ </tex-math></inline-formula>), electron saturation velocity (Vsat), threshold voltage (VTH), breakdown voltage (VBD), transconductance (gm), drain saturation current (IDS), output power (Pout) as well as memory effects and noise performance. To mitigate self-heating effects, a new double-<inline-formula> <tex-math>$pi $ </tex-math></inline-formula> gate HEMT is designed with the gate stem divided into three pillars. This structure redistributes the electric field and reduces phonon scattering. Notably, the device current collapse (CC) percentage drastically decreased when operated at high temperature. Capacitance dispersion is simulated using 2-D TCAD across ambient temperatures ranging from 253°K to 1098°K. Simulation results showed minimal hot electron generation and trapping effects at extreme temperatures. A slight kink effect is observed at temperatures above 773°K for gate stem distances greater than 150 nm.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"574-584"},"PeriodicalIF":2.3,"publicationDate":"2025-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Junction temperature $(T_{j})$ estimation is critical for the health status and reliable operation of SiC MOSFET. Thermal sensitivity electrical parameter (TSEP) method will affect the accuracy of the estimation results due to the measurement conditions, while thermal model method can cause large deviation in the estimation results due to the aging effect of SiC MOSFET. In this paper, a Kalman filter method based on adaptive thermal model is proposed for online $T_{j}$ estimation of SiC MOSFET. This method proposes the principle of updating the thermal model after device aging, and corrects the model parameter change of SiC MOSFET due to aging in real time by continuously updating the thermal model, and then estimates $T_{j}$ by combining the TSEP method and the Kalman filter finally. The method not only has the advantages of the TSEP method and the thermal model method, but also can monitor the aging of the device, eliminate the estimation errors generated by the measurement process and inaccurate thermal model, and effectively improve the accuracy and reliability of the online $T_{j}$ estimation. The experimental results verify the effectiveness of the proposed method.
{"title":"A Kalman Filter Method Based on Adaptive Thermal Model for Online Junction Temperature Estimation of SiC MOSFET","authors":"Zehua Fu;Wei Wu;Yong Chen;Zhangyong Chen;Xin Tong;Lehan Xu","doi":"10.1109/TDMR.2025.3570281","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3570281","url":null,"abstract":"Junction temperature <inline-formula> <tex-math>$(T_{j})$ </tex-math></inline-formula> estimation is critical for the health status and reliable operation of SiC MOSFET. Thermal sensitivity electrical parameter (TSEP) method will affect the accuracy of the estimation results due to the measurement conditions, while thermal model method can cause large deviation in the estimation results due to the aging effect of SiC MOSFET. In this paper, a Kalman filter method based on adaptive thermal model is proposed for online <inline-formula> <tex-math>$T_{j}$ </tex-math></inline-formula> estimation of SiC MOSFET. This method proposes the principle of updating the thermal model after device aging, and corrects the model parameter change of SiC MOSFET due to aging in real time by continuously updating the thermal model, and then estimates <inline-formula> <tex-math>$T_{j}$ </tex-math></inline-formula> by combining the TSEP method and the Kalman filter finally. The method not only has the advantages of the TSEP method and the thermal model method, but also can monitor the aging of the device, eliminate the estimation errors generated by the measurement process and inaccurate thermal model, and effectively improve the accuracy and reliability of the online <inline-formula> <tex-math>$T_{j}$ </tex-math></inline-formula> estimation. The experimental results verify the effectiveness of the proposed method.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"557-566"},"PeriodicalIF":2.3,"publicationDate":"2025-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nowadays, electro-thermal transport behavior analyzing is important in emerging nanoscale devices because thermal management is a critical issue in improving the device’s performance and cooling strategies. In this article, a comparative study for electro-thermal performance analysis of junctionless and an inversion-mode nanowire gate-all-around (GAA) field-effect transistors (FETs) is presented in advanced technology nodes by considering nonlocal effects. The junctionless device showed ~15.2% better thermal reliability and ~26.7%/37.6% better HCI/BTI lifetime compared to the inversion-mode device. The transient behavior of electro-thermal reliability is also investigated for both devices, where the devices turn on for a short time within a duty cycle, the devices showed better thermal reliability and ~52.8%/68.2% HCI/BTI lifetime improvement. This study also provides strategies for thermal management in advanced node devices.
{"title":"Impact of Electro-Thermal Transport on HCI and BTI Lifetime of Twin Nanowire FETs: Different Operational Modes","authors":"Nitish Kumar;Sankatali Venkateswarlu;Ankur Gupta;Pushpapraj Singh","doi":"10.1109/TDMR.2025.3570616","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3570616","url":null,"abstract":"Nowadays, electro-thermal transport behavior analyzing is important in emerging nanoscale devices because thermal management is a critical issue in improving the device’s performance and cooling strategies. In this article, a comparative study for electro-thermal performance analysis of junctionless and an inversion-mode nanowire gate-all-around (GAA) field-effect transistors (FETs) is presented in advanced technology nodes by considering nonlocal effects. The junctionless device showed ~15.2% better thermal reliability and ~26.7%/37.6% better HCI/BTI lifetime compared to the inversion-mode device. The transient behavior of electro-thermal reliability is also investigated for both devices, where the devices turn on for a short time within a duty cycle, the devices showed better thermal reliability and ~52.8%/68.2% HCI/BTI lifetime improvement. This study also provides strategies for thermal management in advanced node devices.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"567-573"},"PeriodicalIF":2.3,"publicationDate":"2025-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-14DOI: 10.1109/TDMR.2025.3567107
Shuai Zhu;Maoliang Jian;Xiaoni Yang;Liang Chen;Li Deng;Lianqiao Yang
Insulated Gate Bipolar Transistors (IGBTs) are extensively utilized in a multitude of fields owing to their proficiency in power conversion and their dependable operation. Anticipating the service life of IGBTs to preemptively mitigate the repercussions of device failure, this research advances a novel lifespan forecasting methodology underpinned by a Convolutional Neural Network (CNN) and Transformer hybrid model. The methodology commences with accelerated aging power cycling tests within a range of temperature thresholds, utilizing the Siemens Power Tester to gather aging parameters at disparate junction temperatures. A pivotal observation is the alteration of the saturated voltage drop, VCE(ON), throughout the aging process, which is then harnessed as a critical aging indicator for model training. Following this, the accrued datasets from three distinct groups undergo a rigorous preprocessing phase. Subsequently, the proposed forecasting technique is deployed to predict lifespan across varying operating conditions. The empirical findings underscore that the model introduced in this paper, when predicated on the variations in saturated voltage drop, achieves markedly enhanced predictive fidelity in both single-step and multi-step forecasting scenarios, outperforming alternative comparative methodologies. Especially in single step prediction, the mean values of the coefficient of determination (R2), mean absolute error (MAE), and root mean square error (RMSE) are 0.996, 0.0016 and 0.0026, respectively.
{"title":"Life Prediction of IGBT Across Working Condition via a CNN-Transformer Network","authors":"Shuai Zhu;Maoliang Jian;Xiaoni Yang;Liang Chen;Li Deng;Lianqiao Yang","doi":"10.1109/TDMR.2025.3567107","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3567107","url":null,"abstract":"Insulated Gate Bipolar Transistors (IGBTs) are extensively utilized in a multitude of fields owing to their proficiency in power conversion and their dependable operation. Anticipating the service life of IGBTs to preemptively mitigate the repercussions of device failure, this research advances a novel lifespan forecasting methodology underpinned by a Convolutional Neural Network (CNN) and Transformer hybrid model. The methodology commences with accelerated aging power cycling tests within a range of temperature thresholds, utilizing the Siemens Power Tester to gather aging parameters at disparate junction temperatures. A pivotal observation is the alteration of the saturated voltage drop, VCE(ON), throughout the aging process, which is then harnessed as a critical aging indicator for model training. Following this, the accrued datasets from three distinct groups undergo a rigorous preprocessing phase. Subsequently, the proposed forecasting technique is deployed to predict lifespan across varying operating conditions. The empirical findings underscore that the model introduced in this paper, when predicated on the variations in saturated voltage drop, achieves markedly enhanced predictive fidelity in both single-step and multi-step forecasting scenarios, outperforming alternative comparative methodologies. Especially in single step prediction, the mean values of the coefficient of determination (R2), mean absolute error (MAE), and root mean square error (RMSE) are 0.996, 0.0016 and 0.0026, respectively.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"195-202"},"PeriodicalIF":2.5,"publicationDate":"2025-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-14DOI: 10.1109/TDMR.2025.3570099
Yaohua Xu;Zeteng Liu;Yi Wang;Na Bai;Ye Liu
The standard cell library forms the foundation of chip design. Conducting rational and efficient radiation-hardening design and performance verification for the library is essential to ensure the safe on-orbit operation of aerospace components. This paper investigates the resettable dual interlocked storage cell (DICE) flip-flop (DICE-FF) from a radiation-hardened cell library and proposes a flip-flop (DICE-REFF) with reset-redundant control circuitry to improve its radiation tolerance. The study examines the effects of Single Event Upset (SEU) both before and after the redundancy hardening of the reset control, identifying sensitive layout regions and critical circuit nodes. Simulations show that the redundancy-hardened DICE-REFF demonstrates strong SEU tolerance, with a Linear Energy Transfer (LET) threshold of 37 MeV/mg/cm2. Additionally, the circuit area increased by only 5% compared to the non-hardened design, with no loss in performance. Additionally, a test chip was designed, and the SEU resistance of the flip-flop was validated through both fault injection and irradiation experiment. The study also explores the impact of different implementation strategies on fault rates.
{"title":"A DICE Flip-Flop Design by Resetting Redundancy Hardening for Single Event Upset Tolerance","authors":"Yaohua Xu;Zeteng Liu;Yi Wang;Na Bai;Ye Liu","doi":"10.1109/TDMR.2025.3570099","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3570099","url":null,"abstract":"The standard cell library forms the foundation of chip design. Conducting rational and efficient radiation-hardening design and performance verification for the library is essential to ensure the safe on-orbit operation of aerospace components. This paper investigates the resettable dual interlocked storage cell (DICE) flip-flop (DICE-FF) from a radiation-hardened cell library and proposes a flip-flop (DICE-REFF) with reset-redundant control circuitry to improve its radiation tolerance. The study examines the effects of Single Event Upset (SEU) both before and after the redundancy hardening of the reset control, identifying sensitive layout regions and critical circuit nodes. Simulations show that the redundancy-hardened DICE-REFF demonstrates strong SEU tolerance, with a Linear Energy Transfer (LET) threshold of 37 MeV/mg/cm2. Additionally, the circuit area increased by only 5% compared to the non-hardened design, with no loss in performance. Additionally, a test chip was designed, and the SEU resistance of the flip-flop was validated through both fault injection and irradiation experiment. The study also explores the impact of different implementation strategies on fault rates.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"501-509"},"PeriodicalIF":2.3,"publicationDate":"2025-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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