Pub Date : 2024-04-04DOI: 10.1109/TNANO.2024.3384968
Tian-Tong Cheng;Qiang Li;Yu-Xi Yang;Zhi-Wei Zheng
As the negative capacitance field-effect transistors (NCFETs) have extensive application prospects and advanced technological support in the analog/radio-frequency (RF) domains, it is important to investigate the theoretical performances of the NCFETs with various feasible structures. In this article, utilizing the TCAD simulation tool and an experimentally calibrated ferroelectric model, we perform a comparative evaluation of MFMIS and MFIS, two prominent NCFET configurations, with regard to their DC/static characteristics and analog/RF performances. Through simulations involving varying ferroelectric thicknesses, it is seen that in comparison with the MFIS device, the MFMIS device demonstrates superior static performances in on-state current ( I ON ), off-state current ( I OFF ) and subthreshold swing ( SS ), and the underlying physical effects of these results have also been uncovered. Furthermore, we extracted the device-level analog/RF figures of merits (FoMs) like transconductance ( g m ), gate capacitance ( C gg ), output conductance ( g d ), cutoff frequency ( f T ), transconductance generation factor ( TGF ), transconductance frequency product ( TFP ), etc from the two structures. It is found that the MFMIS device still possesses advantages in these parameters, and as the thickness of ferroelectric layer increases, the advantages compared to the MFIS device become more pronounced. The investigations in this article indicate that the MFMIS NCFET exhibits superior adaptability and performances in enhancing the analog/RF capabilities of conventional devices as compared with the MFIS device.
{"title":"Comparative Evaluation of Ferroelectric Negative Capacitance MFMIS and MFIS Transistors for Analog/Radio-Frequency Applications","authors":"Tian-Tong Cheng;Qiang Li;Yu-Xi Yang;Zhi-Wei Zheng","doi":"10.1109/TNANO.2024.3384968","DOIUrl":"10.1109/TNANO.2024.3384968","url":null,"abstract":"As the negative capacitance field-effect transistors (NCFETs) have extensive application prospects and advanced technological support in the analog/radio-frequency (RF) domains, it is important to investigate the theoretical performances of the NCFETs with various feasible structures. In this article, utilizing the TCAD simulation tool and an experimentally calibrated ferroelectric model, we perform a comparative evaluation of MFMIS and MFIS, two prominent NCFET configurations, with regard to their DC/static characteristics and analog/RF performances. Through simulations involving varying ferroelectric thicknesses, it is seen that in comparison with the MFIS device, the MFMIS device demonstrates superior static performances in on-state current (\u0000<italic>I</i>\u0000<sub>ON</sub>\u0000), off-state current (\u0000<italic>I</i>\u0000<sub>OFF</sub>\u0000) and subthreshold swing (\u0000<italic>SS</i>\u0000), and the underlying physical effects of these results have also been uncovered. Furthermore, we extracted the device-level analog/RF figures of merits (FoMs) like transconductance (\u0000<italic>g</i>\u0000<sub>m</sub>\u0000), gate capacitance (\u0000<italic>C</i>\u0000<sub>gg</sub>\u0000), output conductance (\u0000<italic>g</i>\u0000<sub>d</sub>\u0000), cutoff frequency (\u0000<italic>f</i>\u0000<sub>T</sub>\u0000), transconductance generation factor (\u0000<italic>TGF</i>\u0000), transconductance frequency product (\u0000<italic>TFP</i>\u0000), etc from the two structures. It is found that the MFMIS device still possesses advantages in these parameters, and as the thickness of ferroelectric layer increases, the advantages compared to the MFIS device become more pronounced. The investigations in this article indicate that the MFMIS NCFET exhibits superior adaptability and performances in enhancing the analog/RF capabilities of conventional devices as compared with the MFIS device.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"317-322"},"PeriodicalIF":2.4,"publicationDate":"2024-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140603422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The production and verification of microwave absorbers are a subject of high priority. These are due to the fast development of telecommunication technologies and the need to reduce electromagnetic pollution. Such materials are implementable in multiple industries, including military, medical, and laboratory equipment. One should remember that the desired material should exhibit a high total shielding effectiveness SE $_{T}$ and controllable performance properties. In this work, an ultrathin graphene oxide paper is fabricated and verified as a wide-range, controllable microwave absorber. Stepwise (100 $^circ$ C – 200 $^circ$ C – 300 $^circ$ C) thermally reduced G-Flake graphene oxide paper of 4.95 μm thickness revealed the conductivity of 1.86 S/cm. A mild level of reduction was proven with combustion elemental analysis, resulting in a 22.4 oxygen percentage (50.9 % before the reduction). Raman spectroscopy suggested the limitation of Stone-Wales defects after heat treatment. Microwave absorption was measured in the W-band frequency region, and the SE$_{T}$/t parameter reached 606 dB/mm for a c.a. 5-μm-thick individual reduced paper sheet. The controlled increase in conductivity resulted in conduction losses, and the occurrence of pores enabled scattering, while the absorption remained the primary shielding mechanism.
{"title":"Graphene Oxide Paper as a Lightweight, Thin, and Controllable Microwave Absorber for Millimeter-Wave Applications","authors":"Agata Romanowska;Stefan Marynowicz;Tomasz Strachowski;Konrad Godziszewski;Yevhen Yashchyshyn;Adrian Racki;Magdalena Baran;Tymoteusz Ciuk;Adrian Chlanda","doi":"10.1109/TNANO.2024.3385092","DOIUrl":"10.1109/TNANO.2024.3385092","url":null,"abstract":"The production and verification of microwave absorbers are a subject of high priority. These are due to the fast development of telecommunication technologies and the need to reduce electromagnetic pollution. Such materials are implementable in multiple industries, including military, medical, and laboratory equipment. One should remember that the desired material should exhibit a high total shielding effectiveness \u0000<italic>SE <inline-formula><tex-math>$_{T}$</tex-math></inline-formula></i>\u0000 and controllable performance properties. In this work, an ultrathin graphene oxide paper is fabricated and verified as a wide-range, controllable microwave absorber. Stepwise (100 \u0000<inline-formula><tex-math>$^circ$</tex-math></inline-formula>\u0000 C – 200 \u0000<inline-formula><tex-math>$^circ$</tex-math></inline-formula>\u0000C – 300 \u0000<inline-formula><tex-math>$^circ$</tex-math></inline-formula>\u0000C) thermally reduced G-Flake graphene oxide paper of 4.95 μm thickness revealed the conductivity of 1.86 S/cm. A mild level of reduction was proven with combustion elemental analysis, resulting in a 22.4 oxygen percentage (50.9 % before the reduction). Raman spectroscopy suggested the limitation of Stone-Wales defects after heat treatment. Microwave absorption was measured in the W-band frequency region, and the \u0000<italic>SE<inline-formula><tex-math>$_{T}$</tex-math></inline-formula>/t</i>\u0000 parameter reached 606 dB/mm for a c.a. 5-μm-thick individual reduced paper sheet. The controlled increase in conductivity resulted in conduction losses, and the occurrence of pores enabled scattering, while the absorption remained the primary shielding mechanism.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"329-337"},"PeriodicalIF":2.4,"publicationDate":"2024-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140596735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The study proposed simple methods with hydrothermal method and physical vapor deposition coating technique (sputter coater) to prepare Pt nanoparticles attach on ZnO nanorods, and then applied in non-enzymatic glucose sensor. Glucose sensing is tested using electrochemical measurement, including cyclic voltammetry and amperometry method. In cyclic voltammetry measurement, the sensitivity of ZnO and Pt/ZnO NRs sensor are 5.0273 and 32.0527 μA/cm 2 -mM when an applied potential at 0.1 V, which is carried out different glucose concentration from 0 mM to 8 mM. For observing the stability and selectivity, we were used the amperometry method to measure various glucose concentration and interfering species (ascorbic acid and uric acid). It is demonstrated that the Pt/ZnO NRs sensor exhibited excellent stability and anti-interference performance.
{"title":"Improved Non-enzymatic Glucose Sensors of ZnO Nanorods by Adsorb Pt Nanoparticles","authors":"Yi-Hsing Liu;Sheng-Joue Young;Cheng-Yen Hsien;Yen-Lin Chu;Zi-Hao Wang;Shoou-Jinn Chang","doi":"10.1109/TNANO.2024.3382635","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3382635","url":null,"abstract":"The study proposed simple methods with hydrothermal method and physical vapor deposition coating technique (sputter coater) to prepare Pt nanoparticles attach on ZnO nanorods, and then applied in non-enzymatic glucose sensor. Glucose sensing is tested using electrochemical measurement, including cyclic voltammetry and amperometry method. In cyclic voltammetry measurement, the sensitivity of ZnO and Pt/ZnO NRs sensor are 5.0273 and 32.0527 μA/cm\u0000<sup>2</sup>\u0000-mM when an applied potential at 0.1 V, which is carried out different glucose concentration from 0 mM to 8 mM. For observing the stability and selectivity, we were used the amperometry method to measure various glucose concentration and interfering species (ascorbic acid and uric acid). It is demonstrated that the Pt/ZnO NRs sensor exhibited excellent stability and anti-interference performance.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"303-310"},"PeriodicalIF":2.4,"publicationDate":"2024-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140544184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this letter, we have successfully fabricated a metal-ferroelectricity-metal (MFM) capacitor of an ultrathin 5 nm HZO utilizing Molybdenum (Mo) as the electrodes. By proposing a novel atomic layer deposition (ALD) scheme, we overcome the challenge of oxidation of the lower Mo electrode; a 2 nm HZO deposited by thermally enhanced ALD followed by a 3 nm HZO deposited by plasma enhanced ALD. The fabricated sample demonstrated a 2Pr value of 38.5 μC/cm 2 at an operating voltage of 2 V. Furthermore, in endurance testing, the sample maintained a 2Pr value of 36.9 μC/cm 2 even after 10 10 cycles (△2Pr/2Pr pristine ≈ 7% from pristine to 10 10 cycles). With a maximum process temperature of 400 °C, our approach thereby meets the stringent requirement of Back-End-of-Line (BEOL) integration.
{"title":"BEOL-Compatible Ferroelectric Capacitor of 5 nm Ultrathin HZO With High Remanent Polarization and Excellent Endurance","authors":"Li-Cheng Teng;Yu-Che Huang;Shu-Jui Chang;Shin-Yuan Wang;Yu-Hsien Lin;Chao-Hsin Chien","doi":"10.1109/TNANO.2024.3407817","DOIUrl":"10.1109/TNANO.2024.3407817","url":null,"abstract":"In this letter, we have successfully fabricated a metal-ferroelectricity-metal (MFM) capacitor of an ultrathin 5 nm HZO utilizing Molybdenum (Mo) as the electrodes. By proposing a novel atomic layer deposition (ALD) scheme, we overcome the challenge of oxidation of the lower Mo electrode; a 2 nm HZO deposited by thermally enhanced ALD followed by a 3 nm HZO deposited by plasma enhanced ALD. The fabricated sample demonstrated a 2Pr value of 38.5 μC/cm\u0000<sup>2</sup>\u0000 at an operating voltage of 2 V. Furthermore, in endurance testing, the sample maintained a 2Pr value of 36.9 μC/cm\u0000<sup>2</sup>\u0000 even after 10\u0000<sup>10</sup>\u0000 cycles (△2Pr/2Pr\u0000<sub>pristine</sub>\u0000 ≈ 7% from pristine to 10\u0000<sup>10</sup>\u0000 cycles). With a maximum process temperature of 400 °C, our approach thereby meets the stringent requirement of Back-End-of-Line (BEOL) integration.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"474-477"},"PeriodicalIF":2.1,"publicationDate":"2024-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141196645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this study, a novel composite material, g-C 3 N 4 - NiS (CN-NiS), was synthesized by the hydrothermal method through the combination of graphitic carbon nitride (g-C 3 N 4 ) and nickel sulfide (NiS). Furthermore, an electrospinning technique was employed to incorporate CN-NiS into titanium dioxide (TiO 2 ) nanofibers, resulting in the formation of a new type of composite nanofibers (CN-NiS/TiO 2 NFs) to be used as a photoanode in dye-sensitized solar cells (DSSCs). The nanomaterial was characterized, and the charge recombination and performance of the device after modifying the photoanode were evaluated. Firstly, the photovoltaic performance of the modified DSSCs under outdoor illumination (AM 1.5G) was examined. The photoanode with CN-NiS/TiO 2 NFs achieved an 6.65% photoelectric conversion efficiency (PCE), demonstrating significant improvement compared to the unmodified DSSCs. Additionally, the PCE of CN-NiS/TiO 2 NFs photoanode under indoor illumination (T5 fluorescent lamp) reached a maximum of 25.10%.
{"title":"Preparation of Dye-Sensitized Solar Cell With Modification of Photoanode by g-C3N4/NiS/TiO2 Nanofibers and Its Performance Under Outdoor and Indoor Illumination","authors":"Yu-Hsun Nien;Shang-Wen Zhuang;Jung-Chuan Chou;Chih-Hsien Lai;Po-Hui Yang;Po-Yu Kuo;Po-Feng Chen;Yu-Han Huang","doi":"10.1109/TNANO.2024.3407375","DOIUrl":"10.1109/TNANO.2024.3407375","url":null,"abstract":"In this study, a novel composite material, g-C\u0000<sub>3</sub>\u0000N\u0000<sub>4</sub>\u0000 - NiS (CN-NiS), was synthesized by the hydrothermal method through the combination of graphitic carbon nitride (g-C\u0000<sub>3</sub>\u0000N\u0000<sub>4</sub>\u0000) and nickel sulfide (NiS). Furthermore, an electrospinning technique was employed to incorporate CN-NiS into titanium dioxide (TiO\u0000<sub>2</sub>\u0000) nanofibers, resulting in the formation of a new type of composite nanofibers (CN-NiS/TiO\u0000<sub>2</sub>\u0000 NFs) to be used as a photoanode in dye-sensitized solar cells (DSSCs). The nanomaterial was characterized, and the charge recombination and performance of the device after modifying the photoanode were evaluated. Firstly, the photovoltaic performance of the modified DSSCs under outdoor illumination (AM 1.5G) was examined. The photoanode with CN-NiS/TiO\u0000<sub>2</sub>\u0000 NFs achieved an 6.65% photoelectric conversion efficiency (PCE), demonstrating significant improvement compared to the unmodified DSSCs. Additionally, the PCE of CN-NiS/TiO\u0000<sub>2</sub>\u0000 NFs photoanode under indoor illumination (T5 fluorescent lamp) reached a maximum of 25.10%.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"427-434"},"PeriodicalIF":2.4,"publicationDate":"2024-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141196633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tunnel Field-Effect Transistors (TFETs) offer more energy efficient alternative to CMOS for design of low power circuits. In spite of this potential, circuits based on TFETs have not been experimentally demonstrated so far. In this letter, we explore TFET fabrication and basic functionality of n-TFET based circuits in the following configurations: a current mirror, a diode-connected inverter, and a cascode. Individual TFETs in the circuit operate well below 60 mV/dec operation with minimum achieved subthreshold swing (SS) of 30 mV/dec at drain voltage of 400 mV. To analyse the circuit operation, individual devices are connected via FEOL and are biased at 300 mV supply voltage, with an input frequency of 200 kHz. The measured circuit configurations demonstrate the expected functionality.
{"title":"TFET Circuit Configurations Operating Below 60 mV/dec","authors":"Gautham Rangasamy;Zhongyunshen Zhu;Lars Ohlsson Fhager;Lars-Erik Wernersson","doi":"10.1109/TNANO.2024.3407360","DOIUrl":"10.1109/TNANO.2024.3407360","url":null,"abstract":"Tunnel Field-Effect Transistors (TFETs) offer more energy efficient alternative to CMOS for design of low power circuits. In spite of this potential, circuits based on TFETs have not been experimentally demonstrated so far. In this letter, we explore TFET fabrication and basic functionality of n-TFET based circuits in the following configurations: a current mirror, a diode-connected inverter, and a cascode. Individual TFETs in the circuit operate well below 60 mV/dec operation with minimum achieved subthreshold swing (SS) of 30 mV/dec at drain voltage of 400 mV. To analyse the circuit operation, individual devices are connected via FEOL and are biased at 300 mV supply voltage, with an input frequency of 200 kHz. The measured circuit configurations demonstrate the expected functionality.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"441-447"},"PeriodicalIF":2.1,"publicationDate":"2024-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141196632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we systematically investigated the effect of oxygen treatment on the material and electrical properties of Indium-Tungsten-Oxide thin film transistors (IWO-TFTs) by O 2 plasma and rapid thermal oxidation (RTO). With RTO treatment, the electrical characteristics of the IWO-TFTs remarkably depicted a subthreshold swing ( S.S. ) of 122.5 mV/decade, an I on / I off of around 4.7×10 8 , and more superior immunity stress-induced degradation. According to the X-ray photoelectron spectroscopy (XPS) results under the RTO treatment condition, the lowest vacancy content and the highest Tungsten-Oxide (W-O) bond content were observed. It indicated that the RTO treatment was more effective in reducing the number of oxygen vacancies and stabilizing the bonding structure of IWO films. As a result, the IWO TFTs subjected to RTO treatment exhibited improved performance and enhanced reliability.
{"title":"Effect of Oxygen Treatment on the Electrical Performance and Reliability of IWO Thin-Film Transistors","authors":"Yi-Xuan Chen;Yi-Lin Wang;Fu-Jyuan Li;Shu-Jui Chang;Tsung-En Lee;Chao-Ching Cheng;Meng-Chien Lee;Hui-Hsuan Li;Yu-Hsien Lin;Chao-Hsin Chien","doi":"10.1109/TNANO.2024.3381478","DOIUrl":"10.1109/TNANO.2024.3381478","url":null,"abstract":"In this work, we systematically investigated the effect of oxygen treatment on the material and electrical properties of Indium-Tungsten-Oxide thin film transistors (IWO-TFTs) by O\u0000<sub>2</sub>\u0000 plasma and rapid thermal oxidation (RTO). With RTO treatment, the electrical characteristics of the IWO-TFTs remarkably depicted a subthreshold swing (\u0000<italic>S.S.</i>\u0000) of 122.5 mV/decade, an \u0000<italic>I</i>\u0000<sub>on</sub>\u0000/\u0000<italic>I</i>\u0000<sub>off</sub>\u0000 of around 4.7×10\u0000<sup>8</sup>\u0000, and more superior immunity stress-induced degradation. According to the X-ray photoelectron spectroscopy (XPS) results under the RTO treatment condition, the lowest vacancy content and the highest Tungsten-Oxide (W-O) bond content were observed. It indicated that the RTO treatment was more effective in reducing the number of oxygen vacancies and stabilizing the bonding structure of IWO films. As a result, the IWO TFTs subjected to RTO treatment exhibited improved performance and enhanced reliability.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"299-302"},"PeriodicalIF":2.4,"publicationDate":"2024-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140300280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-23DOI: 10.1109/TNANO.2024.3404615
E. Amat;A. del Moral;J. Bausells;F. Perez-Murano
Stacking devices in a 3D configuration by using a vertical topology is considered as the next step to improve electronic devices and circuits performance. For instance, a CMOS inverted can be built by continuously depositing both inter-metal and metal layers. This new IC manufacturing proposal has been simulated by using Sentaurus 3D TCAD software. We have analyzed the influence of different device design parameters to optimize its performance. Finally, we have also explored the feasibility to implement a 5-stage ring oscillator circuit by using the proposed stack.
利用垂直拓扑结构在三维配置中堆叠器件被认为是提高电子器件和电路性能的下一步。例如，可以通过连续沉积金属间层和金属层来制造 CMOS 反相器。我们使用 Sentaurus 3D TCAD 软件模拟了这种新的集成电路制造方案。我们分析了不同器件设计参数的影响，以优化其性能。最后，我们还探讨了利用所提出的叠层实现 5 级环形振荡器电路的可行性。
{"title":"Exploring the Suitability of Stacking Devices in a Vertical Nanowire to Implement a CMOS Inverter","authors":"E. Amat;A. del Moral;J. Bausells;F. Perez-Murano","doi":"10.1109/TNANO.2024.3404615","DOIUrl":"10.1109/TNANO.2024.3404615","url":null,"abstract":"Stacking devices in a 3D configuration by using a vertical topology is considered as the next step to improve electronic devices and circuits performance. For instance, a CMOS inverted can be built by continuously depositing both inter-metal and metal layers. This new IC manufacturing proposal has been simulated by using Sentaurus 3D TCAD software. We have analyzed the influence of different device design parameters to optimize its performance. Finally, we have also explored the feasibility to implement a 5-stage ring oscillator circuit by using the proposed stack.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"435-440"},"PeriodicalIF":2.4,"publicationDate":"2024-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141146069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-22DOI: 10.1109/TNANO.2024.3381008
Alex Henderson;Chris Yakopcic;Cory Merkel;Hananel Hazan;Steven Harbour;Tarek M. Taha
Spiking neural network (SNN) hardware has gained significant interest due to its ability to process complex data in size, weight, and power (SWaP) constrained environments. Memristors, in particular, offer the potential to enhance SNN algorithms by providing analog domain acceleration with exceptional energy and throughput efficiency. Among the current SNN architectures, the Liquid State Machine (LSM), a form of Reservoir Computing (RC), stands out due to its low resource utilization and straightforward training process. In this paper, we present a custom memristor-based LSM circuit design with an online learning methodology. The proposed circuit implementing the LSM is designed using SPICE to ensure precise device level accuracy. Furthermore, we explore liquid connectivity tuning to facilitate a real-time and efficient design process. To assess the performance of our system, we evaluate it on multiple datasets, including MNIST, TI-46 spoken digits, acoustic drone recordings, and musical MIDI files. Our results demonstrate comparable accuracy while achieving significant power and energy savings when compared to existing LSM accelerators. Moreover, our design exhibits resilience in the presence of noise and neuron misfires. These findings highlight the potential of a memristor based LSM architecture to rival purely CMOS-based LSM implementations, offering robust and energy-efficient neuromorphic computing capabilities with memristive SNNs.
{"title":"Memristor Based Liquid State Machine With Method for In-Situ Training","authors":"Alex Henderson;Chris Yakopcic;Cory Merkel;Hananel Hazan;Steven Harbour;Tarek M. Taha","doi":"10.1109/TNANO.2024.3381008","DOIUrl":"10.1109/TNANO.2024.3381008","url":null,"abstract":"Spiking neural network (SNN) hardware has gained significant interest due to its ability to process complex data in size, weight, and power (SWaP) constrained environments. Memristors, in particular, offer the potential to enhance SNN algorithms by providing analog domain acceleration with exceptional energy and throughput efficiency. Among the current SNN architectures, the Liquid State Machine (LSM), a form of Reservoir Computing (RC), stands out due to its low resource utilization and straightforward training process. In this paper, we present a custom memristor-based LSM circuit design with an online learning methodology. The proposed circuit implementing the LSM is designed using SPICE to ensure precise device level accuracy. Furthermore, we explore liquid connectivity tuning to facilitate a real-time and efficient design process. To assess the performance of our system, we evaluate it on multiple datasets, including MNIST, TI-46 spoken digits, acoustic drone recordings, and musical MIDI files. Our results demonstrate comparable accuracy while achieving significant power and energy savings when compared to existing LSM accelerators. Moreover, our design exhibits resilience in the presence of noise and neuron misfires. These findings highlight the potential of a memristor based LSM architecture to rival purely CMOS-based LSM implementations, offering robust and energy-efficient neuromorphic computing capabilities with memristive SNNs.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"376-385"},"PeriodicalIF":2.4,"publicationDate":"2024-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140203927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-22DOI: 10.1109/TNANO.2024.3380997
Rebecca Ho;Samuel Fuller;Hae-Seung Lee;Max M. Shulaker
Emerging technologies, such as carbon nanotubes (CNTs), show exciting benefits for next-generation electronic systems and have recently been incorporated within commercial fabrication facilities and foundries. Here we demonstrate a real-world application of carbon nanotube field-effect transistors (CNFETs) leveraging these foundry capabilities: performing disease diagnostics by detecting and identifying infectious pathogens in model biological samples. This Biosensor chip leverages the benefits of 200 mm wafer-scale and VLSI-compatible foundry fabrication of CNFETs, which can be seamlessly integrated with the mature sensing modality of antibody-based targeted antigen binding, to realize a robust and manufacturable biosensor technology. As a demonstration, we realize Biosensor chips that are capable of detecting and identifying three different infectious pathogens simultaneously through multiplexing across hundreds of functionalized CNFET-antibody biosensors within each chip.
{"title":"Biosensor Chip for Point-of-Care Diagnostics: Carbon Nanotube Sensing Platform for Bacterial Detection and Identification","authors":"Rebecca Ho;Samuel Fuller;Hae-Seung Lee;Max M. Shulaker","doi":"10.1109/TNANO.2024.3380997","DOIUrl":"10.1109/TNANO.2024.3380997","url":null,"abstract":"Emerging technologies, such as carbon nanotubes (CNTs), show exciting benefits for next-generation electronic systems and have recently been incorporated within commercial fabrication facilities and foundries. Here we demonstrate a real-world application of carbon nanotube field-effect transistors (CNFETs) leveraging these foundry capabilities: performing disease diagnostics by detecting and identifying infectious pathogens in model biological samples. This Biosensor chip leverages the benefits of 200 mm wafer-scale and VLSI-compatible foundry fabrication of CNFETs, which can be seamlessly integrated with the mature sensing modality of antibody-based targeted antigen binding, to realize a robust and manufacturable biosensor technology. As a demonstration, we realize Biosensor chips that are capable of detecting and identifying three different infectious pathogens simultaneously through multiplexing across hundreds of functionalized CNFET-antibody biosensors within each chip.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"281-285"},"PeriodicalIF":2.4,"publicationDate":"2024-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140203616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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