Pub Date : 2024-06-03DOI: 10.1109/TSM.2024.3404475
Youcheng Wang;Zhuo Chen;Cong Wang;Nick Keller;G. Andrew Antonelli;Zhuan Liu;Troy Ribaudo;Rostislav Grynko
Three dimensional Not-And (3D NAND) flash memory devices are scaling in the vertical direction to more than 200 oxide/sacrificial wordline nitride layers to further increase storage capacity and enhance energy efficiency. The accurate measurement of the thicknesses of these layers is critical to controlling stress-induced wafer warping and pattern distortion. While traditional optical metrology in the UV-vis-NIR range offers a non-destructive inline solution for high volume manufacturing, we demonstrate in this paper, that mid-IR metrology has advantages in de-correlating oxide and nitride thicknesses owing to their unique absorption signatures. Furthermore, because of the depths sensitivity of oxide and nitride absorptions, the simulated measurement results show the ability to differentiate thickness variations in the vertical zones. Good blind test results were obtained with a machine learning model trained on pseudo-references and pseudo spectra with added skew.
{"title":"3-D NAND Oxide/Nitride Tier Stack Thickness and Zonal Measurements With Infrared Metrology","authors":"Youcheng Wang;Zhuo Chen;Cong Wang;Nick Keller;G. Andrew Antonelli;Zhuan Liu;Troy Ribaudo;Rostislav Grynko","doi":"10.1109/TSM.2024.3404475","DOIUrl":"10.1109/TSM.2024.3404475","url":null,"abstract":"Three dimensional Not-And (3D NAND) flash memory devices are scaling in the vertical direction to more than 200 oxide/sacrificial wordline nitride layers to further increase storage capacity and enhance energy efficiency. The accurate measurement of the thicknesses of these layers is critical to controlling stress-induced wafer warping and pattern distortion. While traditional optical metrology in the UV-vis-NIR range offers a non-destructive inline solution for high volume manufacturing, we demonstrate in this paper, that mid-IR metrology has advantages in de-correlating oxide and nitride thicknesses owing to their unique absorption signatures. Furthermore, because of the depths sensitivity of oxide and nitride absorptions, the simulated measurement results show the ability to differentiate thickness variations in the vertical zones. Good blind test results were obtained with a machine learning model trained on pseudo-references and pseudo spectra with added skew.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"244-250"},"PeriodicalIF":2.3,"publicationDate":"2024-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141942155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this study, the origin of growth pits on the surface of 4H-silicon carbide epitaxial films grown using a chemical vapor deposition reactor was clarified by evaluating the surface morphology of substrates immediately before the epitaxial growth and of epitaxial films. When the film was grown under non-optimized conditions, we found that numerous Si particles were formed on the surface of the substrate before the epitaxial growth and that the numerous growth pits on the subsequently grown epitaxial film were originated from Si particles. We observed that, by increasing the HCl flow rate through the outer nozzles in the gas inlet, which has a double-pipe structure consisting of inner and outer nozzles, the growth pit density was successfully decreased.
{"title":"Observation and Suppression of Growth Pits Formed on 4H-SiC Epitaxial Films Grown Using Halide Chemical Vapor Deposition Process","authors":"Yoshiaki Daigo;Keisuke Kurashima;Shigeaki Ishii;Ichiro Mizushima","doi":"10.1109/TSM.2024.3395361","DOIUrl":"10.1109/TSM.2024.3395361","url":null,"abstract":"In this study, the origin of growth pits on the surface of 4H-silicon carbide epitaxial films grown using a chemical vapor deposition reactor was clarified by evaluating the surface morphology of substrates immediately before the epitaxial growth and of epitaxial films. When the film was grown under non-optimized conditions, we found that numerous Si particles were formed on the surface of the substrate before the epitaxial growth and that the numerous growth pits on the subsequently grown epitaxial film were originated from Si particles. We observed that, by increasing the HCl flow rate through the outer nozzles in the gas inlet, which has a double-pipe structure consisting of inner and outer nozzles, the growth pit density was successfully decreased.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"402-404"},"PeriodicalIF":2.3,"publicationDate":"2024-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10511277","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140831548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-26DOI: 10.1109/TSM.2024.3394008
Ching-Ming Ku;Wen Yea Jang;Stone Cheng
In wafer etching, regular cleaning and maintenance of process chambers are necessary to reduce particle contamination of etched wafers during the wafer transfer process. Investigating alternative cleaning and maintenance is imperative. This study analyzed the number of particles falling onto a silicon wafer when the pressure difference within the process chamber was manipulated. We observed that rapid opening of the pressure control valve, which regulates the chamber’s pressure, caused contamination during wafer transport. This was particularly true when the change in the pressure ratio was considerable. The by-products near the side of the chamber’s pressure control valve were activated and transported. We verified this finding by adjusting the opening ratio of the pressure control valve (i.e., its degree of opening). We proposed that during the transition step of the etching process, this opening ratio can be controlled by regulating the process pressure through gas flow settings. This method could suppress the deposition of reflected particles originating from the turbomolecular pump’s pumping line on wafers, thereby minimizing the contamination of wafers.
{"title":"Minimization of Particle Deposition on Wafers Caused by the Pressure Change in the Vacuum Chamber Through a Pressure Control Regulation Process","authors":"Ching-Ming Ku;Wen Yea Jang;Stone Cheng","doi":"10.1109/TSM.2024.3394008","DOIUrl":"10.1109/TSM.2024.3394008","url":null,"abstract":"In wafer etching, regular cleaning and maintenance of process chambers are necessary to reduce particle contamination of etched wafers during the wafer transfer process. Investigating alternative cleaning and maintenance is imperative. This study analyzed the number of particles falling onto a silicon wafer when the pressure difference within the process chamber was manipulated. We observed that rapid opening of the pressure control valve, which regulates the chamber’s pressure, caused contamination during wafer transport. This was particularly true when the change in the pressure ratio was considerable. The by-products near the side of the chamber’s pressure control valve were activated and transported. We verified this finding by adjusting the opening ratio of the pressure control valve (i.e., its degree of opening). We proposed that during the transition step of the etching process, this opening ratio can be controlled by regulating the process pressure through gas flow settings. This method could suppress the deposition of reflected particles originating from the turbomolecular pump’s pumping line on wafers, thereby minimizing the contamination of wafers.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"340-344"},"PeriodicalIF":2.3,"publicationDate":"2024-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140798028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-24DOI: 10.1109/TSM.2024.3392898
Tianhong Pan;Lu Liu;Menghu Li
Virtual metrology (VM) is crucial for improving process capability and production yield during semiconductor manufacturing processes. However, the performance of VM deteriorates owing to the variable operating regime and the nonlinear characteristics of the process. Herein, Variational inference Gaussian mixture model (VIGMM) and extreme learning machine (ELM) are combined to solve these issues. First, variational inference is conducted on a Gaussian mixture model to determine the number of Gaussian components automatically and the corresponding operating regimes are identified. Subsequently, an extreme learning machine is developed for each operating regime to investigate the nonlinear relationship between process inputs and outputs. Finally, VM is implemented using the corresponding local ELM, which is determined based on the responsibility of the Gaussian components. The feasibility and effectiveness of the proposed methods are validated based on a numerical case and the plasma sputtering process for fabricating thin-film transistor liquid-crystal displays. The proposed VIGMM-ELM can serve as a VM algorithm for manufacturing processes with multiple stages.
在半导体制造过程中，虚拟计量（VM）对于提高工艺能力和产量至关重要。然而，由于操作制度多变和工艺的非线性特征，虚拟计量的性能会下降。在此，变异推理高斯混合模型（VIGMM）和极端学习机（ELM）相结合来解决这些问题。首先，对高斯混合物模型进行变分推理，自动确定高斯成分的数量，并确定相应的运行状态。随后，针对每种运行机制开发极端学习机，以研究流程输入和输出之间的非线性关系。最后，使用相应的局部 ELM 实现虚拟机管理，该局部 ELM 是根据高斯成分的责任确定的。基于一个数值案例和用于制造薄膜晶体管液晶显示器的等离子溅射工艺，验证了所提方法的可行性和有效性。提出的 VIGMM-ELM 可以作为多阶段制造过程的 VM 算法。
{"title":"Virtual Metrology for Multistage Processes Using Variational Inference Gaussian Mixture Model and Extreme Learning Machine","authors":"Tianhong Pan;Lu Liu;Menghu Li","doi":"10.1109/TSM.2024.3392898","DOIUrl":"10.1109/TSM.2024.3392898","url":null,"abstract":"Virtual metrology (VM) is crucial for improving process capability and production yield during semiconductor manufacturing processes. However, the performance of VM deteriorates owing to the variable operating regime and the nonlinear characteristics of the process. Herein, Variational inference Gaussian mixture model (VIGMM) and extreme learning machine (ELM) are combined to solve these issues. First, variational inference is conducted on a Gaussian mixture model to determine the number of Gaussian components automatically and the corresponding operating regimes are identified. Subsequently, an extreme learning machine is developed for each operating regime to investigate the nonlinear relationship between process inputs and outputs. Finally, VM is implemented using the corresponding local ELM, which is determined based on the responsibility of the Gaussian components. The feasibility and effectiveness of the proposed methods are validated based on a numerical case and the plasma sputtering process for fabricating thin-film transistor liquid-crystal displays. The proposed VIGMM-ELM can serve as a VM algorithm for manufacturing processes with multiple stages.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"271-279"},"PeriodicalIF":2.3,"publicationDate":"2024-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140798026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-23DOI: 10.1109/TSM.2024.3392712
Christoph Wehmann;Ambarish Kulkarni;Feyzan Durn;Murat Gulcur;Alan Astbury
Maintaining vacuum integrity for the semiconductor manufacturing processes is extremely important to improve semiconductor fab productivity. The expensive machinery and the enormous costs of production downtime require reliable sealing systems which are designed to operate the longest possible preventative maintenance (PM) cycles. Being able to predict the lifetime of the sealing systems can help determine the optimum maintenance periods and hence increase profitability in costly wafer processing. The present contribution describes a finite element method to predict the lifetime of vacuum sealing systems limited by aging effects of the elastomer. Several different applications are considered including isothermal and non-isothermal conditions. Furthermore, homogeneous and inhomogeneous temperature fields are analyzed. Finally, the model predictions are compared to experimental data.
{"title":"Predicting Temperature-Dependent Aging Effects and Permanent Set of Vacuum Sealing Systems in Semiconductor Manufacturing Processes","authors":"Christoph Wehmann;Ambarish Kulkarni;Feyzan Durn;Murat Gulcur;Alan Astbury","doi":"10.1109/TSM.2024.3392712","DOIUrl":"10.1109/TSM.2024.3392712","url":null,"abstract":"Maintaining vacuum integrity for the semiconductor manufacturing processes is extremely important to improve semiconductor fab productivity. The expensive machinery and the enormous costs of production downtime require reliable sealing systems which are designed to operate the longest possible preventative maintenance (PM) cycles. Being able to predict the lifetime of the sealing systems can help determine the optimum maintenance periods and hence increase profitability in costly wafer processing. The present contribution describes a finite element method to predict the lifetime of vacuum sealing systems limited by aging effects of the elastomer. Several different applications are considered including isothermal and non-isothermal conditions. Furthermore, homogeneous and inhomogeneous temperature fields are analyzed. Finally, the model predictions are compared to experimental data.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"260-270"},"PeriodicalIF":2.3,"publicationDate":"2024-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140797920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Transistor random threshold voltage variations due to process fluctuations seriously affects the stability of Static Random Access Memory (SRAM). In this paper, a SRAM bit transistors threshold voltage $({Vth})$ deviation monitoring scheme and system is proposed. This scheme ingeniously achieves on-chip measurement of all transistors threshold voltages without altering compact SRAM bit array layout. Control signal strategies and Transistor ${Vth}$ Determination Circuit (TVDC) for different types of Devices Under Test (DUTs) have been proposed. The system is implemented using a 65 nm CMOS process with a core area of 0.01875mm2. Through Monte Carlo analysis, the Weighted Average (WA) difference of the proposed scheme and the direct measurement method is not more than 10mV, and the Root Mean Square Error (RMSE) difference is not more than 3mV. This system can also effectively detect the cell position of the transistor threshold voltage mismatch simulated by modifying the substrate voltage. For SRAM arrays of different scales, the method proposed in this paper has area efficiency and flexible reconfigurability.
{"title":"A Threshold Voltage Deviation Monitoring Scheme of Bit Transistors in 6T SRAM for Manufacturing Defects Detection","authors":"Rui Liu;Hao Li;Zhao Yang;Guantao Wang;Zefu Chen;Peiyong Zhang","doi":"10.1109/TSM.2024.3387050","DOIUrl":"10.1109/TSM.2024.3387050","url":null,"abstract":"Transistor random threshold voltage variations due to process fluctuations seriously affects the stability of Static Random Access Memory (SRAM). In this paper, a SRAM bit transistors threshold voltage \u0000<inline-formula> <tex-math>$({Vth})$ </tex-math></inline-formula>\u0000 deviation monitoring scheme and system is proposed. This scheme ingeniously achieves on-chip measurement of all transistors threshold voltages without altering compact SRAM bit array layout. Control signal strategies and Transistor \u0000<inline-formula> <tex-math>${Vth}$ </tex-math></inline-formula>\u0000 Determination Circuit (TVDC) for different types of Devices Under Test (DUTs) have been proposed. The system is implemented using a 65 nm CMOS process with a core area of 0.01875mm2. Through Monte Carlo analysis, the Weighted Average (WA) difference of the proposed scheme and the direct measurement method is not more than 10mV, and the Root Mean Square Error (RMSE) difference is not more than 3mV. This system can also effectively detect the cell position of the transistor threshold voltage mismatch simulated by modifying the substrate voltage. For SRAM arrays of different scales, the method proposed in this paper has area efficiency and flexible reconfigurability.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"146-151"},"PeriodicalIF":2.7,"publicationDate":"2024-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140564825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-02DOI: 10.1109/TSM.2024.3378160
Won-Jun Choi;Myong Jae Yoo;Joonho Bae;Ji-Hun Seo;Churl Seung Lee
Through silicon vias (TSVs) are a critical technology for manufacturing three-dimensional stacked structure of semiconductor packages by forming holes that penetrate silicon wafers and vertically interconnect multiple wafers. Typically, TSVs are created by drilling via holes in wafers and filling their interiors using copper electroplating processes. Subsequently, the wafers are exposed to high-temperature environments during the back-end-of-line (BEOL) process. However, improper copper electroplating conditions can form defects, such as voids and seams, within TSVs, while the high temperature of the BEOL process induces copper protrusion phenomena. These defects and copper protrusion degrade the reliability of TSV. In this brief, copper protrusion behavior, which is a direct cause of reliability degradation in TSVs, was mitigated by experimentally exploring the seam defects that can occur during the TSV filling process. Subsequent annealing processes were applied to remove the seam defects based on the copper-grain growth. The copper protrusion height was analyzed based on the size of the seam defects and annealing temperature. From the proposed process in this brief, the copper protrusion heights of TSVs without and with seam defects were confirmed to be 1.531 and $1.289~mu text{m}$ , respectively, representing an improvement of approximately 15.81%.
{"title":"Improving the Reliability of Through Silicon Vias: Reducing Copper Protrusion by Artificial Defect Manipulation and Annealing","authors":"Won-Jun Choi;Myong Jae Yoo;Joonho Bae;Ji-Hun Seo;Churl Seung Lee","doi":"10.1109/TSM.2024.3378160","DOIUrl":"10.1109/TSM.2024.3378160","url":null,"abstract":"Through silicon vias (TSVs) are a critical technology for manufacturing three-dimensional stacked structure of semiconductor packages by forming holes that penetrate silicon wafers and vertically interconnect multiple wafers. Typically, TSVs are created by drilling via holes in wafers and filling their interiors using copper electroplating processes. Subsequently, the wafers are exposed to high-temperature environments during the back-end-of-line (BEOL) process. However, improper copper electroplating conditions can form defects, such as voids and seams, within TSVs, while the high temperature of the BEOL process induces copper protrusion phenomena. These defects and copper protrusion degrade the reliability of TSV. In this brief, copper protrusion behavior, which is a direct cause of reliability degradation in TSVs, was mitigated by experimentally exploring the seam defects that can occur during the TSV filling process. Subsequent annealing processes were applied to remove the seam defects based on the copper-grain growth. The copper protrusion height was analyzed based on the size of the seam defects and annealing temperature. From the proposed process in this brief, the copper protrusion heights of TSVs without and with seam defects were confirmed to be 1.531 and \u0000<inline-formula> <tex-math>$1.289~mu text{m}$ </tex-math></inline-formula>\u0000, respectively, representing an improvement of approximately 15.81%.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"166-173"},"PeriodicalIF":2.7,"publicationDate":"2024-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140565020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-29DOI: 10.1109/TSM.2024.3383287
Aaron Hardy;Matthias Muehle;Cristian Herrera-Rodriguez;Michael Becker;Edward Drown;Nina Baule;Mark Tompkins;Timothy Grotjohn;John D. Albrecht
For single crystal diamond (SCD) to gain practical use in technical applications including solid state electronics, thin (< $1 ~mu text{m}$ ), doped epitaxial SCD layers with very low (<1> $4.5 mm^{2}$ area. A subsequent 8-hour oxidative CMP process utilizing potassium permanganate and a novel self-leveling holder design decreased the average surface roughness from 3.83 nm and 1.57 nm to 0.20 nm and 0.16 nm for the two samples, respectively. MRRs were determined by evaluating five circular wear monitor structures in each sample by atomic force microscopy before and after the CMP process. The average MRRs were found to be 38.6 nm/hr and 37.3 nm/hr for the two samples. The purpose of this study is to demonstrate a CMP process suitable for polishing thin SCD epilayers to meet the needs of solid-state electronics applications.
{"title":"Chemical Mechanical Polishing of Single-Crystalline Diamond Epitaxial Layers for Electronics Applications","authors":"Aaron Hardy;Matthias Muehle;Cristian Herrera-Rodriguez;Michael Becker;Edward Drown;Nina Baule;Mark Tompkins;Timothy Grotjohn;John D. Albrecht","doi":"10.1109/TSM.2024.3383287","DOIUrl":"10.1109/TSM.2024.3383287","url":null,"abstract":"For single crystal diamond (SCD) to gain practical use in technical applications including solid state electronics, thin (<\u0000<inline-formula> <tex-math>$1 ~mu text{m}$ </tex-math></inline-formula>\u0000), doped epitaxial SCD layers with very low (<1> <tex-math>$4.5 mm^{2}$ </tex-math></inline-formula>\u0000 area. A subsequent 8-hour oxidative CMP process utilizing potassium permanganate and a novel self-leveling holder design decreased the average surface roughness from 3.83 nm and 1.57 nm to 0.20 nm and 0.16 nm for the two samples, respectively. MRRs were determined by evaluating five circular wear monitor structures in each sample by atomic force microscopy before and after the CMP process. The average MRRs were found to be 38.6 nm/hr and 37.3 nm/hr for the two samples. The purpose of this study is to demonstrate a CMP process suitable for polishing thin SCD epilayers to meet the needs of solid-state electronics applications.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"190-198"},"PeriodicalIF":2.7,"publicationDate":"2024-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140564910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
It is known that the determination of the good-dice-in-bad-neighborhoods (GDBNs) has been regarded as an effective technique to reduce the value of the defect parts per million (DPPM) by identifying and rejecting the suspicious dice even though they are good in testing. Instead of examining eight immediate neighbors in a small-sized $3times 3$ window or exploiting simple linear regression, a large-sized window can be used to recognize the broad-sighted neighborhoods and accurately infer the suspiciousness level for any given die. In this paper, the artificial neural networks (ANN)-based method can be proposed to solve the GDBN identification. Furthermore, two enhanced techniques can be further presented to improve the inference accuracy of the original ANN-based method by considering the variation of the time-dependent wafer patterns and the wafer-to-wafer relationship between two adjacent wafers. After applying the two enhanced techniques, the business profits can be improved in the new ANN-based method. Various experiments on two datasets clearly reveal the superiority of the proposed ANN-based method over the other existing methods. In addition to the reduction of the DPPM value, the new ANN-based method can achieve the 1.5X–2X better reduction in the cost of the return merchandise authorization (RMA). On the other hand, the experimental results show that the similar result can also be obtained in the other lower-yield products. By using the new ANN-based method, the relationships on bad dice cross wafers can be captured and the highly-accurate inference results can be simultaneously maintained.
众所周知，确定 "好骰子在坏邻居中"（GDBNs）一直被认为是通过识别和剔除可疑骰子（即使这些骰子在测试中是好的）来降低百万分之缺陷率（DPPM）值的有效技术。与在一个 3/3 乘 3$ 的小窗口中检查八个近邻或利用简单的线性回归不同，可以使用一个大窗口来识别广视角邻域，并准确推断任何给定骰子的可疑程度。本文提出了基于人工神经网络（ANN）的方法来解决 GDBN 识别问题。此外，本文还进一步提出了两种增强技术，通过考虑随时间变化的晶圆图案和相邻两个晶圆之间的晶圆与晶圆关系的变化，来提高基于人工神经网络的原始方法的推断精度。应用这两项增强技术后，基于 ANN 的新方法可以提高商业利润。在两个数据集上进行的各种实验清楚地揭示了所提出的基于 ANN 的方法优于其他现有方法。除了降低 DPPM 值，基于 ANN 的新方法还能使退货授权（RMA）成本降低 1.5 倍至 2 倍。另一方面，实验结果表明，其他低收益产品也能获得类似的结果。通过使用基于 ANN 的新方法，可以捕捉到坏骰子交叉晶圆的关系，并同时保持高精度的推理结果。
{"title":"Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks","authors":"Chia-Heng Yen;Ting-Rui Wang;Ching-Min Liu;Cheng-Hao Yang;Chun-Teng Chen;Ying-Yen Chen;Jih-Nung Lee;Shu-Yi Kao;Kai-Chiang Wu;Mango Chia-Tso Chao","doi":"10.1109/TSM.2024.3406395","DOIUrl":"10.1109/TSM.2024.3406395","url":null,"abstract":"It is known that the determination of the good-dice-in-bad-neighborhoods (GDBNs) has been regarded as an effective technique to reduce the value of the defect parts per million (DPPM) by identifying and rejecting the suspicious dice even though they are good in testing. Instead of examining eight immediate neighbors in a small-sized \u0000<inline-formula> <tex-math>$3times 3$ </tex-math></inline-formula>\u0000 window or exploiting simple linear regression, a large-sized window can be used to recognize the broad-sighted neighborhoods and accurately infer the suspiciousness level for any given die. In this paper, the artificial neural networks (ANN)-based method can be proposed to solve the GDBN identification. Furthermore, two enhanced techniques can be further presented to improve the inference accuracy of the original ANN-based method by considering the variation of the time-dependent wafer patterns and the wafer-to-wafer relationship between two adjacent wafers. After applying the two enhanced techniques, the business profits can be improved in the new ANN-based method. Various experiments on two datasets clearly reveal the superiority of the proposed ANN-based method over the other existing methods. In addition to the reduction of the DPPM value, the new ANN-based method can achieve the 1.5X–2X better reduction in the cost of the return merchandise authorization (RMA). On the other hand, the experimental results show that the similar result can also be obtained in the other lower-yield products. By using the new ANN-based method, the relationships on bad dice cross wafers can be captured and the highly-accurate inference results can be simultaneously maintained.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"280-292"},"PeriodicalIF":2.3,"publicationDate":"2024-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141188042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-27DOI: 10.1109/TSM.2024.3382511
S. Abdi;V. Nodjiadjim;R. Hersent;M. Riet;C. Mismer;T. de Vries;K. A. Williams;Y. Jiao
In this study, we focus on the development of key processes towards wafer-scale 3-dimentional/vertical (3D) integration of Indium-Phosphide (InP) photonic membranes on InP electronics via adhesive bonding. First, we identified the most critical steps and optimized them to achieve high thermal and mechanical compatibility of components for the co-integration process. Next, we developed a strategy for InP-to-InP wafer bonding with high topology tolerance, and introduced hard benzocyclobutene (BCB) anchors to preserve the alignment and BCB thickness uniformity after bonding. The resulting bond layer is homogeneous in terms of physical and mechanical properties. Finally, we developed a novel method to selectively remove the InP substrate from the photonics side via wet etching while protecting the electronics carrier wafer with hermetic multi-layer coatings. The investigation of these key steps is essential for scalable 3D integration of photonics and electronics at ultra short distances (< $15 ~mu text{m}$ ).
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