Purpose This paper aims to propose a method to reduce the resistance of silicon-based V-shaped electrothermal microactuator (VEM) by applying a surface sputtering process. Design/methodology/approach Four VEM’s samples have been fabricated using traditional silicon on insulator (SOI)-Micro-electro-mechanical System (MEMS) technology, three of them are coated with a thin layer of platinum on the top surface by sputtering technique with different sputtered times and the other is original. The displacements of the VEM are calculated and simulated to evaluate the advantages of sputtering method. Findings The measured results show that the average resistance of the sputtered structures is approximately 1.16, 1.55 and 2.4 times lower than the non-sputtering sample corresponding to the sputtering time of 1.5, 3 and 6 min. Simulation results confirmed that the maximum displacement of the sputtered VEM is almost 1.45 times larger than non-sputtering one in the range of voltage from 8 to 20 V. The experimental displacements are also measured to validate the better performance of the sputtered samples. Originality/value The experimental results demonstrated the better displacement of the VEM structure after using the platinum sputtering process. The improvement can be considered and applied for enhancing displacement as well as decreasing the driving voltage of the other electrothermal microactuators like U- or Z-shaped structures while combining with the low-cost SOI-MEMS micromachining technology.
{"title":"Improving displacement of silicon V-shaped electrothermal microactuator using platinum sputter deposition process","authors":"D. T. Nguyen, P. H. Pham, K. T. Hoang","doi":"10.1108/mi-05-2022-0076","DOIUrl":"https://doi.org/10.1108/mi-05-2022-0076","url":null,"abstract":"\u0000Purpose\u0000This paper aims to propose a method to reduce the resistance of silicon-based V-shaped electrothermal microactuator (VEM) by applying a surface sputtering process.\u0000\u0000\u0000Design/methodology/approach\u0000Four VEM’s samples have been fabricated using traditional silicon on insulator (SOI)-Micro-electro-mechanical System (MEMS) technology, three of them are coated with a thin layer of platinum on the top surface by sputtering technique with different sputtered times and the other is original. The displacements of the VEM are calculated and simulated to evaluate the advantages of sputtering method.\u0000\u0000\u0000Findings\u0000The measured results show that the average resistance of the sputtered structures is approximately 1.16, 1.55 and 2.4 times lower than the non-sputtering sample corresponding to the sputtering time of 1.5, 3 and 6 min. Simulation results confirmed that the maximum displacement of the sputtered VEM is almost 1.45 times larger than non-sputtering one in the range of voltage from 8 to 20 V. The experimental displacements are also measured to validate the better performance of the sputtered samples.\u0000\u0000\u0000Originality/value\u0000The experimental results demonstrated the better displacement of the VEM structure after using the platinum sputtering process. The improvement can be considered and applied for enhancing displacement as well as decreasing the driving voltage of the other electrothermal microactuators like U- or Z-shaped structures while combining with the low-cost SOI-MEMS micromachining technology.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49108723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose The purpose of this paper is to present a transition detector (TD)-based radiation hardened flip-flop (TDRH-FF) for single event upset (SEU). Design/methodology/approach With SEU recovery and single event transient (SET) detector mechanism, the TDRH-FF can tolerate SEU during hold mode and generate a warning signal for architecture-level recovery during transport mode when input signal contains SET. Evaluation results show that the TDRH-FF outperforms comparable comprehensive performance. Findings Simulation results show that 1) the mean pulse width of the correction glitches (at full width half maximum) of TDRH-FF is less than 10 ps; 2) the area overhead of TDRH-FF is similar to the EVFERST-FF, BISER-FF and DNURHL-FF; 3) TDRH-FF has the same average power consumption as SETTOF, and moderate PDP and Ps values among these compared FFs. Originality/value In this paper, a TD-based TDRH-FF is proposed to solve the problems in the previous design. And the main contributions of the proposed TDRH-FF are summarized: Minimum size transistors are used in the proposed TD which leads to a considerable decrease in area overheads and propagation delay (resulting in an ignorable correction glitch); and compared with other radiation hardened flip-flop, TDRH-FF outperforms comparable comprehensive performance.
{"title":"Radiation-hardened flip-flop for single event upset tolerance","authors":"Chunhua Qi, Guoliang Ma, Yanqing Zhang, Tianqi Wang, Erming Rui, Qiang Jiao, Chaoming Liu, Mingxue Huo, G. Zhai","doi":"10.1108/mi-06-2022-0110","DOIUrl":"https://doi.org/10.1108/mi-06-2022-0110","url":null,"abstract":"\u0000Purpose\u0000The purpose of this paper is to present a transition detector (TD)-based radiation hardened flip-flop (TDRH-FF) for single event upset (SEU).\u0000\u0000\u0000Design/methodology/approach\u0000With SEU recovery and single event transient (SET) detector mechanism, the TDRH-FF can tolerate SEU during hold mode and generate a warning signal for architecture-level recovery during transport mode when input signal contains SET. Evaluation results show that the TDRH-FF outperforms comparable comprehensive performance.\u0000\u0000\u0000Findings\u0000Simulation results show that 1) the mean pulse width of the correction glitches (at full width half maximum) of TDRH-FF is less than 10 ps; 2) the area overhead of TDRH-FF is similar to the EVFERST-FF, BISER-FF and DNURHL-FF; 3) TDRH-FF has the same average power consumption as SETTOF, and moderate PDP and Ps values among these compared FFs.\u0000\u0000\u0000Originality/value\u0000In this paper, a TD-based TDRH-FF is proposed to solve the problems in the previous design. And the main contributions of the proposed TDRH-FF are summarized: Minimum size transistors are used in the proposed TD which leads to a considerable decrease in area overheads and propagation delay (resulting in an ignorable correction glitch); and compared with other radiation hardened flip-flop, TDRH-FF outperforms comparable comprehensive performance.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47487752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose This paper aims to propose a single element, dual feed, polarisation diversity antenna. The proposed antenna operates from 2.9 to 10.6 GHz for covering the entire ultra-wideband (UWB) frequency range. The antenna is designed for usage in massive multiple input multiple output (MIMO) and closed packaging applications. Design/methodology/approach The size of the antenna is 24 × 24 × 1.6 mm3. The radiating element of the antenna is derived from the Sierpinski–Knopp (SK) fractal geometry for miniaturization of the antenna size. The antenna has a single reflecting stub placed between the two orthogonal feeds, to improve isolation. Findings The proposed antenna system exhibits S11 < −10 dB, S21 < −15 dB and stable radiation characteristics in the entire operating region. It also offers an envelope correlation coefficient < 0.01, a diversity gain > 9.9 dB and a capacity loss < 0.4 bps/Hz. The simulated and measured outputs were compared and results were found to be in similarity. Originality/value The proposed UWB-MIMO antenna has significant size reduction through usage of SK fractal geometry for radiating element. The antenna uses a single radiating element with dual feed. The stub is between the antenna elements which provide a compact and miniaturized MIMO solution for high density packaging applications. The UWB-MIMO antenna provides an isolation better than −20 dB in the entire UWB operating band.
{"title":"A monopole polarisation diversity antenna for high density packaging MIMO applications","authors":"Dhanalakshmi K.M., K. G., R. S.","doi":"10.1108/mi-07-2022-0127","DOIUrl":"https://doi.org/10.1108/mi-07-2022-0127","url":null,"abstract":"\u0000Purpose\u0000This paper aims to propose a single element, dual feed, polarisation diversity antenna. The proposed antenna operates from 2.9 to 10.6 GHz for covering the entire ultra-wideband (UWB) frequency range. The antenna is designed for usage in massive multiple input multiple output (MIMO) and closed packaging applications.\u0000\u0000\u0000Design/methodology/approach\u0000The size of the antenna is 24 × 24 × 1.6 mm3. The radiating element of the antenna is derived from the Sierpinski–Knopp (SK) fractal geometry for miniaturization of the antenna size. The antenna has a single reflecting stub placed between the two orthogonal feeds, to improve isolation.\u0000\u0000\u0000Findings\u0000The proposed antenna system exhibits S11 < −10 dB, S21 < −15 dB and stable radiation characteristics in the entire operating region. It also offers an envelope correlation coefficient < 0.01, a diversity gain > 9.9 dB and a capacity loss < 0.4 bps/Hz. The simulated and measured outputs were compared and results were found to be in similarity.\u0000\u0000\u0000Originality/value\u0000The proposed UWB-MIMO antenna has significant size reduction through usage of SK fractal geometry for radiating element. The antenna uses a single radiating element with dual feed. The stub is between the antenna elements which provide a compact and miniaturized MIMO solution for high density packaging applications. The UWB-MIMO antenna provides an isolation better than −20 dB in the entire UWB operating band.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43552578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose A large-scale detection system with more data in short time bins, small dead space and small signal identification is the ideology the scientists pursuing. These proposed demands are able to be solved by 2.5 D integration. The substance of a 2.5 D integration is called silicon interposer, which consists of the through silicon via (TSV) and redistribution layer. However, the state-of-the-art silicon interposer is not able to sustain its own mechanical strength with the detector/readout array often sitting as standalone in large science facilities and fails to reduce the expansions on the installation of the components due to its insufficient thickness and size. This study aims to propose a moderation of current interposer with large-sized, standalone properties. Design/methodology/approach This paper proposes an interposer based on double-sided silicon vias (DSSVs) interconnection. Unlike conventional interposer that is interconnected by TSVs, DSSVs interposer is interconnected by top vias (T-vias) and bottom vias (B-vias). Findings The fabrication process of DSSVs interposer is introduced, and the superiority of the double-sided interconnection process with two etch-stop layers is described in detail. The impact of different T-vias depth on DSSVs interconnections in the same wafer is discussed and two times PI opening processes are proposed to eliminate air bubbles in the B-via. The relationship between the interposer thickness and warpage is studied by finite element analysis simulation and experiment. The prototype of the DSSVs interposer with a size of 100 × 100 mm and a thickness of 318.2 µm is fabricated, and electrical tests including short tests and continuity tests are carried out. Originality/value This paper proposes a large-sized and stand-alone interposer based on DSSVs interconnection.
{"title":"Double-sided silicon vias (DSSVs) interconnection for large-sized interposer fabrication","authors":"Haibo Yang, Fengwei Dai, Liqiang Cao, Guofu Cao, Zhidan Fang, Qidong Wang","doi":"10.1108/mi-07-2022-0139","DOIUrl":"https://doi.org/10.1108/mi-07-2022-0139","url":null,"abstract":"\u0000Purpose\u0000A large-scale detection system with more data in short time bins, small dead space and small signal identification is the ideology the scientists pursuing. These proposed demands are able to be solved by 2.5 D integration. The substance of a 2.5 D integration is called silicon interposer, which consists of the through silicon via (TSV) and redistribution layer. However, the state-of-the-art silicon interposer is not able to sustain its own mechanical strength with the detector/readout array often sitting as standalone in large science facilities and fails to reduce the expansions on the installation of the components due to its insufficient thickness and size. This study aims to propose a moderation of current interposer with large-sized, standalone properties.\u0000\u0000\u0000Design/methodology/approach\u0000This paper proposes an interposer based on double-sided silicon vias (DSSVs) interconnection. Unlike conventional interposer that is interconnected by TSVs, DSSVs interposer is interconnected by top vias (T-vias) and bottom vias (B-vias).\u0000\u0000\u0000Findings\u0000The fabrication process of DSSVs interposer is introduced, and the superiority of the double-sided interconnection process with two etch-stop layers is described in detail. The impact of different T-vias depth on DSSVs interconnections in the same wafer is discussed and two times PI opening processes are proposed to eliminate air bubbles in the B-via. The relationship between the interposer thickness and warpage is studied by finite element analysis simulation and experiment. The prototype of the DSSVs interposer with a size of 100 × 100 mm and a thickness of 318.2 µm is fabricated, and electrical tests including short tests and continuity tests are carried out.\u0000\u0000\u0000Originality/value\u0000This paper proposes a large-sized and stand-alone interposer based on DSSVs interconnection.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47032481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Liyun Li, Yu Zhang, Shiyu Xia, Zhefei Sun, Junjie Yuan, D. Su, H. Cao, X. Chai, Qingtian Wang, Jintang Li, Zhihao Zhang
Purpose This study aims to develop a facile ligand-exchange strategy to promote nano-sintering of oleylamine (OAM)-capped silver nanoparticles (AgNPs). By using ligand exchange process with NH4OH to remove OAM from the surface of AgNP, this study reports effectively reducing the sintering temperature of AgNPs to achieve low-temperature nano-sintering. Compared with untreated AgNPs of OAM-capped, NH4OH-treated AgNPs possess superior sintering performance that could be applied to a fractional generator device as conductor and in favour of the fabrication of flexible circuit modules. Design/methodology/approach First, oleylamine is used as reductant to synthesize monodisperse AgNPs by a simple one-step method. Then ligand exchange is used with NH4OH at different treating times to remove OAM, and micro-Fourier transform infrared spectroscopy and contact angle test are applied to clear the mechanism and structure characteristics of these processes. Finally, NH4OH-treated AgNPs sediment sintering is used at different temperatures to test electrical resistivity and use ex situ scanning electron microscopy combined with in situ X-ray diffraction to study changes in microstructure in the whole nano-sintering process. Findings The AgNPs are always capped by organic ligands to prevent nanoparticles agglomeration. And oleylamine used as reductant could synthesize desirable size distributions of 8–32 nm with monodisperse globular shapes, but the low-temperature nano-sintering seemed not to be achieved by the oleylamine-capped AgNPs because OAM is an organic with long C-chain. The ligand exchange approach was enabled to replace the original organic ligands capped on AgNPs with organic ligands of low thermal stability which could promote nano-sintering. After ligand exchange treated AgNPs could be sintered on photo paper, polydimethylsiloxane (PDMS) and polyethylene terephthalate flexible substrates at low temperature. Originality/value In this research, the method ligand exchange is used to change the ligand of AgNPs. During ligand exchange, NH4OH was used to treat AgNPs. Through the treatment of NH4OH, the change of hydrophilic and hydrophobic properties of AgNPs was successfully realized. The sintering temperature of AgNPs can also be reduced and the properties can be improved. Finally, the applicability of the AgNPs sediment with this nano-sintering process at low temperature for obtaining conductive patterns was evaluated using PDMS as substrates.
{"title":"Facile ligand-exchange strategy to promote low-temperature nano-sintering of oleylamine-capped Ag nanoparticles","authors":"Liyun Li, Yu Zhang, Shiyu Xia, Zhefei Sun, Junjie Yuan, D. Su, H. Cao, X. Chai, Qingtian Wang, Jintang Li, Zhihao Zhang","doi":"10.1108/mi-11-2022-0186","DOIUrl":"https://doi.org/10.1108/mi-11-2022-0186","url":null,"abstract":"\u0000Purpose\u0000This study aims to develop a facile ligand-exchange strategy to promote nano-sintering of oleylamine (OAM)-capped silver nanoparticles (AgNPs). By using ligand exchange process with NH4OH to remove OAM from the surface of AgNP, this study reports effectively reducing the sintering temperature of AgNPs to achieve low-temperature nano-sintering. Compared with untreated AgNPs of OAM-capped, NH4OH-treated AgNPs possess superior sintering performance that could be applied to a fractional generator device as conductor and in favour of the fabrication of flexible circuit modules.\u0000\u0000\u0000Design/methodology/approach\u0000First, oleylamine is used as reductant to synthesize monodisperse AgNPs by a simple one-step method. Then ligand exchange is used with NH4OH at different treating times to remove OAM, and micro-Fourier transform infrared spectroscopy and contact angle test are applied to clear the mechanism and structure characteristics of these processes. Finally, NH4OH-treated AgNPs sediment sintering is used at different temperatures to test electrical resistivity and use ex situ scanning electron microscopy combined with in situ X-ray diffraction to study changes in microstructure in the whole nano-sintering process.\u0000\u0000\u0000Findings\u0000The AgNPs are always capped by organic ligands to prevent nanoparticles agglomeration. And oleylamine used as reductant could synthesize desirable size distributions of 8–32 nm with monodisperse globular shapes, but the low-temperature nano-sintering seemed not to be achieved by the oleylamine-capped AgNPs because OAM is an organic with long C-chain. The ligand exchange approach was enabled to replace the original organic ligands capped on AgNPs with organic ligands of low thermal stability which could promote nano-sintering. After ligand exchange treated AgNPs could be sintered on photo paper, polydimethylsiloxane (PDMS) and polyethylene terephthalate flexible substrates at low temperature.\u0000\u0000\u0000Originality/value\u0000In this research, the method ligand exchange is used to change the ligand of AgNPs. During ligand exchange, NH4OH was used to treat AgNPs. Through the treatment of NH4OH, the change of hydrophilic and hydrophobic properties of AgNPs was successfully realized. The sintering temperature of AgNPs can also be reduced and the properties can be improved. Finally, the applicability of the AgNPs sediment with this nano-sintering process at low temperature for obtaining conductive patterns was evaluated using PDMS as substrates.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48022541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Liu, Songjie Yao, Song Xue, Benben Wang, Hui Jin, C. Pan, Yinwei Zhang, Yijiang Zhou, Rui Zeng, Lihao Ping, Z. Min, Daxing Zhang, Congsi Wang
Purpose Surface mount technology (SMT) is widely used and plays an important role in electronic equipment. The purpose of this paper is to reveal the effects of interface cracks on the fatigue life of SMT solder joint under service load and to provide some valuable reference information for improving service reliability of SMT packages. Design/methodology/approach A 3D geometric model of SMT package is established. The mechanical properties of SMT solder joint under thermal cycling load and random vibration load were solved by 3D finite element analysis. The fatigue life of SMT solder joint under different loads can be calculated by using the modified Coffin–Manson model and high-cycle fatigue model. Findings The results revealed that cracks at different locations and propagation directions have different effect on the fatigue life of the SMT solder joint. From the location of the cracks, Crack 1 has the most significant impact on the thermal fatigue life of the solder joint. Under the same thermal cycling conditions, its life has decreased by 46.98%, followed by Crack 2, Crack 4 and Crack 3. On the other hand, under the same random vibration load, Crack 4 has the most significant impact on the solder joint fatigue life, reducing its life by 81.39%, followed by Crack 1, Crack 3 and Crack 2. From the crack propagation direction, with the increase of crack depth, the thermal fatigue life of the SMT solder joint decreases sharply at first and then continues to decline almost linearly. The random vibration fatigue life of the solder joint decreases continuously with the increase of crack depth. From the crack depth of 0.01 mm to 0.05 mm, the random vibration fatigue life decreases by 86.75%. When the crack width increases, the thermal and random vibration fatigue life of the solder joint decreases almost linearly. Originality/value This paper investigates the effects of interface cracks on the fatigue life and provides useful information on the reliability of SMT packages.
{"title":"Effects of interface cracks on reliability of surface mount technology interconnection in service environment","authors":"S. Liu, Songjie Yao, Song Xue, Benben Wang, Hui Jin, C. Pan, Yinwei Zhang, Yijiang Zhou, Rui Zeng, Lihao Ping, Z. Min, Daxing Zhang, Congsi Wang","doi":"10.1108/mi-10-2022-0183","DOIUrl":"https://doi.org/10.1108/mi-10-2022-0183","url":null,"abstract":"\u0000Purpose\u0000Surface mount technology (SMT) is widely used and plays an important role in electronic equipment. The purpose of this paper is to reveal the effects of interface cracks on the fatigue life of SMT solder joint under service load and to provide some valuable reference information for improving service reliability of SMT packages.\u0000\u0000\u0000Design/methodology/approach\u0000A 3D geometric model of SMT package is established. The mechanical properties of SMT solder joint under thermal cycling load and random vibration load were solved by 3D finite element analysis. The fatigue life of SMT solder joint under different loads can be calculated by using the modified Coffin–Manson model and high-cycle fatigue model.\u0000\u0000\u0000Findings\u0000The results revealed that cracks at different locations and propagation directions have different effect on the fatigue life of the SMT solder joint. From the location of the cracks, Crack 1 has the most significant impact on the thermal fatigue life of the solder joint. Under the same thermal cycling conditions, its life has decreased by 46.98%, followed by Crack 2, Crack 4 and Crack 3. On the other hand, under the same random vibration load, Crack 4 has the most significant impact on the solder joint fatigue life, reducing its life by 81.39%, followed by Crack 1, Crack 3 and Crack 2. From the crack propagation direction, with the increase of crack depth, the thermal fatigue life of the SMT solder joint decreases sharply at first and then continues to decline almost linearly. The random vibration fatigue life of the solder joint decreases continuously with the increase of crack depth. From the crack depth of 0.01 mm to 0.05 mm, the random vibration fatigue life decreases by 86.75%. When the crack width increases, the thermal and random vibration fatigue life of the solder joint decreases almost linearly.\u0000\u0000\u0000Originality/value\u0000This paper investigates the effects of interface cracks on the fatigue life and provides useful information on the reliability of SMT packages.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41970921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Supriya Yadav, Kulwant Singh, Anmol Gupta, Mahesh Kumar, N. N. Sharma, J. Akhtar
Purpose The purpose of this paper is to predict a suitable paper substrate which has high capillary pressure with the tendency of subsequent fluid wrenching in onward direction for the fabrication of microfluidics device application. Design/methodology/approach The experiment has been done on the WhatmanTM grade 1, WhatmanTM chromatography and nitrocellulose paper samples which are made by GE Healthcare Life Sciences. The structural characterization of paper samples for surface properties has been done by scanning electron microscope and ImageJ software. Identification of functional groups on the surface of samples has been done by Fourier transform infrared analysis. A finite elemental analysis has also been performed by using the “Multiphase Flow in Porous Media” module of the COMSOL Multiphysics tool which combines Darcy’s law and Phase Transport in Porous Media interface. Findings Experimentally, it has been concluded that the paper substrate for flexible microfluidic device application must have large number of internal (intra- and interfiber) pores with fewer void spaces (external pores) that have high capillary pressure to propel the fluid in onward direction with narrow paper fiber channel. Originality/value Surface structure has a dynamic impact in paper substrate utilization in multiple applications such as paper manufacturing, printing process and microfluidics applications.
目的本文的目的是预测一种合适的具有高毛细管压力的纸基板，该基板具有随后流体向前扭曲的趋势，用于微流体器件的制造应用。设计/方法/方法本实验是在GE Healthcare Life Sciences生产的WhatmanTM 1级、WhatmanTM色谱和硝化纤维素纸样品上进行的。通过扫描电子显微镜和ImageJ软件对纸张样品的表面性质进行了结构表征。通过傅立叶变换红外分析对样品表面的官能团进行了识别。还使用COMSOL Multiphysics工具的“多孔介质中的多相流动”模块进行了有限元分析，该模块结合了达西定律和多孔介质界面中的相输运。实验发现，用于柔性微流体装置应用的纸基板必须具有大量的内部（纤维内和纤维间）孔隙，这些孔隙具有较少的空隙空间（外部孔隙），这些空隙空间具有较高的毛细管压力，以通过狭窄的纸纤维通道将流体向前推进。独创性/价值表面结构在纸张制造、印刷工艺和微流体应用等多种应用中对纸张基材的利用具有动态影响。
{"title":"Structural analysis of paper substrate for flexible microfluidics device application","authors":"Supriya Yadav, Kulwant Singh, Anmol Gupta, Mahesh Kumar, N. N. Sharma, J. Akhtar","doi":"10.1108/mi-09-2022-0172","DOIUrl":"https://doi.org/10.1108/mi-09-2022-0172","url":null,"abstract":"\u0000Purpose\u0000The purpose of this paper is to predict a suitable paper substrate which has high capillary pressure with the tendency of subsequent fluid wrenching in onward direction for the fabrication of microfluidics device application.\u0000\u0000\u0000Design/methodology/approach\u0000The experiment has been done on the WhatmanTM grade 1, WhatmanTM chromatography and nitrocellulose paper samples which are made by GE Healthcare Life Sciences. The structural characterization of paper samples for surface properties has been done by scanning electron microscope and ImageJ software. Identification of functional groups on the surface of samples has been done by Fourier transform infrared analysis. A finite elemental analysis has also been performed by using the “Multiphase Flow in Porous Media” module of the COMSOL Multiphysics tool which combines Darcy’s law and Phase Transport in Porous Media interface.\u0000\u0000\u0000Findings\u0000Experimentally, it has been concluded that the paper substrate for flexible microfluidic device application must have large number of internal (intra- and interfiber) pores with fewer void spaces (external pores) that have high capillary pressure to propel the fluid in onward direction with narrow paper fiber channel.\u0000\u0000\u0000Originality/value\u0000Surface structure has a dynamic impact in paper substrate utilization in multiple applications such as paper manufacturing, printing process and microfluidics applications.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48023664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose Bumpless Cu/SiO2 hybrid bonding, which this paper aims to, is a key technology of three-dimensional (3D) high-density integration to promote the integrated circuits industry’s continuous development, which achieves the stacks of chips vertically connected via through-silicon via. Surface-activated bonding (SAB) and thermal-compression bonding (TCB) are used, but both have some shortcomings. The SAB method is overdemanding in the bonding environment, and the TCB method requires a high temperature to remove copper oxide from surfaces, which increases the thermal budget and grossly damages the fine-pitch device. Design/methodology/approach In this review, methods to prevent and remove copper oxidation in the whole bonding process for a lower bonding temperature, such as wet treatment, plasma surface activation, nanotwinned copper and the metal passivation layer, are investigated. Findings The cooperative bonding method combining wet treatment and plasma activation shows outstanding technological superiority without the high cost and additional necessity of copper passivation in manufacture. Cu/SiO2 hybrid bonding has great potential to effectively enhance the integration density in future 3D packaging for artificial intelligence, the internet of things and other high-density chips. Originality/value To achieve heterogeneous bonding at a lower temperature, the SAB method, chemical treatment and the plasma-assisted bonding method (based on TCB) are used, and surface-enhanced measurements such as nanotwinned copper and the metal passivation layer are also applied to prevent surface copper oxide.
{"title":"Recent progress on bumpless Cu/SiO2 hybrid bonding for 3D heterogeneous integration","authors":"Ge Li, Qiushi Kang, F. Niu, Chenxi Wang","doi":"10.1108/mi-07-2022-0121","DOIUrl":"https://doi.org/10.1108/mi-07-2022-0121","url":null,"abstract":"\u0000Purpose\u0000Bumpless Cu/SiO2 hybrid bonding, which this paper aims to, is a key technology of three-dimensional (3D) high-density integration to promote the integrated circuits industry’s continuous development, which achieves the stacks of chips vertically connected via through-silicon via. Surface-activated bonding (SAB) and thermal-compression bonding (TCB) are used, but both have some shortcomings. The SAB method is overdemanding in the bonding environment, and the TCB method requires a high temperature to remove copper oxide from surfaces, which increases the thermal budget and grossly damages the fine-pitch device.\u0000\u0000\u0000Design/methodology/approach\u0000In this review, methods to prevent and remove copper oxidation in the whole bonding process for a lower bonding temperature, such as wet treatment, plasma surface activation, nanotwinned copper and the metal passivation layer, are investigated.\u0000\u0000\u0000Findings\u0000The cooperative bonding method combining wet treatment and plasma activation shows outstanding technological superiority without the high cost and additional necessity of copper passivation in manufacture. Cu/SiO2 hybrid bonding has great potential to effectively enhance the integration density in future 3D packaging for artificial intelligence, the internet of things and other high-density chips.\u0000\u0000\u0000Originality/value\u0000To achieve heterogeneous bonding at a lower temperature, the SAB method, chemical treatment and the plasma-assisted bonding method (based on TCB) are used, and surface-enhanced measurements such as nanotwinned copper and the metal passivation layer are also applied to prevent surface copper oxide.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2022-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42068169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xuebing Su, Yang Wang, Xiangliang Jin, Hongjiao Yang, Yuye Zhang, Shuaikang Yang, Bo Yu
Purpose As it is known, the electrostatic discharge (ESD) protection design of integrated circuit is very important, among which the silicon controlled rectifier (SCR) is one of the most commonly used ESD protection devices. However, the traditional SCR has the disadvantages of too high trigger voltage, too low holding voltage after the snapback and longer turn-on time. The purpose of this paper is to design a high-performance SCR in accordance with the design window under 0.25 µm process, and provide a new scheme for SCR design to reduce the trigger voltage, improve the holding voltage and reduce the turn-on time. Design/methodology/approach Based on the traditional SCR, an RC-INV trigger circuit is introduced. Through theoretical analysis, TCAD simulation and tape-out verification, it is shown that RC-INV triggering SCR can reduce the trigger voltage, increase the holding voltage and reduce the turn-on time of the device on the premise of maintaining good robustness. Findings The RC-INV triggering SCR has great performance, and the test shows that the transmission line pulse curve with almost no snapback can be obtained. Compared with the traditional SCR, the trigger voltage decreased from 32.39 to 16.24 V, the holding voltage increased from 3.12 to 14.18 V and the turn-on time decreased from 29.6 to 16.6 ns, decreasing by 43.9% the level of human body model reached 18 kV+. Originality/value Under 0.25 µm BCD process, this study propose a high-performance RC-INV triggering SCR ESD protection device. The work presented in this paper has a certain guiding significance for the design of SCR ESD protection devices.
{"title":"A high performance RC-INV triggering SCR under 0.25 µm process","authors":"Xuebing Su, Yang Wang, Xiangliang Jin, Hongjiao Yang, Yuye Zhang, Shuaikang Yang, Bo Yu","doi":"10.1108/mi-04-2022-0069","DOIUrl":"https://doi.org/10.1108/mi-04-2022-0069","url":null,"abstract":"\u0000Purpose\u0000As it is known, the electrostatic discharge (ESD) protection design of integrated circuit is very important, among which the silicon controlled rectifier (SCR) is one of the most commonly used ESD protection devices. However, the traditional SCR has the disadvantages of too high trigger voltage, too low holding voltage after the snapback and longer turn-on time. The purpose of this paper is to design a high-performance SCR in accordance with the design window under 0.25 µm process, and provide a new scheme for SCR design to reduce the trigger voltage, improve the holding voltage and reduce the turn-on time.\u0000\u0000\u0000Design/methodology/approach\u0000Based on the traditional SCR, an RC-INV trigger circuit is introduced. Through theoretical analysis, TCAD simulation and tape-out verification, it is shown that RC-INV triggering SCR can reduce the trigger voltage, increase the holding voltage and reduce the turn-on time of the device on the premise of maintaining good robustness.\u0000\u0000\u0000Findings\u0000The RC-INV triggering SCR has great performance, and the test shows that the transmission line pulse curve with almost no snapback can be obtained. Compared with the traditional SCR, the trigger voltage decreased from 32.39 to 16.24 V, the holding voltage increased from 3.12 to 14.18 V and the turn-on time decreased from 29.6 to 16.6 ns, decreasing by 43.9% the level of human body model reached 18 kV+.\u0000\u0000\u0000Originality/value\u0000Under 0.25 µm BCD process, this study propose a high-performance RC-INV triggering SCR ESD protection device. The work presented in this paper has a certain guiding significance for the design of SCR ESD protection devices.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2022-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47457435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose The design, fabrication and experimental validation of defected microstrip structure (DMS) are proposed to address the problem of near-end crosstalk (NEXT) and far-end crosstalk (FEXT) between the microstrip transmission lines in a printed circuit board. Design/methodology/approach The proposed DMS evolved with the combination of spur line (L-shaped DMS) and U-shaped DMS topologies. This technique reduces the strength of electromagnetic coupling and suppresses crosstalk by optimizing the capacitive and inductive coupling ratio between the linked microstrip lines. The practical inductance value is much more significant in DMS than in defected ground structures (DGS), but the capacitance value remains the same. Findings A DMS unit is etched on the aggressor microstrip line instead of the DGS circuit. Because there is no leakage via the ground plane and the circuit size is far smaller than with DGS, the enclosure issue is disregarded. DMS structures have a larger effective inductance and are resistant to electromagnetic interference. A tightly coupled transmission line structure with minimal separation between the coupled microstrip line is designed using DMS. Further research must be conducted to improve the NEXT, FEXT and spacing between the transmission lines. Originality/value Simulation and actual measurement results show that the proposed DMS structure can effectively suppress crosstalk by analysing the S-parameters, namely, S_12, S_13 and S_14, with measured values of 1.48 dB, 20.65 dB and 21.099 dB, respectively. The data rate is measured to be 1.34 Gbps as per the eye diagram characterization. The results show that the NEXT and FEXT are reduced by approximately 20 dB in the frequency range of 1–11 GHz for mixed signals. The substantial measured results in the vector network analyser coincide with the computer simulation technology microwave studio suite simulation results.
{"title":"Defected microstrip structure-based near-end and far-end crosstalk mitigation in high-speed PCBs for mixed signals","authors":"Y. V., G. Alsath, M. Kanagasabai","doi":"10.1108/mi-05-2022-0089","DOIUrl":"https://doi.org/10.1108/mi-05-2022-0089","url":null,"abstract":"\u0000Purpose\u0000The design, fabrication and experimental validation of defected microstrip structure (DMS) are proposed to address the problem of near-end crosstalk (NEXT) and far-end crosstalk (FEXT) between the microstrip transmission lines in a printed circuit board.\u0000\u0000\u0000Design/methodology/approach\u0000The proposed DMS evolved with the combination of spur line (L-shaped DMS) and U-shaped DMS topologies. This technique reduces the strength of electromagnetic coupling and suppresses crosstalk by optimizing the capacitive and inductive coupling ratio between the linked microstrip lines. The practical inductance value is much more significant in DMS than in defected ground structures (DGS), but the capacitance value remains the same.\u0000\u0000\u0000Findings\u0000A DMS unit is etched on the aggressor microstrip line instead of the DGS circuit. Because there is no leakage via the ground plane and the circuit size is far smaller than with DGS, the enclosure issue is disregarded. DMS structures have a larger effective inductance and are resistant to electromagnetic interference. A tightly coupled transmission line structure with minimal separation between the coupled microstrip line is designed using DMS. Further research must be conducted to improve the NEXT, FEXT and spacing between the transmission lines.\u0000\u0000\u0000Originality/value\u0000Simulation and actual measurement results show that the proposed DMS structure can effectively suppress crosstalk by analysing the S-parameters, namely, S_12, S_13 and S_14, with measured values of 1.48 dB, 20.65 dB and 21.099 dB, respectively. The data rate is measured to be 1.34 Gbps as per the eye diagram characterization. The results show that the NEXT and FEXT are reduced by approximately 20 dB in the frequency range of 1–11 GHz for mixed signals. The substantial measured results in the vector network analyser coincide with the computer simulation technology microwave studio suite simulation results.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45412372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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