Yuchen Xiao, H. Tang, Hehe Zhang, Xiaoling Yang, Ling Sun, Yong Xie, Baoan Wu, B. Luan, W. Xie, X. Cai
Purpose The purpose of this paper is to develop high-performance Au-coated Ag alloy wires (ACAA wires) and demonstrate the effect of Au coating layers on the bonding performance and oxidation resistance for stable and reliable electronic packaging applications. Design/methodology/approach ACAA wire with a diameter of approximately 25 µm and Au layer thickness of approximately 100 nm were prepared by the continuous casting, plating and wire drawing method. The bonding performance of the ACAA wires were studied through bonding on 3,535 chips. The oxidation resistance of ACAA wires and Ag alloy wires (AA wires) were comparatively studied by means of chemical oxidation tests, accelerated life tests and electrochemical tests systematically. Findings ACAA wires could form axi-symmetrical spherical free air balls with controllable diameter of 1.5∼2.5 times of the wire diameter after electric flame-off process. The ball shear strength of ACAA wire was higher than that of AA wires. Most importantly, because of the surface Au coating layer, the oxidation resistance of ACAA wires was much enhanced. Research limitations/implications ACAA wires with different lengths of heat affected zone were not developed in this study, which limited their application with different loop height requirements. Practical implications With higher bonding strength and oxidation resistance, ACAA wires would be a better choice than previous reported AA wire in chip packaging which require high stability and reliability. Originality/value This paper provides a kind of novel ACAA wire, which possess the merits of high bonding strength and reliability, and show great potential in electronic packaging applications.
{"title":"Au-coated Ag alloy bonding wires with enhanced oxidation resistance for electronic packaging applications","authors":"Yuchen Xiao, H. Tang, Hehe Zhang, Xiaoling Yang, Ling Sun, Yong Xie, Baoan Wu, B. Luan, W. Xie, X. Cai","doi":"10.1108/mi-08-2022-0158","DOIUrl":"https://doi.org/10.1108/mi-08-2022-0158","url":null,"abstract":"\u0000Purpose\u0000The purpose of this paper is to develop high-performance Au-coated Ag alloy wires (ACAA wires) and demonstrate the effect of Au coating layers on the bonding performance and oxidation resistance for stable and reliable electronic packaging applications.\u0000\u0000\u0000Design/methodology/approach\u0000ACAA wire with a diameter of approximately 25 µm and Au layer thickness of approximately 100 nm were prepared by the continuous casting, plating and wire drawing method. The bonding performance of the ACAA wires were studied through bonding on 3,535 chips. The oxidation resistance of ACAA wires and Ag alloy wires (AA wires) were comparatively studied by means of chemical oxidation tests, accelerated life tests and electrochemical tests systematically.\u0000\u0000\u0000Findings\u0000ACAA wires could form axi-symmetrical spherical free air balls with controllable diameter of 1.5∼2.5 times of the wire diameter after electric flame-off process. The ball shear strength of ACAA wire was higher than that of AA wires. Most importantly, because of the surface Au coating layer, the oxidation resistance of ACAA wires was much enhanced.\u0000\u0000\u0000Research limitations/implications\u0000ACAA wires with different lengths of heat affected zone were not developed in this study, which limited their application with different loop height requirements.\u0000\u0000\u0000Practical implications\u0000With higher bonding strength and oxidation resistance, ACAA wires would be a better choice than previous reported AA wire in chip packaging which require high stability and reliability.\u0000\u0000\u0000Originality/value\u0000This paper provides a kind of novel ACAA wire, which possess the merits of high bonding strength and reliability, and show great potential in electronic packaging applications.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47577351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose Lapping is a vital flattening process to improve the quality of processed semiconductor wafers such as single-crystal sapphire wafers. This study aims to optimise the lapping process of the fixed-abrasive lapping plate of sapphire wafers with good overall performance [i.e. high material removal rate (MRR), small surface roughness (Ra) of the wafers after lapping and small lapping plate wear ratio (η)]. Design/methodology/approach The influence of process parameters such as lapping time, abrasive size, abrasive concentration, lapping pressure and lapping speed on MRR, Ra and η of lapping-processed sapphire wafers was studied, and the results were combined with experimental data to establish a regression model. The multi-evaluation index optimisation problem was transformed into a single-index optimisation problem via an entropy method and the grey relational analysis (GRA) to comprehensively evaluate the performance of each parameter. Findings The results revealed that lapping time, abrasive size, abrasive concentration, lapping pressure and lapping speed had different influence degrees on MRR, Ra and η. Among these parameters, lapping time, lapping speed and abrasive size had the most significant effects on MRR, Ra and η, and the established regression equations predicted the response values of MRR, Ra and η to be 99.56%, 99.51% and 93.88% and the relative errors between the predicted and actual measured values were <12%, respectively. With increased lapping time, MRR, Ra and η gradually decreased. With increased abrasive size, MRR increased nearly linearly, whereas Ra and η initially decreased but subsequently increased. With an increase in abrasive concentration, MRR, Ra and η initially increased but subsequently decreased. With increased lapping pressure, MRR and η increased nearly linearly and continuously, whereas Ra decreased nearly linearly and continuously. With increased lapping speed, Ra initially decreased sharply but subsequently increased gradually, whereas η initially increased sharply but subsequently decreased gradually; however, the change in MRR was not significant. Comparing the optimised results obtained via the analysis of influence law, the parameters optimised via the entropy method and GRA were used to obtain sapphire wafers lapping with an MRR of 4.26 µm/min, Ra of 0.141 µm and η of 25.08, and the lapping effect was significantly improved. Originality/value Therefore, GRA can provide new ideas for ultra-precision processing and process optimisation of semiconductor materials such as sapphire wafers.
{"title":"Surface quality prediction and lapping process optimisation on the fixed-abrasive lapping plate of sapphire wafers","authors":"Yanfu Wang, X. Wang, Lifei Liu","doi":"10.1108/mi-01-2022-0007","DOIUrl":"https://doi.org/10.1108/mi-01-2022-0007","url":null,"abstract":"\u0000Purpose\u0000Lapping is a vital flattening process to improve the quality of processed semiconductor wafers such as single-crystal sapphire wafers. This study aims to optimise the lapping process of the fixed-abrasive lapping plate of sapphire wafers with good overall performance [i.e. high material removal rate (MRR), small surface roughness (Ra) of the wafers after lapping and small lapping plate wear ratio (η)].\u0000\u0000\u0000Design/methodology/approach\u0000The influence of process parameters such as lapping time, abrasive size, abrasive concentration, lapping pressure and lapping speed on MRR, Ra and η of lapping-processed sapphire wafers was studied, and the results were combined with experimental data to establish a regression model. The multi-evaluation index optimisation problem was transformed into a single-index optimisation problem via an entropy method and the grey relational analysis (GRA) to comprehensively evaluate the performance of each parameter.\u0000\u0000\u0000Findings\u0000The results revealed that lapping time, abrasive size, abrasive concentration, lapping pressure and lapping speed had different influence degrees on MRR, Ra and η. Among these parameters, lapping time, lapping speed and abrasive size had the most significant effects on MRR, Ra and η, and the established regression equations predicted the response values of MRR, Ra and η to be 99.56%, 99.51% and 93.88% and the relative errors between the predicted and actual measured values were <12%, respectively. With increased lapping time, MRR, Ra and η gradually decreased. With increased abrasive size, MRR increased nearly linearly, whereas Ra and η initially decreased but subsequently increased. With an increase in abrasive concentration, MRR, Ra and η initially increased but subsequently decreased. With increased lapping pressure, MRR and η increased nearly linearly and continuously, whereas Ra decreased nearly linearly and continuously. With increased lapping speed, Ra initially decreased sharply but subsequently increased gradually, whereas η initially increased sharply but subsequently decreased gradually; however, the change in MRR was not significant. Comparing the optimised results obtained via the analysis of influence law, the parameters optimised via the entropy method and GRA were used to obtain sapphire wafers lapping with an MRR of 4.26 µm/min, Ra of 0.141 µm and η of 25.08, and the lapping effect was significantly improved.\u0000\u0000\u0000Originality/value\u0000Therefore, GRA can provide new ideas for ultra-precision processing and process optimisation of semiconductor materials such as sapphire wafers.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2022-08-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45828207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. M. Abed, S. M. Mohammad, Z. Hassan, A. Muhammad, Suvindraj Rajamanickam
Purpose The purpose of this study is to fabricate an ultraviolet (UV) metal-semiconductor-metal (MSM) photodetector based on zinc oxide nanorods (ZnO NRs) grown on seeded silicon (Si) substrate that was prepared by a low-cost method (drop-casting technique). Design/methodology/approach The drop-casting method was used for the seed layer deposition, the hydrothermal method was used for the growth of ZnO NRs and subsequent fabrication of UV MSM photodetector was done using the direct current sputtering technique. The performance of the fabricated MSM devices was investigated by current–voltage (I–V) measurements. The photodetection mechanism of the fabricated device was discussed. Findings Semi-vertically high-density ZnO (NRs) were effectively produced with a preferential orientation along the (002) direction, and increased crystallinity is confirmed by X-ray diffraction analysis. Photoluminescence results show a high UV region. The fabricated MSM UV photodetector showed that the ZnO (NRs) MSM device has great stability over time, high photocurrent, good sensitivity and high responsivity under 365 nm wavelength illumination and 0 V, 1 V, 2 V and 3 V applied bias. The responsivity and sensitivity for the fabricated ZnO NRs UV photodetector are 0.015 A W-1, 0.383 A W-1, 1.290 A W-1 and 1.982 A W-1 and 15,030, 42.639, 100.173 and 334.029, respectively, under UV light (365 nm) illumination at (0 V, 1 V, 2 V and 3 V). Originality/value This paper uses the drop-casting technique and the hydrothermal method as simple and low-cost methods to fabricate and improve the ZnO NRs photodetector.
{"title":"Fabrication of UV ZnO NRS photodetector based on seeded silicon substrate via the drop-casting technique","authors":"S. M. Abed, S. M. Mohammad, Z. Hassan, A. Muhammad, Suvindraj Rajamanickam","doi":"10.1108/mi-03-2022-0046","DOIUrl":"https://doi.org/10.1108/mi-03-2022-0046","url":null,"abstract":"\u0000Purpose\u0000The purpose of this study is to fabricate an ultraviolet (UV) metal-semiconductor-metal (MSM) photodetector based on zinc oxide nanorods (ZnO NRs) grown on seeded silicon (Si) substrate that was prepared by a low-cost method (drop-casting technique).\u0000\u0000\u0000Design/methodology/approach\u0000The drop-casting method was used for the seed layer deposition, the hydrothermal method was used for the growth of ZnO NRs and subsequent fabrication of UV MSM photodetector was done using the direct current sputtering technique. The performance of the fabricated MSM devices was investigated by current–voltage (I–V) measurements. The photodetection mechanism of the fabricated device was discussed.\u0000\u0000\u0000Findings\u0000Semi-vertically high-density ZnO (NRs) were effectively produced with a preferential orientation along the (002) direction, and increased crystallinity is confirmed by X-ray diffraction analysis. Photoluminescence results show a high UV region. The fabricated MSM UV photodetector showed that the ZnO (NRs) MSM device has great stability over time, high photocurrent, good sensitivity and high responsivity under 365 nm wavelength illumination and 0 V, 1 V, 2 V and 3 V applied bias. The responsivity and sensitivity for the fabricated ZnO NRs UV photodetector are 0.015 A W-1, 0.383 A W-1, 1.290 A W-1 and 1.982 A W-1 and 15,030, 42.639, 100.173 and 334.029, respectively, under UV light (365 nm) illumination at (0 V, 1 V, 2 V and 3 V).\u0000\u0000\u0000Originality/value\u0000This paper uses the drop-casting technique and the hydrothermal method as simple and low-cost methods to fabricate and improve the ZnO NRs photodetector.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2022-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49093657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ming-Xun Jiang, Mengyang Shi, Jiamao Li, Juan Liu, Lei Zhang, Jianyu Qin, Yongtao Jiu, Bin Tang, Dong Xu
Purpose This paper aims to study the effects of MnO2 on the ZnO–Bi2O3-based varistor prepared via flash sintering (FS) Design/methodology/approach MnO2-doped ZnO–Bi2O3-based varistors were successfully prepared by the FS with a step-wise increase of the .current in 60 s at the furnace temperature <750°C under the direct current electric field of 300 V cm−1. The FS process, microstructure and the electrical performance of ZnO–Bi2O3-based varistors were systematically investigated. Findings The doping of MnO2 significantly decreased the onset temperature of FS and improved the electrical performance of FS ZnO varistor ceramic. The sample with 0.5 mol% MnO2 doping shows the highest improvement, with the nonlinear coefficient of 18, the leakage current of 16.82 µA, the threshold voltage of 459 V/mm and the dielectric constant of 1,221 at 1 kHz. Originality/value FS is a wonderful technology to enhance ZnO varistors for its low energy consumption, and a short sintering time can reduce grain growth and inhabit Bi2O3 volatilize, yet few research studies work on that. In this research, the authors analyzed the FS process and improved the electrical characteristics through MnO2 doping.
目的研究MnO2对闪速烧结（FS）制备的ZnO–Bi2O3基压敏电阻的影响。设计/方法/方法在60 在300的直流电场下，炉温<750°C时的s V cm−1。系统地研究了ZnO–Bi2O3基压敏电阻的FS工艺、微观结构和电学性能。结果MnO2的掺杂显著降低了FS的起始温度，改善了FS-ZnO压敏陶瓷的电学性能。0.5的样品 mol%MnO2掺杂表现出最高的改善，非线性系数为18，漏电流为16.82 µA，阈值电压459 V/mm，介电常数为1221 kHz。Originality/valueFS是一种很好的增强ZnO压敏电阻的技术，因为它能耗低，而且短的烧结时间可以减少晶粒生长并抑制Bi2O3的挥发，但很少有研究对此进行研究。在本研究中，作者分析了FS工艺，并通过掺杂MnO2改善了电学特性。
{"title":"Microstructure and properties of ZnO-Bi2O3-based varistor ceramics via flash sintering","authors":"Ming-Xun Jiang, Mengyang Shi, Jiamao Li, Juan Liu, Lei Zhang, Jianyu Qin, Yongtao Jiu, Bin Tang, Dong Xu","doi":"10.1108/mi-05-2022-0079","DOIUrl":"https://doi.org/10.1108/mi-05-2022-0079","url":null,"abstract":"\u0000Purpose\u0000This paper aims to study the effects of MnO2 on the ZnO–Bi2O3-based varistor prepared via flash sintering (FS)\u0000\u0000\u0000Design/methodology/approach\u0000MnO2-doped ZnO–Bi2O3-based varistors were successfully prepared by the FS with a step-wise increase of the .current in 60 s at the furnace temperature <750°C under the direct current electric field of 300 V cm−1. The FS process, microstructure and the electrical performance of ZnO–Bi2O3-based varistors were systematically investigated.\u0000\u0000\u0000Findings\u0000The doping of MnO2 significantly decreased the onset temperature of FS and improved the electrical performance of FS ZnO varistor ceramic. The sample with 0.5 mol% MnO2 doping shows the highest improvement, with the nonlinear coefficient of 18, the leakage current of 16.82 µA, the threshold voltage of 459 V/mm and the dielectric constant of 1,221 at 1 kHz.\u0000\u0000\u0000Originality/value\u0000FS is a wonderful technology to enhance ZnO varistors for its low energy consumption, and a short sintering time can reduce grain growth and inhabit Bi2O3 volatilize, yet few research studies work on that. In this research, the authors analyzed the FS process and improved the electrical characteristics through MnO2 doping.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2022-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41786443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yumei Song, Jianzhang Hao, Changhao Dong, Xizheng Guo, Li Wang
Purpose This paper aims to study a multi-level reinjection current source converter (MLR-CSC) that adds attracting properties such as the self-commutation and pulse multiplication to the thyristor converter, which is of great significance for increasing the device capacity and reducing current harmonics on the grid side. Particularly, designing advantageous driving methods of the reinjection circuit is a critical issue that impacts the harmonic reduction and operation reliability of the MLR-CSC. Design/methodology/approach To deal with the mentioned issue, this paper takes the five-level reinjection current source converter (FLR-CSC), which is a type of the MLR-CSC, as the research object. Then, a method that can fully use combinations of five-level reinjection switching functions based on the concept of decomposition and recombination is proposed. It is worthy to mention that the proposed method can be easily extended to other multi-level reinjection circuits. Moreover, the working principle of the three-phase bridge circuit based on semi-controlled thyristors in the FLR-CSC that can achieve the four-quadrant power conversion is analyzed in detail. Findings Finally, the simulation and experimental results of FLR-CSC verify the effectiveness of the proposed reinjection circuit driving method and the operating principle of four-quadrant power conversion in this paper. Originality/value The outstanding features of the proposed driving method for FLR-CSC in this paper include combinations of reinjection switching functions that are fully exploited through three simple steps and can be conveniently extended to other multi-level reinjection circuits.
{"title":"An improved parallel five-level reinjection CSC for self-commutation of thyristor converter","authors":"Yumei Song, Jianzhang Hao, Changhao Dong, Xizheng Guo, Li Wang","doi":"10.1108/mi-05-2022-0093","DOIUrl":"https://doi.org/10.1108/mi-05-2022-0093","url":null,"abstract":"\u0000Purpose\u0000This paper aims to study a multi-level reinjection current source converter (MLR-CSC) that adds attracting properties such as the self-commutation and pulse multiplication to the thyristor converter, which is of great significance for increasing the device capacity and reducing current harmonics on the grid side. Particularly, designing advantageous driving methods of the reinjection circuit is a critical issue that impacts the harmonic reduction and operation reliability of the MLR-CSC.\u0000\u0000\u0000Design/methodology/approach\u0000To deal with the mentioned issue, this paper takes the five-level reinjection current source converter (FLR-CSC), which is a type of the MLR-CSC, as the research object. Then, a method that can fully use combinations of five-level reinjection switching functions based on the concept of decomposition and recombination is proposed. It is worthy to mention that the proposed method can be easily extended to other multi-level reinjection circuits. Moreover, the working principle of the three-phase bridge circuit based on semi-controlled thyristors in the FLR-CSC that can achieve the four-quadrant power conversion is analyzed in detail.\u0000\u0000\u0000Findings\u0000Finally, the simulation and experimental results of FLR-CSC verify the effectiveness of the proposed reinjection circuit driving method and the operating principle of four-quadrant power conversion in this paper.\u0000\u0000\u0000Originality/value\u0000The outstanding features of the proposed driving method for FLR-CSC in this paper include combinations of reinjection switching functions that are fully exploited through three simple steps and can be conveniently extended to other multi-level reinjection circuits.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2022-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48630410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Faheem, Muhammad Basit Azeem, A. A. Minhas, Shun'an Zhong, Xinghua Wang
Purpose RF transceiver module is considered a vital part of any wireless communication system. This module consists of two important parts the RF transceiver and analog-to-digital converter (ADC). Usually, both these parts – RF transceiver and ADC – are used to enhance the perspective of size and power. The data processing in 4G communication makes hurdles and need research attention to make it faster and smaller in size. Accuracy and fast processing are the critical challenges in the modern communication system. Design/methodology/approach After theoretical and practical investigations, this research work proposes key new techniques for the RF transceiver module. These techniques will make RF transceiver small, power-efficient and on the other hand, make dual SAR-ADC more effective as well. The proposed design has no intermediate frequency where the RF transceiver is reduced its major blocks from five to four, which includes crystal oscillator, phase lock loop, power amplifier and low noise amplifier. Moreover, the shared circuitry is introduced in the architecture of the SAR-ADC for the production of dual outputs, specifically in bootstrapped switch and comparator. Findings The miniaturized RF transceiver and SAR-ADC are well tested separately before the plantation on the printed circuit board (PCB). The operating voltage and frequency of the RF transceiver module are 1.2 V and 5.8 GHz, where the sampling rate, bandwidth and output power are 25 MHz, 200 MHz and 5 dBm, respectively. The core area of the PCB is 58.13 mm2. The bandwidth efficiency is 93% using surface acoustic wave less transmitter. The circuit is based on the library of 90 nm CMOS technology. Originality/value The entire circuit is highly synchronized with the input and reference clocks to avoid self-interference.
{"title":"Key techniques of ultra-low-power ADC and miniaturized RF transceiver circuits for 4G/LTE applications","authors":"M. Faheem, Muhammad Basit Azeem, A. A. Minhas, Shun'an Zhong, Xinghua Wang","doi":"10.1108/mi-06-2021-0054","DOIUrl":"https://doi.org/10.1108/mi-06-2021-0054","url":null,"abstract":"\u0000Purpose\u0000RF transceiver module is considered a vital part of any wireless communication system. This module consists of two important parts the RF transceiver and analog-to-digital converter (ADC). Usually, both these parts – RF transceiver and ADC – are used to enhance the perspective of size and power. The data processing in 4G communication makes hurdles and need research attention to make it faster and smaller in size. Accuracy and fast processing are the critical challenges in the modern communication system.\u0000\u0000\u0000Design/methodology/approach\u0000After theoretical and practical investigations, this research work proposes key new techniques for the RF transceiver module. These techniques will make RF transceiver small, power-efficient and on the other hand, make dual SAR-ADC more effective as well. The proposed design has no intermediate frequency where the RF transceiver is reduced its major blocks from five to four, which includes crystal oscillator, phase lock loop, power amplifier and low noise amplifier. Moreover, the shared circuitry is introduced in the architecture of the SAR-ADC for the production of dual outputs, specifically in bootstrapped switch and comparator.\u0000\u0000\u0000Findings\u0000The miniaturized RF transceiver and SAR-ADC are well tested separately before the plantation on the printed circuit board (PCB). The operating voltage and frequency of the RF transceiver module are 1.2 V and 5.8 GHz, where the sampling rate, bandwidth and output power are 25 MHz, 200 MHz and 5 dBm, respectively. The core area of the PCB is 58.13 mm2. The bandwidth efficiency is 93% using surface acoustic wave less transmitter. The circuit is based on the library of 90 nm CMOS technology.\u0000\u0000\u0000Originality/value\u0000The entire circuit is highly synchronized with the input and reference clocks to avoid self-interference.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2022-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48155245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Khairul Mohd Arshad, Muhamad Mat Noor, A. A. Manaf, Kawarada H., F. S., Syamsul M.
Purpose Vertical-cavity surface-emitting laser (VCSEL) is a high-performance semiconductor device made of unique epitaxial layers grown on n-type GaAs or InP substrates. The VCSEL’s thermal resistance, Rth, is an essential metric that reflects its thermal properties and dependability. The purpose of this paper is to develop packaging for 1 mm2 VCSEL chips made of a variety of materials, such as ceramic, lead frame and printed circuit board (PCB)-based packaging, as well as provide an idea or design that can withstand and perform well in terms of Rth and heat dissipation during operation. SolidWorks 2017 and AutoCAD Mechanical 2017 software were used to publish all thoughts and ideas, including the size dimensions (x, y and z) and material choices for each package. Design/methodology/approach Following the modelling and material selection, the next step is to use the Ansys Mechanical Structural FEA Analysis software to simulate all packaging for Rth and determine which packaging produced the best result, therefore, determining the heat dissipation for each packing. All parameters were used based on the standard cleanroom requirement for the industrial manufacturing backend process, where the cleanroom classification is 10,000 particles (ISO 7). The results demonstrated that the ceramic and lead frame provided good Rth values of 7.3 and 7.0 K/W, respectively, when compared to the PCB, which provided more than 80 K/W; thus, the heat dissipation for PCB packaging also increased. Findings As a result of the research, it was determined that ceramic and lead frame packaging are appropriate and capable of delivering good Rth and heat dissipation values when compared to PCB. In comparison to PCB, which requires numerous modifications, such as adding via holes and a thermal bar in an attempt to lower the Rth value, neither packaging requires improvement. Ceramic was chosen for development based on Rth's highest performance, with the actual device consisting of a lead frame and PCB. The Zth measurement test was carried out on a ceramic package, and the Rth result was comparable to the simulation result of 7.6 K/W, indicating that simulation was already proved for research and development. Originality/value The purpose of this study is to determine which proposed packaging design would give the highest Rth performance of a 1 mm2 chip as well as the best heat dissipation. In comparison to other studies, VCSEL packaging used the header and window cap as package components with a wavelength of 850 nm, and other VCSEL packaging developments used the sub mount on ceramic package with an output power ranging from 500 mW to 2 W, whereas this study used a huge wavelength and an output power of 4 W.
{"title":"Packaging design and thermal analysis for 1 mm2 high power VCSEL","authors":"Khairul Mohd Arshad, Muhamad Mat Noor, A. A. Manaf, Kawarada H., F. S., Syamsul M.","doi":"10.1108/mi-03-2022-0048","DOIUrl":"https://doi.org/10.1108/mi-03-2022-0048","url":null,"abstract":"\u0000Purpose\u0000Vertical-cavity surface-emitting laser (VCSEL) is a high-performance semiconductor device made of unique epitaxial layers grown on n-type GaAs or InP substrates. The VCSEL’s thermal resistance, Rth, is an essential metric that reflects its thermal properties and dependability. The purpose of this paper is to develop packaging for 1 mm2 VCSEL chips made of a variety of materials, such as ceramic, lead frame and printed circuit board (PCB)-based packaging, as well as provide an idea or design that can withstand and perform well in terms of Rth and heat dissipation during operation. SolidWorks 2017 and AutoCAD Mechanical 2017 software were used to publish all thoughts and ideas, including the size dimensions (x, y and z) and material choices for each package.\u0000\u0000\u0000Design/methodology/approach\u0000Following the modelling and material selection, the next step is to use the Ansys Mechanical Structural FEA Analysis software to simulate all packaging for Rth and determine which packaging produced the best result, therefore, determining the heat dissipation for each packing. All parameters were used based on the standard cleanroom requirement for the industrial manufacturing backend process, where the cleanroom classification is 10,000 particles (ISO 7). The results demonstrated that the ceramic and lead frame provided good Rth values of 7.3 and 7.0 K/W, respectively, when compared to the PCB, which provided more than 80 K/W; thus, the heat dissipation for PCB packaging also increased.\u0000\u0000\u0000Findings\u0000As a result of the research, it was determined that ceramic and lead frame packaging are appropriate and capable of delivering good Rth and heat dissipation values when compared to PCB. In comparison to PCB, which requires numerous modifications, such as adding via holes and a thermal bar in an attempt to lower the Rth value, neither packaging requires improvement. Ceramic was chosen for development based on Rth's highest performance, with the actual device consisting of a lead frame and PCB. The Zth measurement test was carried out on a ceramic package, and the Rth result was comparable to the simulation result of 7.6 K/W, indicating that simulation was already proved for research and development.\u0000\u0000\u0000Originality/value\u0000The purpose of this study is to determine which proposed packaging design would give the highest Rth performance of a 1 mm2 chip as well as the best heat dissipation. In comparison to other studies, VCSEL packaging used the header and window cap as package components with a wavelength of 850 nm, and other VCSEL packaging developments used the sub mount on ceramic package with an output power ranging from 500 mW to 2 W, whereas this study used a huge wavelength and an output power of 4 W.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2022-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47805695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Halo D. Omar, Auwal Abdulkadir, M. Hashim, M. Z. Pakhuruddin
Purpose This paper aims to present investigation on textured polyimide (PI) substrate for enhanced light absorption in flexible black silicon (bSi). Design/methodology/approach Flexible bSi with thickness of 60 µm is used in this work. To texture the PI substrate, copper-seeding technique is used. A copper (Cu) layer with a thickness of 100 nm is deposited on PI substrate by sputtering. The substrate is then annealed at 400°C in air ambient for different durations of 60, 90 and 120 min. Findings With 90 min of annealing, root mean square roughness as large as 130 nm, peak angle of 24° and angle distribution of up to 87° are obtained. With this texturing condition, the flexible bSi exhibits maximum potential short-circuit current density (Jmax) of 40.33 mA/cm2, or 0.45 mA/cm2 higher compared to the flexible bSi on planar PI. The improvement is attributed to enhanced light scattering at the flexible bSi/textured PI interface. The findings from this work demonstrate that the optimization of the PI texturing via Cu-seeding process leads to an enhancement in the long wavelengths light absorption and potential Jmax in the flexible bSi absorber. Originality/value Demonstrated enhanced light absorption and potential Jmax in flexible bSi on textured PI substrate (compared to planar PI substrate) by Cu-seeding with different annealing durations.
{"title":"Polyimide substrate textured by copper-seeding technique for enhanced light absorption in flexible black silicon","authors":"Halo D. Omar, Auwal Abdulkadir, M. Hashim, M. Z. Pakhuruddin","doi":"10.1108/mi-03-2022-0038","DOIUrl":"https://doi.org/10.1108/mi-03-2022-0038","url":null,"abstract":"\u0000Purpose\u0000This paper aims to present investigation on textured polyimide (PI) substrate for enhanced light absorption in flexible black silicon (bSi).\u0000\u0000\u0000Design/methodology/approach\u0000Flexible bSi with thickness of 60 µm is used in this work. To texture the PI substrate, copper-seeding technique is used. A copper (Cu) layer with a thickness of 100 nm is deposited on PI substrate by sputtering. The substrate is then annealed at 400°C in air ambient for different durations of 60, 90 and 120 min.\u0000\u0000\u0000Findings\u0000With 90 min of annealing, root mean square roughness as large as 130 nm, peak angle of 24° and angle distribution of up to 87° are obtained. With this texturing condition, the flexible bSi exhibits maximum potential short-circuit current density (Jmax) of 40.33 mA/cm2, or 0.45 mA/cm2 higher compared to the flexible bSi on planar PI. The improvement is attributed to enhanced light scattering at the flexible bSi/textured PI interface. The findings from this work demonstrate that the optimization of the PI texturing via Cu-seeding process leads to an enhancement in the long wavelengths light absorption and potential Jmax in the flexible bSi absorber.\u0000\u0000\u0000Originality/value\u0000Demonstrated enhanced light absorption and potential Jmax in flexible bSi on textured PI substrate (compared to planar PI substrate) by Cu-seeding with different annealing durations.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2022-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49077724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Muhammad, S. M. Mohammad, Z. Hassan, Suvindraj Rajamanickam, S. M. Abed, M. Ashiq
Purpose The purpose of this study is to dope silver (Ag) and fluorine (F) in zinc oxide (ZnO) for the enhancement of electrical and optical properties of ZnO, as previous studies reported the improvement of these properties using individual doping of F and Ag. In this paper, F and Ag co-doped ZnO nanorods were synthesized using a modified hydrothermal method. Design/methodology/approach The hydrothermal method was modified and used for the synthesis of the doped ZnO nanostructures, where stainless autoclave and oven were replaced with the Duran laboratory bottle and water boiler system in the process. The ultraviolet metal-semiconductor-metal photodetector (PD) was fabricated using DC sputtering method. Findings Vertically aligned nanorods images were captured from field emission scanning electron microscopy. XPS analysis confirmed greater spin-orbital interaction in the F and Ag co-doped ZnO sample and revealed the presence of F, Ag, Zn and O in the samples, indicating a successful doping process. X-ray diffraction revealed a hexagonal wurtzite structure with enhanced crystal quality upon co-doping. The bandgap decreased from 3.19 to 3.14 eV upon co-doping because of reduced defects density in the sample. Finally, an ultra-violet PD was fabricated with enhanced sensitivity and response times upon co-doping. Originality/value The low-cost, less energy-consuming Duran laboratory bottle and water boiler system were used as the substitute of expensive, more energy-consuming stainless autoclave and oven in a hydrothermal method for synthesis of F and Ag co-doped ZnO and subsequent fabrication of PD.
{"title":"Fabrication of fluorine and silver co-doped ZnO photodetector using modified hydrothermal method","authors":"A. Muhammad, S. M. Mohammad, Z. Hassan, Suvindraj Rajamanickam, S. M. Abed, M. Ashiq","doi":"10.1108/mi-03-2022-0045","DOIUrl":"https://doi.org/10.1108/mi-03-2022-0045","url":null,"abstract":"\u0000Purpose\u0000The purpose of this study is to dope silver (Ag) and fluorine (F) in zinc oxide (ZnO) for the enhancement of electrical and optical properties of ZnO, as previous studies reported the improvement of these properties using individual doping of F and Ag. In this paper, F and Ag co-doped ZnO nanorods were synthesized using a modified hydrothermal method.\u0000\u0000\u0000Design/methodology/approach\u0000The hydrothermal method was modified and used for the synthesis of the doped ZnO nanostructures, where stainless autoclave and oven were replaced with the Duran laboratory bottle and water boiler system in the process. The ultraviolet metal-semiconductor-metal photodetector (PD) was fabricated using DC sputtering method.\u0000\u0000\u0000Findings\u0000Vertically aligned nanorods images were captured from field emission scanning electron microscopy. XPS analysis confirmed greater spin-orbital interaction in the F and Ag co-doped ZnO sample and revealed the presence of F, Ag, Zn and O in the samples, indicating a successful doping process. X-ray diffraction revealed a hexagonal wurtzite structure with enhanced crystal quality upon co-doping. The bandgap decreased from 3.19 to 3.14 eV upon co-doping because of reduced defects density in the sample. Finally, an ultra-violet PD was fabricated with enhanced sensitivity and response times upon co-doping.\u0000\u0000\u0000Originality/value\u0000The low-cost, less energy-consuming Duran laboratory bottle and water boiler system were used as the substitute of expensive, more energy-consuming stainless autoclave and oven in a hydrothermal method for synthesis of F and Ag co-doped ZnO and subsequent fabrication of PD.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2022-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45961032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nur Atiqah Hamzah, Mohd Ann Amirul Zulffiqal Md Sahar, Aik Kwan Tan, Mohd Anas Ahmad, Muhammad Fadhirul Izwan Abdul Malik, Chin Chyi Loo, Wei Sea Chang, Sha Shiong Ng
Purpose
This study aims to investigate the effects of indium composition on surface morphology and optical properties of indium gallium nitride on gallium nitride (InGaN/GaN) heterostructures.
Design/methodology/approach
The InGaN/GaN heterostructures were grown on flat sapphire substrates using a metal-organic chemical vapour deposition reactor with a trimethylindium flow rate of 368 sccm. The indium composition of the InGaN epilayers was controlled by applying different substrate temperatures. The surface morphology and topography were observed using field emission scanning electron microscope (F.E.I. Nova NanoSEM 450) and atomic force microscopy (Bruker Dimension Edge) with a scanning area of 10 µm × 10 µm, respectively. The compositional analysis was done by Energy Dispersive X-Ray Analysis. Finally, the ultraviolet-visible (UV-Vis) spectrophotometer (Agilent Technology Cary Series UV-Vis-near-infrared spectrometer) was measured from 200 nm to 1500 nm to investigate the optical properties of the samples.
Findings
The InGaN/GaN thin films have been successfully grown at three different substrate temperatures. The indium composition reduced as the temperature increased. At 760 C, the highest indium composition was obtained, 21.17%. This result was acquired from the simulation fitting of ω−2θ scan on (0002) plane using LEPTOS software by Bruker D8 Discover. The InGaN/GaN shows significantly different surface morphologies and topographies as the indium composition increases. The thickness of InGaN epilayers of the structure was ∼300 nm estimated from the field emission scanning electron microscopy. The energy bandgap of the InGaN was 2.54 eV – 2.79 eV measured by UV-Vis measurements.
Originality/value
It can be seen from this work that changes in substrate temperature can affect the indium composition. From all the results obtained, this work can be helpful towards efficiency improvement in solar cell applications.
{"title":"Effects of indium composition on the surface morphological and optical properties of InGaN/GaN heterostructures","authors":"Nur Atiqah Hamzah, Mohd Ann Amirul Zulffiqal Md Sahar, Aik Kwan Tan, Mohd Anas Ahmad, Muhammad Fadhirul Izwan Abdul Malik, Chin Chyi Loo, Wei Sea Chang, Sha Shiong Ng","doi":"10.1108/mi-03-2022-0042","DOIUrl":"https://doi.org/10.1108/mi-03-2022-0042","url":null,"abstract":"<h3>Purpose</h3>\u0000<p>This study aims to investigate the effects of indium composition on surface morphology and optical properties of indium gallium nitride on gallium nitride (InGaN/GaN) heterostructures.</p><!--/ Abstract__block -->\u0000<h3>Design/methodology/approach</h3>\u0000<p>The InGaN/GaN heterostructures were grown on flat sapphire substrates using a metal-organic chemical vapour deposition reactor with a trimethylindium flow rate of 368 sccm. The indium composition of the InGaN epilayers was controlled by applying different substrate temperatures. The surface morphology and topography were observed using field emission scanning electron microscope (F.E.I. Nova NanoSEM 450) and atomic force microscopy (Bruker Dimension Edge) with a scanning area of 10 µm × 10 µm, respectively. The compositional analysis was done by Energy Dispersive X-Ray Analysis. Finally, the ultraviolet-visible (UV-Vis) spectrophotometer (Agilent Technology Cary Series UV-Vis-near-infrared spectrometer) was measured from 200 nm to 1500 nm to investigate the optical properties of the samples.</p><!--/ Abstract__block -->\u0000<h3>Findings</h3>\u0000<p>The InGaN/GaN thin films have been successfully grown at three different substrate temperatures. The indium composition reduced as the temperature increased. At 760 C, the highest indium composition was obtained, 21.17%. This result was acquired from the simulation fitting of ω−2θ scan on (0002) plane using LEPTOS software by Bruker D8 Discover. The InGaN/GaN shows significantly different surface morphologies and topographies as the indium composition increases. The thickness of InGaN epilayers of the structure was ∼300 nm estimated from the field emission scanning electron microscopy. The energy bandgap of the InGaN was 2.54 eV – 2.79 eV measured by UV-Vis measurements.</p><!--/ Abstract__block -->\u0000<h3>Originality/value</h3>\u0000<p>It can be seen from this work that changes in substrate temperature can affect the indium composition. From all the results obtained, this work can be helpful towards efficiency improvement in solar cell applications.</p><!--/ Abstract__block -->","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2022-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138513981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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