Purpose The purpose of this paper is to study the electronic transport performance of Ag-ZnO film under dark and UV light conditions. Design/methodology/approach Ag-doped ZnO thin films were prepared on fluorine thin oxide (FTO) substrates by sol-gel method. The crystal structure of ZnO and Ag-ZnO powders was tested by X-ray diffraction with Cu Kα radiation. The absorption spectra of ZnO and Ag-ZnO films were recorded by a UV–visible spectrophotometer. The micro electrical transport performance of Ag-ZnO thin films in dark and light state was investigated by photoassisted conductive atomic force microscope (PC-AFM). Findings The results show that the dark reverse current of Ag-ZnO films does not increase, but the reverse current increases significantly under illumination, indicating that the response of Ag-ZnO films to light is greatly improved, owing to the formation of Ohmic contact. Originality/value To the best of the author’s knowledge, the micro electrical transport performance of Ag-ZnO thin films in dark and light state was firstly investigated by PC-AFM.
{"title":"Study on electronic transport performance of Ag-ZnO film by photoassisted conductive atomic force microscopy","authors":"Yidong Zhang","doi":"10.1108/mi-02-2023-0017","DOIUrl":"https://doi.org/10.1108/mi-02-2023-0017","url":null,"abstract":"\u0000Purpose\u0000The purpose of this paper is to study the electronic transport performance of Ag-ZnO film under dark and UV light conditions.\u0000\u0000\u0000Design/methodology/approach\u0000Ag-doped ZnO thin films were prepared on fluorine thin oxide (FTO) substrates by sol-gel method. The crystal structure of ZnO and Ag-ZnO powders was tested by X-ray diffraction with Cu Kα radiation. The absorption spectra of ZnO and Ag-ZnO films were recorded by a UV–visible spectrophotometer. The micro electrical transport performance of Ag-ZnO thin films in dark and light state was investigated by photoassisted conductive atomic force microscope (PC-AFM).\u0000\u0000\u0000Findings\u0000The results show that the dark reverse current of Ag-ZnO films does not increase, but the reverse current increases significantly under illumination, indicating that the response of Ag-ZnO films to light is greatly improved, owing to the formation of Ohmic contact.\u0000\u0000\u0000Originality/value\u0000To the best of the author’s knowledge, the micro electrical transport performance of Ag-ZnO thin films in dark and light state was firstly investigated by PC-AFM.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62093625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hao Chen, Fan Yang, M. Aguirre, Muhammad Asghar Saqib, G. Demidova, A. Anuchin, M. Orabi, R. Palka, L. Sakhno, N. Korovkin
Purpose Because of the shortage of energy, the development of green and reliable energy is particularly important. As a green and clean energy, wind power is widely used. As the core component of wind power generation, it is particularly important to choose generators with high reliability. Switched reluctance machine is widely used as generators because of its strong fault tolerance and high reliability. Therefore, this paper aims to propose a power converter and its control strategy to improve the efficiency of switched reluctance generators. Design/methodology/approach In this paper, a full-bridge power converter (FBPC) instead of the asymmetric half-bridge power converter (AHBPC) is adopted to drive the switched reluctance generator (SRG) system. Compare the FBPC with the AHBPC, the FBPC has several advantages including low cost and modularization, and operation process of SRG winding current direction is variable. Findings The results show that the SRG system can keep smooth operation by the FBPC with relatively high efficiency. Originality/value The FBPC is suitable to drive the SRG system. Meanwhile, this paper introduces two excitation modes of the FBPC as three-phase three-beat mode and six-phase six-beat mode. When the six-phase six-beat control strategy is adopted, the dead band time of the converter can be avoided. At the same time, the SRG has higher efficiency.
{"title":"Bipolar power converter and control of switched reluctance generator system for renewable energy storage","authors":"Hao Chen, Fan Yang, M. Aguirre, Muhammad Asghar Saqib, G. Demidova, A. Anuchin, M. Orabi, R. Palka, L. Sakhno, N. Korovkin","doi":"10.1108/mi-07-2022-0135","DOIUrl":"https://doi.org/10.1108/mi-07-2022-0135","url":null,"abstract":"\u0000Purpose\u0000Because of the shortage of energy, the development of green and reliable energy is particularly important. As a green and clean energy, wind power is widely used. As the core component of wind power generation, it is particularly important to choose generators with high reliability. Switched reluctance machine is widely used as generators because of its strong fault tolerance and high reliability. Therefore, this paper aims to propose a power converter and its control strategy to improve the efficiency of switched reluctance generators.\u0000\u0000\u0000Design/methodology/approach\u0000In this paper, a full-bridge power converter (FBPC) instead of the asymmetric half-bridge power converter (AHBPC) is adopted to drive the switched reluctance generator (SRG) system. Compare the FBPC with the AHBPC, the FBPC has several advantages including low cost and modularization, and operation process of SRG winding current direction is variable.\u0000\u0000\u0000Findings\u0000The results show that the SRG system can keep smooth operation by the FBPC with relatively high efficiency.\u0000\u0000\u0000Originality/value\u0000The FBPC is suitable to drive the SRG system. Meanwhile, this paper introduces two excitation modes of the FBPC as three-phase three-beat mode and six-phase six-beat mode. When the six-phase six-beat control strategy is adopted, the dead band time of the converter can be avoided. At the same time, the SRG has higher efficiency.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49536814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose This study aims to investigate the ammonia-sensing performance of polyaniline/polyethylene oxide (PANI/PEO) and polyaniline/polyethylene oxide/zinc oxide (PANI/PEO-ZnO) composite nanofibers at room temperature. Design/methodology/approach Gas sensor structures were fabricated using microfabrication techniques. First, onto the SiO 2 wafer, gold electrodes were fabricated via thermal evaporation. PANI/PEO nanofibers were produced by the electrospinning method, and the ZnO layer was deposited by using radio frequency (RF) magnetron sputtering on the electrospun nanofibers as a sensing layer. Fourier transform infrared spectroscopy (FTIR), scanning electron microscopy (SEM) and X-ray diffraction were performed to characterize the analysis of nanofibers. After all, gas sensing analysis of PANI/PEO and PANI/PEO/ZnO nanofibers was conducted using an experimental setup at room temperature conditions. Furthermore, the impact of humidity (17%–90% RH) on the sensor resistance was actively investigated. Findings FTIR analysis confirms the presence of functional groups of PANI, PEO and ZnO in nanofiber structure. SEM micrographs demonstrate beads-free, thinner and smooth nanofibers with ZnO contribution to electrospun PANI/PEO nanofibers. Moreover, according to the gas sensing results, the PANI/PEO nanofibers exhibit 115 s and 457 s response time and recovery time, respectively. However, the PANI/PEO/ZnO nanofibers exhibit 245 s and 153 s response time and recovery time, respectively. PANI/PEO/MOx composite nanofibers ensure stability to the NH 3 gas owing to the high surface/volume ratio and decrease in the humidity dependence of gas sensors, making gas sensors more stable to the environment. Originality/value In this study, ZnO was deposited via RF magnetron sputtering techniques on PANI/PEO nanofibers as a different approach instead of in situ polymerization to investigate and enhance the sensor response and recovery time of the PANI/PEO/ZnO and PANI/PEO composite nanofibers to ammonia. These results indicated that ZnO can enhance the sensing properties of conductive polymer-based resistive sensors.
{"title":"A chemosensitive-based ammonia gas sensor with PANI/PEO–ZnO nanofiber composites sensing layer","authors":"Gözde Konuk Ege, Özge Akay, Hüseyin Yüce","doi":"10.1108/mi-04-2023-0051","DOIUrl":"https://doi.org/10.1108/mi-04-2023-0051","url":null,"abstract":"Purpose This study aims to investigate the ammonia-sensing performance of polyaniline/polyethylene oxide (PANI/PEO) and polyaniline/polyethylene oxide/zinc oxide (PANI/PEO-ZnO) composite nanofibers at room temperature. Design/methodology/approach Gas sensor structures were fabricated using microfabrication techniques. First, onto the SiO 2 wafer, gold electrodes were fabricated via thermal evaporation. PANI/PEO nanofibers were produced by the electrospinning method, and the ZnO layer was deposited by using radio frequency (RF) magnetron sputtering on the electrospun nanofibers as a sensing layer. Fourier transform infrared spectroscopy (FTIR), scanning electron microscopy (SEM) and X-ray diffraction were performed to characterize the analysis of nanofibers. After all, gas sensing analysis of PANI/PEO and PANI/PEO/ZnO nanofibers was conducted using an experimental setup at room temperature conditions. Furthermore, the impact of humidity (17%–90% RH) on the sensor resistance was actively investigated. Findings FTIR analysis confirms the presence of functional groups of PANI, PEO and ZnO in nanofiber structure. SEM micrographs demonstrate beads-free, thinner and smooth nanofibers with ZnO contribution to electrospun PANI/PEO nanofibers. Moreover, according to the gas sensing results, the PANI/PEO nanofibers exhibit 115 s and 457 s response time and recovery time, respectively. However, the PANI/PEO/ZnO nanofibers exhibit 245 s and 153 s response time and recovery time, respectively. PANI/PEO/MOx composite nanofibers ensure stability to the NH 3 gas owing to the high surface/volume ratio and decrease in the humidity dependence of gas sensors, making gas sensors more stable to the environment. Originality/value In this study, ZnO was deposited via RF magnetron sputtering techniques on PANI/PEO nanofibers as a different approach instead of in situ polymerization to investigate and enhance the sensor response and recovery time of the PANI/PEO/ZnO and PANI/PEO composite nanofibers to ammonia. These results indicated that ZnO can enhance the sensing properties of conductive polymer-based resistive sensors.","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134959860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose Quantitative reliability analysis can effectively identify the time the driving system needs to be maintained. Then, the potential safety problems can be found, and some catastrophic failures can be effectively prevented. Therefore, this paper aims to evaluate the reliability of the switched reluctance generator (SRG) driving system. Design/methodology/approach In this paper, a method considering different thermal stresses and fault tolerance capacity is proposed to analyze the reliability of an SRG. A full-bridge power converter (FBPC) instead of the asymmetric half-bridge power converter (AHBPC) is adopted to drive the SRG system. First, the primary fault modes of the SRG system are introduced, and a fault criterion is proposed to determine whether the system fails. Second, the thermal circuit model of the converter is established to quickly and accurately obtain the junction temperature of the devices. At last, the Markov models of different levels are established to evaluate the reliability of the system. Findings The results show that the two-level Markov model is the most suitable when compared to the static model and the one-level Markov model. Originality/value The driving system of SRG will be more reliable after the reliability of the system is evaluated by the Markov model. At the same time, an FBPC is adopted to drive the SRG. The FBPCs have the advantages of fewer switching devices, higher integration and lower cost. The proposed driving strategy of the FBPC avoids the current reversal and the generation of dead zone time, which has the advantage of reliable operation. In addition, a precise thermal circuit model of the FBPC is proposed, and the junction temperature of each device can be obtained, respectively.
{"title":"Reliability evaluation on SRG with full-bridge power converter considering thermal stress","authors":"Fan Yang, Hao Chen, Shuai Xu","doi":"10.1108/mi-06-2022-0094","DOIUrl":"https://doi.org/10.1108/mi-06-2022-0094","url":null,"abstract":"\u0000Purpose\u0000Quantitative reliability analysis can effectively identify the time the driving system needs to be maintained. Then, the potential safety problems can be found, and some catastrophic failures can be effectively prevented. Therefore, this paper aims to evaluate the reliability of the switched reluctance generator (SRG) driving system.\u0000\u0000\u0000Design/methodology/approach\u0000In this paper, a method considering different thermal stresses and fault tolerance capacity is proposed to analyze the reliability of an SRG. A full-bridge power converter (FBPC) instead of the asymmetric half-bridge power converter (AHBPC) is adopted to drive the SRG system. First, the primary fault modes of the SRG system are introduced, and a fault criterion is proposed to determine whether the system fails. Second, the thermal circuit model of the converter is established to quickly and accurately obtain the junction temperature of the devices. At last, the Markov models of different levels are established to evaluate the reliability of the system.\u0000\u0000\u0000Findings\u0000The results show that the two-level Markov model is the most suitable when compared to the static model and the one-level Markov model.\u0000\u0000\u0000Originality/value\u0000The driving system of SRG will be more reliable after the reliability of the system is evaluated by the Markov model. At the same time, an FBPC is adopted to drive the SRG. The FBPCs have the advantages of fewer switching devices, higher integration and lower cost. The proposed driving strategy of the FBPC avoids the current reversal and the generation of dead zone time, which has the advantage of reliable operation. In addition, a precise thermal circuit model of the FBPC is proposed, and the junction temperature of each device can be obtained, respectively.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47031817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose The aim of this study is to make a contribution towards reducing the deflections of silicon wafers. The deformation of silicon wafers used in the manufacture of electronic micro-components is one of the most common problems encountered by industrialists during manufacturing. Stack warping is typically produced during the process of depositing thin layers on a substrate. This is due to the thermal-mechanical stresses caused by the difference between the thermal expansion coefficients of the materials. Reducing wafer deformation is essential to increase reliability and improve quality. In this paper, the authors propose an approach based on minimal geometrical modifications to reduce the deformation of a silicon wafer coated with two thin layers. Numerical finite element models have been developed to evaluate the impact of geometrical modifications on warping amplitude. Finite element models have been validated compared with experimental models. The results obtained are encouraging and clearly show a considerable reduction in wafer deformation. Design/methodology/approach Reducing wafer deformation is essential to increase reliability and improve quality. In this paper, the authors propose an approach based on minimal geometrical modifications to reduce the deformation of a silicon wafer coated with two thin layers. Numerical finite element models have been developed to evaluate the impact of geometrical modifications on warping amplitude. Finite element models have been validated compared with experimental models. Findings The results obtained are encouraging and clearly show a considerable reduction in wafer deformation. Originality/value This paper describes the influence of geometric modification on wafer deformation. The work show also the cruciality of stress reduction in the purpose to obtain less wafer deformation.
{"title":"Reduction of the warping of a silicon wafer coated with two thin layers by minimal geometric modifications","authors":"Imad El Fatmi, S. Belhenini, A. Tougui","doi":"10.1108/mi-02-2022-0025","DOIUrl":"https://doi.org/10.1108/mi-02-2022-0025","url":null,"abstract":"\u0000Purpose\u0000The aim of this study is to make a contribution towards reducing the deflections of silicon wafers. The deformation of silicon wafers used in the manufacture of electronic micro-components is one of the most common problems encountered by industrialists during manufacturing. Stack warping is typically produced during the process of depositing thin layers on a substrate. This is due to the thermal-mechanical stresses caused by the difference between the thermal expansion coefficients of the materials. Reducing wafer deformation is essential to increase reliability and improve quality. In this paper, the authors propose an approach based on minimal geometrical modifications to reduce the deformation of a silicon wafer coated with two thin layers. Numerical finite element models have been developed to evaluate the impact of geometrical modifications on warping amplitude. Finite element models have been validated compared with experimental models. The results obtained are encouraging and clearly show a considerable reduction in wafer deformation.\u0000\u0000\u0000Design/methodology/approach\u0000Reducing wafer deformation is essential to increase reliability and improve quality. In this paper, the authors propose an approach based on minimal geometrical modifications to reduce the deformation of a silicon wafer coated with two thin layers. Numerical finite element models have been developed to evaluate the impact of geometrical modifications on warping amplitude. Finite element models have been validated compared with experimental models.\u0000\u0000\u0000Findings\u0000The results obtained are encouraging and clearly show a considerable reduction in wafer deformation.\u0000\u0000\u0000Originality/value\u0000This paper describes the influence of geometric modification on wafer deformation. The work show also the cruciality of stress reduction in the purpose to obtain less wafer deformation.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44230919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose Wafer bonding is a key process for 3 D advanced packaging of integrated circuits. It requires very high accuracy for the wafer alignment. To solve the problems of large movement stroke, position calibration error and low production efficiency in optical alignment, this paper aims to propose a new wafer magnetic alignment technology (MAT) which is based on tunnel magneto resistance effect. MAT can realize micro distance alignment and reduces the design and manufacturing difficulty of wafer bonding equipment. Design/methodology/approach The current methods and existing problems of wafer optical alignment are introduced, and the mechanism and realization process of wafer magnetic alignment are proposed. Micro magnetic column (MMC) marks are designed on the wafer by the semiconductor manufacturing process. The mathematical model of the space magnetic field of the MMC is established, and the magnetic field distribution of the MMC alignment is numerically simulated and visualized. The relationship between the alignment accuracy and the MMC diameter, MMC remanence, MMC thickness and sensor measurement height was studied. Findings The simulation analysis shows that the overlapping double MMCs can align the wafer with accuracy within 1 µm and can control the bonding distance within the micrometer range to improve the alignment efficiency. Originality/value Magnetic alignment technology provides a new idea for wafer bonding alignment, which is expected to improve the accuracy and efficiency of wafer bonding.
{"title":"Magnetic alignment technology for wafer bonding","authors":"L. Ye, Xuanjie Song, Chang Yue","doi":"10.1108/mi-08-2022-0160","DOIUrl":"https://doi.org/10.1108/mi-08-2022-0160","url":null,"abstract":"\u0000Purpose\u0000Wafer bonding is a key process for 3 D advanced packaging of integrated circuits. It requires very high accuracy for the wafer alignment. To solve the problems of large movement stroke, position calibration error and low production efficiency in optical alignment, this paper aims to propose a new wafer magnetic alignment technology (MAT) which is based on tunnel magneto resistance effect. MAT can realize micro distance alignment and reduces the design and manufacturing difficulty of wafer bonding equipment.\u0000\u0000\u0000Design/methodology/approach\u0000The current methods and existing problems of wafer optical alignment are introduced, and the mechanism and realization process of wafer magnetic alignment are proposed. Micro magnetic column (MMC) marks are designed on the wafer by the semiconductor manufacturing process. The mathematical model of the space magnetic field of the MMC is established, and the magnetic field distribution of the MMC alignment is numerically simulated and visualized. The relationship between the alignment accuracy and the MMC diameter, MMC remanence, MMC thickness and sensor measurement height was studied.\u0000\u0000\u0000Findings\u0000The simulation analysis shows that the overlapping double MMCs can align the wafer with accuracy within 1 µm and can control the bonding distance within the micrometer range to improve the alignment efficiency.\u0000\u0000\u0000Originality/value\u0000Magnetic alignment technology provides a new idea for wafer bonding alignment, which is expected to improve the accuracy and efficiency of wafer bonding.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47176512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose Au stud bump bonding technology is an effective means to realize heterogeneous integration of commercial chips in the 2.5D electronic packaging. The purpose of this paper is to study the long-term reliability of the Au stud bump treated by four different high temperature storage times (200°C for 0, 100, 200 and 300 h). Design/methodology/approach The bonding strength and the fracture behavior are investigated by chip shear test. The experiment is further studied by microstructural characterization approaches such as scanning electron microscope, energy dispersive spectrometer and so on. Findings It is recognized that there were mainly three typical fracture models during the chip shear test among all the Au stud bump samples treated by high temperature storage. For solder bump before aging, the fracture occurred at the interface between the Cu pad and the Au stud bump. As the aging time increased, the fracture mainly occurred inside the Au stud bump at 200°C for 100 and 200 h. When aging time increased to 300 h, it is found that the fracture transferred to the interface between the Au stud bump and the Al Pad. Originality/value In addition, the bonding strength also changed with the high temperature storage time increasing. The bonding strength does not change linearly with the high temperature storage time increasing but decreases first and then increases. The investigation shows that the formation of the intermetallic compounds because of the reaction between the Au and Al atoms plays a key role on the bonding strength and fracture behavior variation.
{"title":"Experimental study on the fracture behavior variation of the Au stud bump bonding with different high temperature storage times","authors":"Xiangou Zhang, Yuexing Wang, Xiangyu Sun, Zejia Deng, Y. Pu, Ping Zhang, Zhiyong Huang, Quanfeng Zhou","doi":"10.1108/mi-12-2022-0203","DOIUrl":"https://doi.org/10.1108/mi-12-2022-0203","url":null,"abstract":"\u0000Purpose\u0000Au stud bump bonding technology is an effective means to realize heterogeneous integration of commercial chips in the 2.5D electronic packaging. The purpose of this paper is to study the long-term reliability of the Au stud bump treated by four different high temperature storage times (200°C for 0, 100, 200 and 300 h).\u0000\u0000\u0000Design/methodology/approach\u0000The bonding strength and the fracture behavior are investigated by chip shear test. The experiment is further studied by microstructural characterization approaches such as scanning electron microscope, energy dispersive spectrometer and so on.\u0000\u0000\u0000Findings\u0000It is recognized that there were mainly three typical fracture models during the chip shear test among all the Au stud bump samples treated by high temperature storage. For solder bump before aging, the fracture occurred at the interface between the Cu pad and the Au stud bump. As the aging time increased, the fracture mainly occurred inside the Au stud bump at 200°C for 100 and 200 h. When aging time increased to 300 h, it is found that the fracture transferred to the interface between the Au stud bump and the Al Pad.\u0000\u0000\u0000Originality/value\u0000In addition, the bonding strength also changed with the high temperature storage time increasing. The bonding strength does not change linearly with the high temperature storage time increasing but decreases first and then increases. The investigation shows that the formation of the intermetallic compounds because of the reaction between the Au and Al atoms plays a key role on the bonding strength and fracture behavior variation.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42635013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose Solder bumps for chip interconnections are downsizing from current approximately 100 µm to the expected 1 µm in future. As a result, the Cu-Ni cross-interaction in Cu/Solder/Ni solder joints will be more complicated and then strongly influence the growth of the intermetallic compounds (IMCs). Thus, it is critical to understand the fundamental aspects of interfacial reaction in micro solder joints. This paper aims to reveal the effect mechanism of reflow temperature and solder size on the interfacial reaction in Cu/Solder/Ni solder joints. Design/methodology/approach The Cu-Ni cross-interaction in the Cu/Sn/Ni micro solder joints with 50 and 100 µm solder sizes at 250°C and 300°C were observed, respectively. The line-type interconnects were soaked in silicone oil, and the temperature of the line-type interconnects was 250 ± 3°C and 300 ± 3°C, which were monitored by a fine K-type thermocouple, and followed by an isothermal aging process at various times. After aging, the specimens were removed from the silicone oil and cooled in the air to room temperature. Findings The major interfacial reaction product on both interfaces was (Cu,Ni)6Sn5, and the asymmetric growth of (Cu,Ni)6Sn5, evidenced by the thickness of (Cu,Ni)6Sn5 IMCs at the Sn/Ni interface was always larger than that at the Sn/Cu interface, resulted from the directional migration of Cu atoms toward the Sn/Ni interface under Cu concentration gradient. The morphology of (Cu,Ni)6Sn5 IMC at Sn/Cu interface was columnlike at 250°C, and which changed from columnlike to scallop with large aspect ratio at 300°C, while that at Sn/Ni interface gradually evolved from needlelike to the mixture of needlelike and layered at 250°C, and which evolved from needlelike to scallop with large aspect ratio at 300°C. The evolution of morphology of (Cu,Ni)6Sn5 is attributed to the content of Ni. Furthermore, the results indicate that the Cu-Ni cross-interaction was stronger with small solder size and relatively low temperature in the Cu/Sn/Ni micro solder joints. Originality/value The asymmetric growth of (Cu,Ni)6Sn5 in the Cu/Sn/Ni micro solder joints, evidenced by the thickness of (Cu,Ni)6Sn5 IMCs at the Sn/Ni interface, was always larger than that at the Sn/Cu interface. The morphology evolution of (Cu,Ni)6Sn5 IMC at both interfaces was attributed to the content of Ni. The Cu-Ni cross-interaction was stronger with small solder size and relatively low temperature in the Cu/Sn/Ni micro solder joints.
{"title":"Effect of reflow temperature and solder size on Cu-Ni cross-interaction in the Cu/Sn/Ni micro solder joints","authors":"","doi":"10.1108/mi-09-2022-0173","DOIUrl":"https://doi.org/10.1108/mi-09-2022-0173","url":null,"abstract":"\u0000Purpose\u0000Solder bumps for chip interconnections are downsizing from current approximately 100 µm to the expected 1 µm in future. As a result, the Cu-Ni cross-interaction in Cu/Solder/Ni solder joints will be more complicated and then strongly influence the growth of the intermetallic compounds (IMCs). Thus, it is critical to understand the fundamental aspects of interfacial reaction in micro solder joints. This paper aims to reveal the effect mechanism of reflow temperature and solder size on the interfacial reaction in Cu/Solder/Ni solder joints.\u0000\u0000\u0000Design/methodology/approach\u0000The Cu-Ni cross-interaction in the Cu/Sn/Ni micro solder joints with 50 and 100 µm solder sizes at 250°C and 300°C were observed, respectively. The line-type interconnects were soaked in silicone oil, and the temperature of the line-type interconnects was 250 ± 3°C and 300 ± 3°C, which were monitored by a fine K-type thermocouple, and followed by an isothermal aging process at various times. After aging, the specimens were removed from the silicone oil and cooled in the air to room temperature.\u0000\u0000\u0000Findings\u0000The major interfacial reaction product on both interfaces was (Cu,Ni)6Sn5, and the asymmetric growth of (Cu,Ni)6Sn5, evidenced by the thickness of (Cu,Ni)6Sn5 IMCs at the Sn/Ni interface was always larger than that at the Sn/Cu interface, resulted from the directional migration of Cu atoms toward the Sn/Ni interface under Cu concentration gradient. The morphology of (Cu,Ni)6Sn5 IMC at Sn/Cu interface was columnlike at 250°C, and which changed from columnlike to scallop with large aspect ratio at 300°C, while that at Sn/Ni interface gradually evolved from needlelike to the mixture of needlelike and layered at 250°C, and which evolved from needlelike to scallop with large aspect ratio at 300°C. The evolution of morphology of (Cu,Ni)6Sn5 is attributed to the content of Ni. Furthermore, the results indicate that the Cu-Ni cross-interaction was stronger with small solder size and relatively low temperature in the Cu/Sn/Ni micro solder joints.\u0000\u0000\u0000Originality/value\u0000The asymmetric growth of (Cu,Ni)6Sn5 in the Cu/Sn/Ni micro solder joints, evidenced by the thickness of (Cu,Ni)6Sn5 IMCs at the Sn/Ni interface, was always larger than that at the Sn/Cu interface. The morphology evolution of (Cu,Ni)6Sn5 IMC at both interfaces was attributed to the content of Ni. The Cu-Ni cross-interaction was stronger with small solder size and relatively low temperature in the Cu/Sn/Ni micro solder joints.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47144272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose Laser soldering has attracted attention as an alternative soldering process for microsoldering due to its localized and noncontact heating, a rapid rise and fall in temperature, fluxless and easy automation compared to reflow soldering. Design/methodology/approach In this study, the metallurgical and mechanical properties of the Sn3.0Ag0.5Cu/Ni-P joints after laser and reflow soldering and isothermal aging were compared and analyzed. Findings In the as-soldered Sn3.0Ag0.5Cu/Ni-P joints, a small granular and loose (Cu,Ni)6Sn5 intermetallic compound (IMC) structure was formed by laser soldering regardless of the laser energy, and a long and needlelike (Cu,Ni)6Sn5 IMC structure was generated by reflow soldering. During aging at 150°C, the growth rate of the IMC layer was faster by laser soldering than by reflow soldering. The shear strength of as-soldered joints for reflow soldering was similar to that of laser soldering with 7.5 mJ, which sharply decreased from 0 to 100 h for both cases and then was maintained at a similar level with increasing aging time. Originality/value Laser soldering with certain energy is effective for reducing the thickness of IMCs, and ensuring the mechanical property of the joints was similar to reflow soldering.
{"title":"Comparative study on solid-solid interfacial reaction and bonding property of Sn-Ag-Cu/Ni-P joints by laser and reflow soldering","authors":"Yuehua Wu, Z.J. Zhang, L.D. Chen, X. Zhou","doi":"10.1108/mi-11-2022-0185","DOIUrl":"https://doi.org/10.1108/mi-11-2022-0185","url":null,"abstract":"\u0000Purpose\u0000Laser soldering has attracted attention as an alternative soldering process for microsoldering due to its localized and noncontact heating, a rapid rise and fall in temperature, fluxless and easy automation compared to reflow soldering.\u0000\u0000\u0000Design/methodology/approach\u0000In this study, the metallurgical and mechanical properties of the Sn3.0Ag0.5Cu/Ni-P joints after laser and reflow soldering and isothermal aging were compared and analyzed.\u0000\u0000\u0000Findings\u0000In the as-soldered Sn3.0Ag0.5Cu/Ni-P joints, a small granular and loose (Cu,Ni)6Sn5 intermetallic compound (IMC) structure was formed by laser soldering regardless of the laser energy, and a long and needlelike (Cu,Ni)6Sn5 IMC structure was generated by reflow soldering. During aging at 150°C, the growth rate of the IMC layer was faster by laser soldering than by reflow soldering. The shear strength of as-soldered joints for reflow soldering was similar to that of laser soldering with 7.5 mJ, which sharply decreased from 0 to 100 h for both cases and then was maintained at a similar level with increasing aging time.\u0000\u0000\u0000Originality/value\u0000Laser soldering with certain energy is effective for reducing the thickness of IMCs, and ensuring the mechanical property of the joints was similar to reflow soldering.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47988335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose The purpose of chopper amplifier is to provide the wideband frequency to support biomedical signals. Design/methodology/approach This paper proposes a chopper-stabilized amplifier with a cascoded operational transconductance amplifier. The high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor. Findings The total power consumption is 451 nW with a supplied voltage of 800 mV. The Gain and common mode rejection ratio are 48 dB and 78 dB, respectively. Research limitations/implications All kinds of real time data analysis was not carried out, only few test samples related to EEG signals are validated because the real time chip was not manufactured due to funding issues. Practical implications The proposed work was validated with Monte-Carlo simulations. There is no external funding for the proposed work. So there is no fabrication for the design. But post simulations are performed. Originality/value The high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor. To the best of the author’s knowledge, this concept is completely novel and there are no publications on this work. All the modules designed for chopper amplifier are new concepts.
{"title":"A chopper amplifier with a pseudo MOS resistor-based tunable bandwidth for EEG applications","authors":"Amrita Sajja, S. Rooban","doi":"10.1108/mi-06-2022-0106","DOIUrl":"https://doi.org/10.1108/mi-06-2022-0106","url":null,"abstract":"\u0000Purpose\u0000The purpose of chopper amplifier is to provide the wideband frequency to support biomedical signals.\u0000\u0000\u0000Design/methodology/approach\u0000This paper proposes a chopper-stabilized amplifier with a cascoded operational transconductance amplifier. The high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor.\u0000\u0000\u0000Findings\u0000The total power consumption is 451 nW with a supplied voltage of 800 mV. The Gain and common mode rejection ratio are 48 dB and 78 dB, respectively.\u0000\u0000\u0000Research limitations/implications\u0000All kinds of real time data analysis was not carried out, only few test samples related to EEG signals are validated because the real time chip was not manufactured due to funding issues.\u0000\u0000\u0000Practical implications\u0000The proposed work was validated with Monte-Carlo simulations. There is no external funding for the proposed work. So there is no fabrication for the design. But post simulations are performed.\u0000\u0000\u0000Originality/value\u0000The high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor. To the best of the author’s knowledge, this concept is completely novel and there are no publications on this work. All the modules designed for chopper amplifier are new concepts.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43763692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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