Purpose The purpose of this paper is to show a possibility to measure a change of a contact angle during the melting in real-time and to reveal significant factors of a wettability. Influence of the flux with combination of plasma on copper surface was investigated in experiment as well. Design/methodology/approach Laboratory equipment consists of heating and optical part that was developed and tested for real-time contact angle’s measurements. Solder balls based on Sn96.5/Ag3/Cu0.5 and Sn63Pb37 spread out on a copper substrate during a melting process. The wettability of pure copper surface was compared with copper surface treated with flux or combination plasma–flux. The contact angle and spreading rate of a melted solder balls observed by the charged-coupled device camera were analyzed in real-time and measured using the JavaScript. Findings Laboratory equipment allows for analysis of contact angle and spreading rate in real-time during the melting process. The contact angle decreases more noticeable after applying the plasma-flux treatment in contrast to no flux or flux treatment only. Using the plasma treatment before application of the flux improves the wettability and the effectivity of the flux activity on the copper surface during the melting process. Originality/value The interpretation of the results of such a comprehensive measurement leads to a better understanding of the mutual relation between flux and combination plasma–flux of the wetting during the melting process. The simple, cheap, fast and accurate laboratory equipment, which consists of the heating and the optical part, allows for the wettability evaluation of the melting process in real-time.
{"title":"Real-time contact angle’s measurement of molten solder balls in laboratory conditions","authors":"Daniel Dzivý, A. Pietrikova","doi":"10.1108/mi-12-2021-0122","DOIUrl":"https://doi.org/10.1108/mi-12-2021-0122","url":null,"abstract":"\u0000Purpose\u0000The purpose of this paper is to show a possibility to measure a change of a contact angle during the melting in real-time and to reveal significant factors of a wettability. Influence of the flux with combination of plasma on copper surface was investigated in experiment as well.\u0000\u0000\u0000Design/methodology/approach\u0000Laboratory equipment consists of heating and optical part that was developed and tested for real-time contact angle’s measurements. Solder balls based on Sn96.5/Ag3/Cu0.5 and Sn63Pb37 spread out on a copper substrate during a melting process. The wettability of pure copper surface was compared with copper surface treated with flux or combination plasma–flux. The contact angle and spreading rate of a melted solder balls observed by the charged-coupled device camera were analyzed in real-time and measured using the JavaScript.\u0000\u0000\u0000Findings\u0000Laboratory equipment allows for analysis of contact angle and spreading rate in real-time during the melting process. The contact angle decreases more noticeable after applying the plasma-flux treatment in contrast to no flux or flux treatment only. Using the plasma treatment before application of the flux improves the wettability and the effectivity of the flux activity on the copper surface during the melting process.\u0000\u0000\u0000Originality/value\u0000The interpretation of the results of such a comprehensive measurement leads to a better understanding of the mutual relation between flux and combination plasma–flux of the wetting during the melting process. The simple, cheap, fast and accurate laboratory equipment, which consists of the heating and the optical part, allows for the wettability evaluation of the melting process in real-time.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2022-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49239559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose Modern wireless communications need novel microwave components that can be effectively used for high data rate and low-power applications. The operating environment decides the severity of the noise coupled to the transceiver system from the ambient environment. In a deep fading environment, narrowband systems fail where the wideband systems come for rescue. Thus, the microwave components are ought to switch between the narrowband and wideband states. This paper aims to study the design of a bandpass filter to meet the requirements by appropriately switching between the dual narrowband frequencies and single ultra-wideband frequency band. Design/methodology/approach The design and implementation of a compact microwave filter with reconfigurable bandwidth characteristics are presented in this paper. The proposed filter is constructed using a hexagonal ring with shorted perturbation along one corner. The filter is capacitively coupled to the external excitation source. External stubs are connected to the corners of the hexagonal resonator to obtain dual passband characteristics centred at 2.1 and 4.5 GHz. The external stubs are configured to achieve bandwidth reconfigurable characteristics. PIN diodes are used with a suitable biasing network to obtain reconfiguration. In the reconfigured state, the proposed two-port filter offers a continuous bandwidth from 2.1 to 5.9 GHz. The roll-off rate along the band edges is improved by increasing the order of the filter. Findings The proposed filter operates in two states. In state 1, the filter operates with dual frequencies centred around 2 and 4.5 GHz with insertion loss less than <1 dB and return loss greater than 13 dB with a peak return loss of 21 and 31 dB at 2.1 and 2.15 GHz, respectively. In state 2, the filter operates from 2.1 to 5.9 GHz with insertion loss less than 1 dB and return loss greater than 12 dB. The filter exhibits four-pole characteristics with a peak return loss greater than 22 dB. Thus, the fractional bandwidth of the proposed filter is 17% and 16% in state 1, whereas the fractional bandwidth is 95% in state 2. Originality/value The proposed filter is the first of its kind to simultaneously offer miniaturization and bandwidth reconfiguration. The proposed second-order filter has two-pole characteristics in the narrowband state, whereas four-pole characteristics are realized in the wideband state. The growing interest in 4G and 5G wireless communications makes the proposed filter a suitable candidate for operation in the rich scattering environment.
{"title":"Miniaturized bandwidth reconfigurable microwave bandpass filter","authors":"P. P., M. J.","doi":"10.1108/mi-03-2022-0032","DOIUrl":"https://doi.org/10.1108/mi-03-2022-0032","url":null,"abstract":"\u0000Purpose\u0000Modern wireless communications need novel microwave components that can be effectively used for high data rate and low-power applications. The operating environment decides the severity of the noise coupled to the transceiver system from the ambient environment. In a deep fading environment, narrowband systems fail where the wideband systems come for rescue. Thus, the microwave components are ought to switch between the narrowband and wideband states. This paper aims to study the design of a bandpass filter to meet the requirements by appropriately switching between the dual narrowband frequencies and single ultra-wideband frequency band.\u0000\u0000\u0000Design/methodology/approach\u0000The design and implementation of a compact microwave filter with reconfigurable bandwidth characteristics are presented in this paper. The proposed filter is constructed using a hexagonal ring with shorted perturbation along one corner. The filter is capacitively coupled to the external excitation source. External stubs are connected to the corners of the hexagonal resonator to obtain dual passband characteristics centred at 2.1 and 4.5 GHz. The external stubs are configured to achieve bandwidth reconfigurable characteristics. PIN diodes are used with a suitable biasing network to obtain reconfiguration. In the reconfigured state, the proposed two-port filter offers a continuous bandwidth from 2.1 to 5.9 GHz. The roll-off rate along the band edges is improved by increasing the order of the filter.\u0000\u0000\u0000Findings\u0000The proposed filter operates in two states. In state 1, the filter operates with dual frequencies centred around 2 and 4.5 GHz with insertion loss less than <1 dB and return loss greater than 13 dB with a peak return loss of 21 and 31 dB at 2.1 and 2.15 GHz, respectively. In state 2, the filter operates from 2.1 to 5.9 GHz with insertion loss less than 1 dB and return loss greater than 12 dB. The filter exhibits four-pole characteristics with a peak return loss greater than 22 dB. Thus, the fractional bandwidth of the proposed filter is 17% and 16% in state 1, whereas the fractional bandwidth is 95% in state 2.\u0000\u0000\u0000Originality/value\u0000The proposed filter is the first of its kind to simultaneously offer miniaturization and bandwidth reconfiguration. The proposed second-order filter has two-pole characteristics in the narrowband state, whereas four-pole characteristics are realized in the wideband state. The growing interest in 4G and 5G wireless communications makes the proposed filter a suitable candidate for operation in the rich scattering environment.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48592202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fatimah Zulkifli, R. Radzali, A. F. Abd Rahim, A. Mahmood, N. S. Mohd Razali, Aslina Abu Bakar
Purpose Porous silicon (Si) was fabricated by using three different wet etching methods, namely, direct current photo-assisted electrochemical (DCPEC), alternating CPEC (ACPEC) and two-step ACPEC etching. This study aims to investigate the structural properties of porous structures formed by using these etching methods and to identify which etching method works best. Design/methodology/approach Si n(100) was used to fabricate porous Si using three different etching methods (DCPEC, ACPEC and two-step ACPEC). All the samples were etched with the same current density and etching duration. The samples were etched by using hydrofluoric acid-based electrolytes under the illumination of an incandescent lamp. Findings Field emission scanning electron microscopy (FESEM) images showed that porous Si etched using the two-step ACPEC method has a higher porosity and density than porous Si etched using DCPEC and ACPEC. The atomic force microscopy results supported the FESEM results showing that porous Si etched using the two-step ACPEC method has the highest surface roughness relative to the samples produced using the other two methods. High resolution X-ray diffraction revealed that porous Si produced through two-step ACPEC has the highest peak intensity out of the three porous Si samples suggesting an improvement in pore uniformity with a better crystalline quality. Originality/value Two-step ACPEC method is a fairly new etching method and many of its fundamental properties are yet to be established. This work presents a comparison of the effect of these three different etching methods on the structural properties of Si. The results obtained indicated that the two-step ACPEC method produced an etched sample with a higher porosity, pore density, surface roughness, improvement in uniformity of pores and better crystalline quality than the other etching methods.
{"title":"Influence of different etching methods on the structural properties of porous silicon","authors":"Fatimah Zulkifli, R. Radzali, A. F. Abd Rahim, A. Mahmood, N. S. Mohd Razali, Aslina Abu Bakar","doi":"10.1108/mi-01-2022-0009","DOIUrl":"https://doi.org/10.1108/mi-01-2022-0009","url":null,"abstract":"\u0000Purpose\u0000Porous silicon (Si) was fabricated by using three different wet etching methods, namely, direct current photo-assisted electrochemical (DCPEC), alternating CPEC (ACPEC) and two-step ACPEC etching. This study aims to investigate the structural properties of porous structures formed by using these etching methods and to identify which etching method works best.\u0000\u0000\u0000Design/methodology/approach\u0000Si n(100) was used to fabricate porous Si using three different etching methods (DCPEC, ACPEC and two-step ACPEC). All the samples were etched with the same current density and etching duration. The samples were etched by using hydrofluoric acid-based electrolytes under the illumination of an incandescent lamp.\u0000\u0000\u0000Findings\u0000Field emission scanning electron microscopy (FESEM) images showed that porous Si etched using the two-step ACPEC method has a higher porosity and density than porous Si etched using DCPEC and ACPEC. The atomic force microscopy results supported the FESEM results showing that porous Si etched using the two-step ACPEC method has the highest surface roughness relative to the samples produced using the other two methods. High resolution X-ray diffraction revealed that porous Si produced through two-step ACPEC has the highest peak intensity out of the three porous Si samples suggesting an improvement in pore uniformity with a better crystalline quality.\u0000\u0000\u0000Originality/value\u0000Two-step ACPEC method is a fairly new etching method and many of its fundamental properties are yet to be established. This work presents a comparison of the effect of these three different etching methods on the structural properties of Si. The results obtained indicated that the two-step ACPEC method produced an etched sample with a higher porosity, pore density, surface roughness, improvement in uniformity of pores and better crystalline quality than the other etching methods.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2022-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41574814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose The purpose of this paper is to investigate the effects of the sintering temperature on the microstructural, morphological and electrical characteristics of Zinc oxide (ZnO)-based varistors. Design/methodology/approach This study used a conventional method to design and produce ZnO varistors by sintering ZnO powder with small amounts of various metal oxides. Furthermore, the effect of sintering temperature on varistor properties of (Bi, Co, Cr, Sb, Mn)-doped ZnO ceramics was investigated in the range of 1280–1350 °C. Findings The obtained results showed an EB value of 2109.79 V/cm, a Vgb value of 0.831 V and a nonlinear coefficient (α) value of 19.91 for sample sintered at temperature of 1300 °C. In addition, the low value of tan δ at low frequency range confirmed that the grain boundaries created in 1300 °C sintering temperature were obviously good. Originality/value Based on the previous research on the ZnO-based varistors, a thorough study was carried out on these components to improve their electrical characteristics. Thus, it is necessary that those varistors have low leakage current and low value of dissipation factor to ensure their good quality. High breakdown fields and nonlinearity coefficients are also required in such kind of components. The effect of sintering temperature on the varistor properties of the new compositions (zinc, bismuth, manganese, chrome, cobalt, antimony and silicon oxides)-doped ZnO ceramics was studied in the range of 1280–1350 °C. Also, the microstructure and the phase evolution of the samples sintered at various temperatures (1280 °C, 1300 °C, 1320 °C and 1350 °C) were investigated according to X-ray diffraction and scanning electron microscope measurements.
{"title":"Synthesis and characterization of ZnO based varistor ceramics: effect of sintering temperatures","authors":"A. Bouchekhlal, M. Boulesbaa","doi":"10.1108/mi-01-2022-0005","DOIUrl":"https://doi.org/10.1108/mi-01-2022-0005","url":null,"abstract":"\u0000Purpose\u0000The purpose of this paper is to investigate the effects of the sintering temperature on the microstructural, morphological and electrical characteristics of Zinc oxide (ZnO)-based varistors.\u0000\u0000\u0000Design/methodology/approach\u0000This study used a conventional method to design and produce ZnO varistors by sintering ZnO powder with small amounts of various metal oxides. Furthermore, the effect of sintering temperature on varistor properties of (Bi, Co, Cr, Sb, Mn)-doped ZnO ceramics was investigated in the range of 1280–1350 °C.\u0000\u0000\u0000Findings\u0000The obtained results showed an EB value of 2109.79 V/cm, a Vgb value of 0.831 V and a nonlinear coefficient (α) value of 19.91 for sample sintered at temperature of 1300 °C. In addition, the low value of tan δ at low frequency range confirmed that the grain boundaries created in 1300 °C sintering temperature were obviously good.\u0000\u0000\u0000Originality/value\u0000Based on the previous research on the ZnO-based varistors, a thorough study was carried out on these components to improve their electrical characteristics. Thus, it is necessary that those varistors have low leakage current and low value of dissipation factor to ensure their good quality. High breakdown fields and nonlinearity coefficients are also required in such kind of components. The effect of sintering temperature on the varistor properties of the new compositions (zinc, bismuth, manganese, chrome, cobalt, antimony and silicon oxides)-doped ZnO ceramics was studied in the range of 1280–1350 °C. Also, the microstructure and the phase evolution of the samples sintered at various temperatures (1280 °C, 1300 °C, 1320 °C and 1350 °C) were investigated according to X-ray diffraction and scanning electron microscope measurements.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2022-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43028009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose This paper is aimed to study the design of a miniaturized filter with tri-band characteristics. In this paper, perturbation is used to realize circuit miniaturization and multi-band by exploiting the inductive property. During this process, vias are added for twofold benefit, namely, circuit miniaturization and enhanced frequency selectivity at high frequency. Thus, with the introduction of the shorting via, the single-band dual-mode bandpass filter is converted into a tri-band filter with a smaller electrical size. Design/methodology/approach This paper presents the design and characterization of a miniaturized two-port filter with tri-band operating characteristics. The proposed filter is constructed using a square patch resonator operating at 5.2 GHz with a capacitively coupled feed configuration. A square perturbation is added to the corner of the square patch to achieve diagonal symmetry and to excite dual mode. The perturbation offers a sharp transmission zero defining bandwidth of the proposed filter. In addition, a shorting post is introduced to achieve an 88% size reduction by lowering the operating frequency to 1.8 GHz. Findings The prototype filter has insertion less than 1.2 dB and return loss better than 12 dB throughout all the realized frequency bands. The prototype filter is fabricated and the simulation results are validated using experimental measurements. The realized fractional bandwidths of the proposed bandpass filter are 11/5.6/1 at 1.8/4.6/5.85 GHz, respectively. The quality factor of the proposed antenna is greater than 80 and a peak Q-factor of 387 is realized at 5.85 GHz. The high Q-factor indicates low loss and improved selectivity. The rejection levels in the stopband are greater than 20 dB. Originality/value The results indicate that the proposed filter is a suitable choice for low-power small-scale wireless systems operating in the microwave bands. The realized filter has the smallest footprint of 0.36λeff × 0.19λeff where λeff is the effective wavelength calculated at the lowest frequency of operation.
{"title":"Design and implementation of miniaturized tri-band microwave bandpass filter","authors":"P. P., M. J.","doi":"10.1108/mi-12-2021-0119","DOIUrl":"https://doi.org/10.1108/mi-12-2021-0119","url":null,"abstract":"\u0000Purpose\u0000This paper is aimed to study the design of a miniaturized filter with tri-band characteristics. In this paper, perturbation is used to realize circuit miniaturization and multi-band by exploiting the inductive property. During this process, vias are added for twofold benefit, namely, circuit miniaturization and enhanced frequency selectivity at high frequency. Thus, with the introduction of the shorting via, the single-band dual-mode bandpass filter is converted into a tri-band filter with a smaller electrical size.\u0000\u0000\u0000Design/methodology/approach\u0000This paper presents the design and characterization of a miniaturized two-port filter with tri-band operating characteristics. The proposed filter is constructed using a square patch resonator operating at 5.2 GHz with a capacitively coupled feed configuration. A square perturbation is added to the corner of the square patch to achieve diagonal symmetry and to excite dual mode. The perturbation offers a sharp transmission zero defining bandwidth of the proposed filter. In addition, a shorting post is introduced to achieve an 88% size reduction by lowering the operating frequency to 1.8 GHz.\u0000\u0000\u0000Findings\u0000The prototype filter has insertion less than 1.2 dB and return loss better than 12 dB throughout all the realized frequency bands. The prototype filter is fabricated and the simulation results are validated using experimental measurements. The realized fractional bandwidths of the proposed bandpass filter are 11/5.6/1 at 1.8/4.6/5.85 GHz, respectively. The quality factor of the proposed antenna is greater than 80 and a peak Q-factor of 387 is realized at 5.85 GHz. The high Q-factor indicates low loss and improved selectivity. The rejection levels in the stopband are greater than 20 dB.\u0000\u0000\u0000Originality/value\u0000The results indicate that the proposed filter is a suitable choice for low-power small-scale wireless systems operating in the microwave bands. The realized filter has the smallest footprint of 0.36λeff × 0.19λeff where λeff is the effective wavelength calculated at the lowest frequency of operation.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2022-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43692810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. S. Mohamed Sunar, M. Abu Bakar, A. Jalar, Mohamad Riduwan Ramli, F. Che Ani
Purpose Reflow solder joint quality is significantly affected by the ability of the solder to perfectly fill pad space and retain good solder joint shape. This study aims to investigate solder joint quality by quantitatively analyzing the stencil printing-deposited solder volume, solder height and solder coverage area. Design/methodology/approach The dispensability of different solder paste types on printed circuit board (PCB) pads using different stencil aperture shapes was evaluated. Lead-free Type 4 (20–38 µm particle size) and Type 5 (15–25 µm particle size) solder pastes were used to create solder joints according to standard reflow soldering. Findings The results show that the stencil aperture shape greatly affects the solder joint quality as compared with the type of solder paste. These investigations allow the development of new strategies for solving solder paste stencil printing issues and evaluating the quality of solder joints. Originality/value The reflow soldering process requires the appropriate selection of the stencil aperture shape according to the PCB and the solder paste according to the particle-size distribution of the solder alloy powder. However, there are scarce studies on the effects of stencil aperture shape and the solder alloy particle size on the solder paste space-filling ability.
{"title":"Effect of alloy particle size and stencil aperture shape on solder printing quality","authors":"M. S. Mohamed Sunar, M. Abu Bakar, A. Jalar, Mohamad Riduwan Ramli, F. Che Ani","doi":"10.1108/mi-12-2021-0121","DOIUrl":"https://doi.org/10.1108/mi-12-2021-0121","url":null,"abstract":"\u0000Purpose\u0000Reflow solder joint quality is significantly affected by the ability of the solder to perfectly fill pad space and retain good solder joint shape. This study aims to investigate solder joint quality by quantitatively analyzing the stencil printing-deposited solder volume, solder height and solder coverage area.\u0000\u0000\u0000Design/methodology/approach\u0000The dispensability of different solder paste types on printed circuit board (PCB) pads using different stencil aperture shapes was evaluated. Lead-free Type 4 (20–38 µm particle size) and Type 5 (15–25 µm particle size) solder pastes were used to create solder joints according to standard reflow soldering.\u0000\u0000\u0000Findings\u0000The results show that the stencil aperture shape greatly affects the solder joint quality as compared with the type of solder paste. These investigations allow the development of new strategies for solving solder paste stencil printing issues and evaluating the quality of solder joints.\u0000\u0000\u0000Originality/value\u0000The reflow soldering process requires the appropriate selection of the stencil aperture shape according to the PCB and the solder paste according to the particle-size distribution of the solder alloy powder. However, there are scarce studies on the effects of stencil aperture shape and the solder alloy particle size on the solder paste space-filling ability.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2022-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48930403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose The paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The advanced encryption standard (AES) and PRESENT block ciphers are deployed together, leading to a common crypto chip for performing encryption and decryption operations. Design/methodology/approach An integrated very large-scale integration (VLSI) architecture and its implementation for the AES and PRESENT ciphers is proposed. As per the choice, the architecture performs encryption or decryption operations for the selected cipher. Experimental results of the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations and related design analysis are provided. Findings FPGA implementation of the architecture on Xilinx xc5vfx70t-1-ff1136 device consumes 19% slices, whereas the ASIC design is implemented in 180 nm complementary metal-oxide semiconductor ASIC technology that takes 1.0746 mm2 of standard cell area and consumes 14.26 mW of power at 50 MHz clock frequency. A secure audio application using the designed architecture on an open source SoC environment is also provided. A test methodology for validation of the designed chip using an FPGA-based platform and tools is discussed. Originality/value The proposed architecture is compared with a set of existing hardware architectures for analyzing various design metrics such as latency, area, maximum operating frequency, power, and throughput.
{"title":"Design, integration and implementation of crypto cores in an SoC environment","authors":"J. Pandey, Sanskriti Gupta, A. Karmakar","doi":"10.1108/mi-09-2021-0091","DOIUrl":"https://doi.org/10.1108/mi-09-2021-0091","url":null,"abstract":"\u0000Purpose\u0000The paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The advanced encryption standard (AES) and PRESENT block ciphers are deployed together, leading to a common crypto chip for performing encryption and decryption operations.\u0000\u0000\u0000Design/methodology/approach\u0000An integrated very large-scale integration (VLSI) architecture and its implementation for the AES and PRESENT ciphers is proposed. As per the choice, the architecture performs encryption or decryption operations for the selected cipher. Experimental results of the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations and related design analysis are provided.\u0000\u0000\u0000Findings\u0000FPGA implementation of the architecture on Xilinx xc5vfx70t-1-ff1136 device consumes 19% slices, whereas the ASIC design is implemented in 180 nm complementary metal-oxide semiconductor ASIC technology that takes 1.0746 mm2 of standard cell area and consumes 14.26 mW of power at 50 MHz clock frequency. A secure audio application using the designed architecture on an open source SoC environment is also provided. A test methodology for validation of the designed chip using an FPGA-based platform and tools is discussed.\u0000\u0000\u0000Originality/value\u0000The proposed architecture is compared with a set of existing hardware architectures for analyzing various design metrics such as latency, area, maximum operating frequency, power, and throughput.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2022-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49373147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose This paper aims to propose a cylindrical conformal wideband antenna with increased directive behaviour using integrated parasitic triangular-shaped elements for WiMAX application. Design/methodology/approach The proposed antenna is a wideband directional cylindrical conformal antenna consisting of three fork-shaped dipole elements incorporated with parasitic triangular-shaped reflecting components increases the gain of reference conformal antenna. The novel parasitic elements with triangular shapes are designed on the radiating patch as well as the ground plane side. The parasitic triangular elements enable the antenna to enhance the gain along the end-fire direction. Findings The proposed antenna has a 20.2% impedance bandwidth ranging from 3.1 to 3.8 GHz. The half power beam-width (HPBW) of the reference antenna in the H-plane is 122.9° and falls to 99.1° after integrating with parasitic elements at 3.3 GHz, whereas it falls from 56.7° to 54.7° in the E-plane. However, at 3.5 GHz, the reference antenna’s HPBW is at 116.8°, which decreases to 92.4° in the H-plane, whereas it reduces from 57.9 to 53.4° in the E-plane. The proposed antenna has a lower HPBW than reference antennas and achieved a gain enhancement of 1.2 dBi, indicating that the pattern becomes more directed. Originality/value In the proposed work, the directive behaviour of cylindrical conformal antenna structure with a 30 mm radius of curvature is improved using parasitic reflective elements. The fabricated antennas’ experimental findings are an excellent contender for wireless point-to-point WiMAX applications because it features a wideband, directional properties, and strong gain over the whole operational frequency range of 3.1–3.8 GHz.
{"title":"Cylindrical conformal wideband antenna with enhancement of gain using integrated parasitic triangular shaped elements for WiMAX application","authors":"Ratikanta Sahoo","doi":"10.1108/mi-11-2021-0115","DOIUrl":"https://doi.org/10.1108/mi-11-2021-0115","url":null,"abstract":"\u0000Purpose\u0000This paper aims to propose a cylindrical conformal wideband antenna with increased directive behaviour using integrated parasitic triangular-shaped elements for WiMAX application.\u0000\u0000\u0000Design/methodology/approach\u0000The proposed antenna is a wideband directional cylindrical conformal antenna consisting of three fork-shaped dipole elements incorporated with parasitic triangular-shaped reflecting components increases the gain of reference conformal antenna. The novel parasitic elements with triangular shapes are designed on the radiating patch as well as the ground plane side. The parasitic triangular elements enable the antenna to enhance the gain along the end-fire direction.\u0000\u0000\u0000Findings\u0000The proposed antenna has a 20.2% impedance bandwidth ranging from 3.1 to 3.8 GHz. The half power beam-width (HPBW) of the reference antenna in the H-plane is 122.9° and falls to 99.1° after integrating with parasitic elements at 3.3 GHz, whereas it falls from 56.7° to 54.7° in the E-plane. However, at 3.5 GHz, the reference antenna’s HPBW is at 116.8°, which decreases to 92.4° in the H-plane, whereas it reduces from 57.9 to 53.4° in the E-plane. The proposed antenna has a lower HPBW than reference antennas and achieved a gain enhancement of 1.2 dBi, indicating that the pattern becomes more directed.\u0000\u0000\u0000Originality/value\u0000In the proposed work, the directive behaviour of cylindrical conformal antenna structure with a 30 mm radius of curvature is improved using parasitic reflective elements. The fabricated antennas’ experimental findings are an excellent contender for wireless point-to-point WiMAX applications because it features a wideband, directional properties, and strong gain over the whole operational frequency range of 3.1–3.8 GHz.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2022-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44624876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Synkiewicz-Musialska, D. Szwagierczak, J. Kulawik, E. Czerwińska
Purpose This paper aims to report on fabrication procedure and presents microstructure and dielectric behaviour of LiZn0.92Cu0.08PO4 ceramic material with Li2CO3 as a sintering aid. Design/methodology/approach Substrates based on LiZn0.92Cu0.08PO4 with Li2CO3 addition were prepared via solid-state synthesis, doping, milling, pressing and sintering. Characterization of the composition, microstructure and dielectric properties was performed using X-ray diffractometry, energy dispersive spectroscopy, scanning electron microscopy, impedance spectroscopy in the 100 Hz to 2 MHz range and time-domain spectroscopy in the 0.1–3 THz range. Findings Doped LiZnPO4 ceramic, which exhibits a low dielectric constant of 5.9 at 1 THz and low sintering temperature of 800 °C, suitable for low temperature co-fired ceramics (LTCC) technology, was successfully prepared. However, further studies are needed to lower dielectric losses by optimising the doping level, synthesis and sintering conditions. Originality/value Search for new low dielectric constant materials applicable in LTCC technology and optimization of processing are essential tasks for developing modern microwave circuits. The dielectric characterization of doped LiZnPO4 ceramic in the terahertz range, which was performed for the first time, is crucial for potential millimetre-wave applications of this substrate material.
{"title":"Preparation and characterization of doped LiZn0.92Cu0.08PO4 ceramic for microwave and millimeter-wave substrates","authors":"B. Synkiewicz-Musialska, D. Szwagierczak, J. Kulawik, E. Czerwińska","doi":"10.1108/mi-07-2021-0068","DOIUrl":"https://doi.org/10.1108/mi-07-2021-0068","url":null,"abstract":"\u0000Purpose\u0000This paper aims to report on fabrication procedure and presents microstructure and dielectric behaviour of LiZn0.92Cu0.08PO4 ceramic material with Li2CO3 as a sintering aid.\u0000\u0000\u0000Design/methodology/approach\u0000Substrates based on LiZn0.92Cu0.08PO4 with Li2CO3 addition were prepared via solid-state synthesis, doping, milling, pressing and sintering. Characterization of the composition, microstructure and dielectric properties was performed using X-ray diffractometry, energy dispersive spectroscopy, scanning electron microscopy, impedance spectroscopy in the 100 Hz to 2 MHz range and time-domain spectroscopy in the 0.1–3 THz range.\u0000\u0000\u0000Findings\u0000Doped LiZnPO4 ceramic, which exhibits a low dielectric constant of 5.9 at 1 THz and low sintering temperature of 800 °C, suitable for low temperature co-fired ceramics (LTCC) technology, was successfully prepared. However, further studies are needed to lower dielectric losses by optimising the doping level, synthesis and sintering conditions.\u0000\u0000\u0000Originality/value\u0000Search for new low dielectric constant materials applicable in LTCC technology and optimization of processing are essential tasks for developing modern microwave circuits. The dielectric characterization of doped LiZnPO4 ceramic in the terahertz range, which was performed for the first time, is crucial for potential millimetre-wave applications of this substrate material.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2022-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49072407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. S., Zuvairiya Parveen J., Y. D., Venkadeshwari E.
Purpose The purpose of this paper is to present the design of a compact microstrip bandpass filter (BPF) in dual-mode configuration loaded with cross-loop and square ring slots on a square patch resonator for C-band applications. Design/methodology/approach In the proposed design, the dual-mode response for the filter is realized with two transmission zeros (TZs) by the insertion of a perturbation element at the diagonal corner of the square patch resonator with orthogonal feed lines. Such TZs at the edges of the passband result in better selectivity for the proposed BPF. Moreover, the cross-loop and square ring slots are etched on a square patch resonator to obtain a miniaturized BPF. Findings The proposed dual-mode microstrip filter fabricated in RT/duroid 6010 substrate using PCB technology has a measured minimum insertion loss of 1.8 dB and return loss better than 24.5 dB with a fractional bandwidth (FBW) of 6.9%. A compact size of 7.35 × 7.35 mm2 is achieved for the slotted patch resonator-based dual-mode BPF at the center frequency of 4.76 GHz. As compared with the conventional square patch resonator, a size reduction of 61% is achieved with the proposed slotted design. The feasibility of the filter design is confirmed by the good agreement between the measured and simulated responses. The performance of the proposed filter structure is compared with other dual-mode filter works. Originality/value In the proposed work, a compact dual-mode BPF is reported with slotted structures. The conventional square patch resonator is deployed with cross-loop and square ring slots to design a dual-mode filter with a square perturbation element at its diagonal corner. The proposed filter exhibits compact size and favorable performance compared to other dual-mode filter works reported in literature. The aforementioned design of the dual-mode BPF at 4.76 GHz is suitable for applications in the lower part of the C-band.
{"title":"Compact dual-mode microstrip bandpass filter based on slotted square patch resonator","authors":"K. S., Zuvairiya Parveen J., Y. D., Venkadeshwari E.","doi":"10.1108/mi-08-2021-0080","DOIUrl":"https://doi.org/10.1108/mi-08-2021-0080","url":null,"abstract":"\u0000Purpose\u0000The purpose of this paper is to present the design of a compact microstrip bandpass filter (BPF) in dual-mode configuration loaded with cross-loop and square ring slots on a square patch resonator for C-band applications.\u0000\u0000\u0000Design/methodology/approach\u0000In the proposed design, the dual-mode response for the filter is realized with two transmission zeros (TZs) by the insertion of a perturbation element at the diagonal corner of the square patch resonator with orthogonal feed lines. Such TZs at the edges of the passband result in better selectivity for the proposed BPF. Moreover, the cross-loop and square ring slots are etched on a square patch resonator to obtain a miniaturized BPF.\u0000\u0000\u0000Findings\u0000The proposed dual-mode microstrip filter fabricated in RT/duroid 6010 substrate using PCB technology has a measured minimum insertion loss of 1.8 dB and return loss better than 24.5 dB with a fractional bandwidth (FBW) of 6.9%. A compact size of 7.35 × 7.35 mm2 is achieved for the slotted patch resonator-based dual-mode BPF at the center frequency of 4.76 GHz. As compared with the conventional square patch resonator, a size reduction of 61% is achieved with the proposed slotted design. The feasibility of the filter design is confirmed by the good agreement between the measured and simulated responses. The performance of the proposed filter structure is compared with other dual-mode filter works.\u0000\u0000\u0000Originality/value\u0000In the proposed work, a compact dual-mode BPF is reported with slotted structures. The conventional square patch resonator is deployed with cross-loop and square ring slots to design a dual-mode filter with a square perturbation element at its diagonal corner. The proposed filter exhibits compact size and favorable performance compared to other dual-mode filter works reported in literature. The aforementioned design of the dual-mode BPF at 4.76 GHz is suitable for applications in the lower part of the C-band.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2021-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49500122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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